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Merging r196588: ------------------------------------------------------------------------ r196588 | weimingz | 2013-12-06 09:56:48 -0800 (Fri, 06 Dec 2013) | 7 lines Bug 18149: [AArch32] VSel instructions has no ARMCC field The current peephole optimizing for compare inst assumes an instr that uses CPSR has an MO for ARM Cond code.However, for VSEL instructions (vseqeq, vselgt, vselgt, vselvs), there is no such operand nor do they support the modification of Cond Code. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196704 91177308-0d34-0410-b5e6-96231b3b80d8 Bill Wendling 6 years ago
2 changed file(s) with 94 addition(s) and 7 deletion(s). Raw diff Collapse all Expand all
23712371 isSafe = true;
23722372 break;
23732373 }
2374 // Condition code is after the operand before CPSR.
2375 ARMCC::CondCodes CC = (ARMCC::CondCodes)Instr.getOperand(IO-1).getImm();
2374 // Condition code is after the operand before CPSR except for VSELs.
2375 ARMCC::CondCodes CC;
2376 bool IsInstrVSel = true;
2377 switch (Instr.getOpcode()) {
2378 default:
2379 IsInstrVSel = false;
2380 CC = (ARMCC::CondCodes)Instr.getOperand(IO - 1).getImm();
2381 break;
2382 case ARM::VSELEQD:
2383 case ARM::VSELEQS:
2384 CC = ARMCC::EQ;
2385 break;
2386 case ARM::VSELGTD:
2387 case ARM::VSELGTS:
2388 CC = ARMCC::GT;
2389 break;
2390 case ARM::VSELGED:
2391 case ARM::VSELGES:
2392 CC = ARMCC::GE;
2393 break;
2394 case ARM::VSELVSS:
2395 case ARM::VSELVSD:
2396 CC = ARMCC::VS;
2397 break;
2398 }
2399
23762400 if (Sub) {
23772401 ARMCC::CondCodes NewCC = getSwappedCondition(CC);
23782402 if (NewCC == ARMCC::AL)
23832407 // If it is safe to remove CmpInstr, the condition code of these
23842408 // operands will be modified.
23852409 if (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
2386 Sub->getOperand(2).getReg() == SrcReg)
2387 OperandsToUpdate.push_back(std::make_pair(&((*I).getOperand(IO-1)),
2388 NewCC));
2389 }
2390 else
2410 Sub->getOperand(2).getReg() == SrcReg) {
2411 // VSel doesn't support condition code update.
2412 if (IsInstrVSel)
2413 return false;
2414 OperandsToUpdate.push_back(
2415 std::make_pair(&((*I).getOperand(IO - 1)), NewCC));
2416 }
2417 } else
23912418 switch (CC) {
23922419 default:
23932420 // CPSR can be used multiple times, we should continue.
0 ; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s
1 ; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s --check-prefix=V7
2 ; RUN: llc < %s -mtriple=armv8-none-linux-gnueabi | FileCheck %s -check-prefix=V8
3
14
25 define i32 @f(i32 %a, i32 %b) nounwind ssp {
36 entry:
8386 if.end11: ; preds = %num2long.exit
8487 ret i32 23
8588 }
89
90 define float @float_sel(i32 %a, i32 %b, float %x, float %y) {
91 entry:
92 ; CHECK-LABEL: float_sel:
93 ; CHECK-NOT: cmp
94 ; V8-LABEL: float_sel:
95 ; V8-NOT: cmp
96 ; V8: vseleq.f32
97 %sub = sub i32 %a, %b
98 %cmp = icmp eq i32 %sub, 0
99 %ret = select i1 %cmp, float %x, float %y
100 ret float %ret
101 }
102
103 define double @double_sel(i32 %a, i32 %b, double %x, double %y) {
104 entry:
105 ; CHECK-LABEL: double_sel:
106 ; CHECK-NOT: cmp
107 ; V8-LABEL: double_sel:
108 ; V8-NOT: cmp
109 ; V8: vseleq.f64
110 %sub = sub i32 %a, %b
111 %cmp = icmp eq i32 %sub, 0
112 %ret = select i1 %cmp, double %x, double %y
113 ret double %ret
114 }
115
116 @t = common global i32 0
117 define double @double_sub(i32 %a, i32 %b, double %x, double %y) {
118 entry:
119 ; CHECK-LABEL: double_sub:
120 ; CHECK: subs
121 ; CHECK-NOT: cmp
122 ; V8-LABEL: double_sub:
123 ; V8: vsel
124 %cmp = icmp sgt i32 %a, %b
125 %sub = sub i32 %a, %b
126 store i32 %sub, i32* @t
127 %ret = select i1 %cmp, double %x, double %y
128 ret double %ret
129 }
130
131 define double @double_sub_swap(i32 %a, i32 %b, double %x, double %y) {
132 entry:
133 ; V7-LABEL: double_sub_swap:
134 ; V7-NOT: cmp
135 ; V7: subs
136 ; V8-LABEL: double_sub_swap:
137 ; V8-NOT: subs
138 ; V8: cmp
139 ; V8: vsel
140 %cmp = icmp sgt i32 %a, %b
141 %sub = sub i32 %b, %a
142 %ret = select i1 %cmp, double %x, double %y
143 store i32 %sub, i32* @t
144 ret double %ret
145 }