llvm.org GIT mirror llvm / 2bd2c56
Teach the table generated emitPseudoExpansionLowering function to not emit a switch statement containing only a default statement (and no cases). Updated some of the code to use range-based for loops as well. No functional changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209521 91177308-0d34-0410-b5e6-96231b3b80d8 Aaron Ballman 5 years ago
1 changed file(s) with 65 addition(s) and 61 deletion(s). Raw diff Collapse all Expand all
199199
200200 o << "bool " << Target.getName() + "AsmPrinter" << "::\n"
201201 << "emitPseudoExpansionLowering(MCStreamer &OutStreamer,\n"
202 << " const MachineInstr *MI) {\n"
203 << " switch (MI->getOpcode()) {\n"
204 << " default: return false;\n";
205 for (unsigned i = 0, e = Expansions.size(); i != e; ++i) {
206 PseudoExpansion &Expansion = Expansions[i];
207 CodeGenInstruction &Source = Expansion.Source;
208 CodeGenInstruction &Dest = Expansion.Dest;
209 o << " case " << Source.Namespace << "::"
210 << Source.TheDef->getName() << ": {\n"
211 << " MCInst TmpInst;\n"
212 << " MCOperand MCOp;\n"
213 << " TmpInst.setOpcode(" << Dest.Namespace << "::"
214 << Dest.TheDef->getName() << ");\n";
215
216 // Copy the operands from the source instruction.
217 // FIXME: Instruction operands with defaults values (predicates and cc_out
218 // in ARM, for example shouldn't need explicit values in the
219 // expansion DAG.
220 unsigned MIOpNo = 0;
221 for (unsigned OpNo = 0, E = Dest.Operands.size(); OpNo != E;
222 ++OpNo) {
223 o << " // Operand: " << Dest.Operands[OpNo].Name << "\n";
224 for (unsigned i = 0, e = Dest.Operands[OpNo].MINumOperands;
225 i != e; ++i) {
226 switch (Expansion.OperandMap[MIOpNo + i].Kind) {
227 case OpData::Operand:
228 o << " lowerOperand(MI->getOperand("
229 << Source.Operands[Expansion.OperandMap[MIOpNo].Data
230 .Operand].MIOperandNo + i
231 << "), MCOp);\n"
232 << " TmpInst.addOperand(MCOp);\n";
233 break;
234 case OpData::Imm:
235 o << " TmpInst.addOperand(MCOperand::CreateImm("
236 << Expansion.OperandMap[MIOpNo + i].Data.Imm << "));\n";
237 break;
238 case OpData::Reg: {
239 Record *Reg = Expansion.OperandMap[MIOpNo + i].Data.Reg;
240 o << " TmpInst.addOperand(MCOperand::CreateReg(";
241 // "zero_reg" is special.
242 if (Reg->getName() == "zero_reg")
243 o << "0";
244 else
245 o << Reg->getValueAsString("Namespace") << "::" << Reg->getName();
246 o << "));\n";
247 break;
202 << " const MachineInstr *MI) {\n";
203
204 if (!Expansions.empty()) {
205 o << " switch (MI->getOpcode()) {\n"
206 << " default: return false;\n";
207 for (auto &Expansion : Expansions) {
208 CodeGenInstruction &Source = Expansion.Source;
209 CodeGenInstruction &Dest = Expansion.Dest;
210 o << " case " << Source.Namespace << "::"
211 << Source.TheDef->getName() << ": {\n"
212 << " MCInst TmpInst;\n"
213 << " MCOperand MCOp;\n"
214 << " TmpInst.setOpcode(" << Dest.Namespace << "::"
215 << Dest.TheDef->getName() << ");\n";
216
217 // Copy the operands from the source instruction.
218 // FIXME: Instruction operands with defaults values (predicates and cc_out
219 // in ARM, for example shouldn't need explicit values in the
220 // expansion DAG.
221 unsigned MIOpNo = 0;
222 for (const auto &DestOperand : Dest.Operands) {
223 o << " // Operand: " << DestOperand.Name << "\n";
224 for (unsigned i = 0, e = DestOperand.MINumOperands; i != e; ++i) {
225 switch (Expansion.OperandMap[MIOpNo + i].Kind) {
226 case OpData::Operand:
227 o << " lowerOperand(MI->getOperand("
228 << Source.Operands[Expansion.OperandMap[MIOpNo].Data
229 .Operand].MIOperandNo + i
230 << "), MCOp);\n"
231 << " TmpInst.addOperand(MCOp);\n";
232 break;
233 case OpData::Imm:
234 o << " TmpInst.addOperand(MCOperand::CreateImm("
235 << Expansion.OperandMap[MIOpNo + i].Data.Imm << "));\n";
236 break;
237 case OpData::Reg: {
238 Record *Reg = Expansion.OperandMap[MIOpNo + i].Data.Reg;
239 o << " TmpInst.addOperand(MCOperand::CreateReg(";
240 // "zero_reg" is special.
241 if (Reg->getName() == "zero_reg")
242 o << "0";
243 else
244 o << Reg->getValueAsString("Namespace") << "::"
245 << Reg->getName();
246 o << "));\n";
247 break;
248 }
249 }
248250 }
249 }
251 MIOpNo += DestOperand.MINumOperands;
250252 }
251 MIOpNo += Dest.Operands[OpNo].MINumOperands;
253 if (Dest.Operands.isVariadic) {
254 MIOpNo = Source.Operands.size() + 1;
255 o << " // variable_ops\n";
256 o << " for (unsigned i = " << MIOpNo
257 << ", e = MI->getNumOperands(); i != e; ++i)\n"
258 << " if (lowerOperand(MI->getOperand(i), MCOp))\n"
259 << " TmpInst.addOperand(MCOp);\n";
260 }
261 o << " EmitToStreamer(OutStreamer, TmpInst);\n"
262 << " break;\n"
263 << " }\n";
252264 }
253 if (Dest.Operands.isVariadic) {
254 MIOpNo = Source.Operands.size() + 1;
255 o << " // variable_ops\n";
256 o << " for (unsigned i = " << MIOpNo
257 << ", e = MI->getNumOperands(); i != e; ++i)\n"
258 << " if (lowerOperand(MI->getOperand(i), MCOp))\n"
259 << " TmpInst.addOperand(MCOp);\n";
260 }
261 o << " EmitToStreamer(OutStreamer, TmpInst);\n"
262 << " break;\n"
263 << " }\n";
264 }
265 o << " }\n return true;\n}\n\n";
265 o << " }\n return true;";
266 } else
267 o << " return false;";
268
269 o << "\n}\n\n";
266270 }
267271
268272 void PseudoLoweringEmitter::run(raw_ostream &o) {