llvm.org GIT mirror llvm / 2ba62ef
Unbreak getOnesVector() / getZeroVector() to use valid ARM extended imm's. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81262 91177308-0d34-0410-b5e6-96231b3b80d8 Anton Korobeynikov 10 years ago
3 changed file(s) with 43 addition(s) and 19 deletion(s). Raw diff Collapse all Expand all
20852085 // will be implemented with the NEON VNEG instruction. However, VNEG does
20862086 // not support i64 elements, so sometimes the zero vectors will need to be
20872087 // explicitly constructed. For those cases, and potentially other uses in
2088 // the future, always build zero vectors as <4 x i32> or <2 x i32> bitcasted
2088 // the future, always build zero vectors as <16 x i8> or <8 x i8> bitcasted
20892089 // to their dest type. This ensures they get CSE'd.
20902090 SDValue Vec;
2091 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
2092 if (VT.getSizeInBits() == 64)
2093 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
2094 else
2095 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
2091 SDValue Cst = DAG.getTargetConstant(0, MVT::i8);
2092 SmallVector Ops;
2093 MVT TVT;
2094
2095 if (VT.getSizeInBits() == 64) {
2096 Ops.assign(8, Cst); TVT = MVT::v8i8;
2097 } else {
2098 Ops.assign(16, Cst); TVT = MVT::v16i8;
2099 }
2100 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, TVT, &Ops[0], Ops.size());
20962101
20972102 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
20982103 }
21022107 static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
21032108 assert(VT.isVector() && "Expected a vector type");
21042109
2105 // Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest
2106 // type. This ensures they get CSE'd.
2110 // Always build ones vectors as <16 x i32> or <8 x i32> bitcasted to their
2111 // dest type. This ensures they get CSE'd.
21072112 SDValue Vec;
2108 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
2109 if (VT.getSizeInBits() == 64)
2110 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
2111 else
2112 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
2113 SDValue Cst = DAG.getTargetConstant(0xFF, MVT::i8);
2114 SmallVector Ops;
2115 MVT TVT;
2116
2117 if (VT.getSizeInBits() == 64) {
2118 Ops.assign(8, Cst); TVT = MVT::v8i8;
2119 } else {
2120 Ops.assign(16, Cst); TVT = MVT::v16i8;
2121 }
2122 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, TVT, &Ops[0], Ops.size());
21132123
21142124 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
21152125 }
15991599 def VBICd : N3V<0, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst),
16001600 (ins DPR:$src1, DPR:$src2), NoItinerary,
16011601 "vbic\t$dst, $src1, $src2", "",
1602 [(set DPR:$dst, (v2i32 (and DPR:$src1,(vnot DPR:$src2))))]>;
1602 [(set DPR:$dst, (v2i32 (and DPR:$src1,
1603 (vnot_conv DPR:$src2))))]>;
16031604 def VBICq : N3V<0, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst),
16041605 (ins QPR:$src1, QPR:$src2), NoItinerary,
16051606 "vbic\t$dst, $src1, $src2", "",
1606 [(set QPR:$dst, (v4i32 (and QPR:$src1,(vnot QPR:$src2))))]>;
1607 [(set QPR:$dst, (v4i32 (and QPR:$src1,
1608 (vnot_conv QPR:$src2))))]>;
16071609
16081610 // VORN : Vector Bitwise OR NOT
16091611 def VORNd : N3V<0, 0, 0b11, 0b0001, 0, 1, (outs DPR:$dst),
16101612 (ins DPR:$src1, DPR:$src2), NoItinerary,
16111613 "vorn\t$dst, $src1, $src2", "",
1612 [(set DPR:$dst, (v2i32 (or DPR:$src1, (vnot DPR:$src2))))]>;
1614 [(set DPR:$dst, (v2i32 (or DPR:$src1,
1615 (vnot_conv DPR:$src2))))]>;
16131616 def VORNq : N3V<0, 0, 0b11, 0b0001, 1, 1, (outs QPR:$dst),
16141617 (ins QPR:$src1, QPR:$src2), NoItinerary,
16151618 "vorn\t$dst, $src1, $src2", "",
1616 [(set QPR:$dst, (v4i32 (or QPR:$src1, (vnot QPR:$src2))))]>;
1619 [(set QPR:$dst, (v4i32 (or QPR:$src1,
1620 (vnot_conv QPR:$src2))))]>;
16171621
16181622 // VMVN : Vector Bitwise NOT
16191623 def VMVNd : N2V<0b11, 0b11, 0b00, 0b00, 0b01011, 0, 0,
16331637 "vbsl\t$dst, $src2, $src3", "$src1 = $dst",
16341638 [(set DPR:$dst,
16351639 (v2i32 (or (and DPR:$src2, DPR:$src1),
1636 (and DPR:$src3, (vnot DPR:$src1)))))]>;
1640 (and DPR:$src3, (vnot_conv DPR:$src1)))))]>;
16371641 def VBSLq : N3V<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst),
16381642 (ins QPR:$src1, QPR:$src2, QPR:$src3), NoItinerary,
16391643 "vbsl\t$dst, $src2, $src3", "$src1 = $dst",
16401644 [(set QPR:$dst,
16411645 (v4i32 (or (and QPR:$src2, QPR:$src1),
1642 (and QPR:$src3, (vnot QPR:$src1)))))]>;
1646 (and QPR:$src3, (vnot_conv QPR:$src1)))))]>;
16431647
16441648 // VBIF : Vector Bitwise Insert if False
16451649 // like VBSL but with: "vbif\t$dst, $src3, $src1", "$src2 = $dst",
0 ; RUN: llc -mattr=+neon < %s
1 target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32"
2 target triple = "thumbv7-elf"
3
4 define arm_apcscc void @foo() {
5 entry:
6 %0 = insertelement <4 x i32> undef, i32 -1, i32 3
7 store <4 x i32> %0, <4 x i32>* undef, align 16
8 unreachable
9 }