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Reverting r229831 due to multiple ARM/PPC/MIPS build-bot failures. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229841 91177308-0d34-0410-b5e6-96231b3b80d8 Michael Kuperstein 5 years ago
33 changed file(s) with 346 addition(s) and 374 deletion(s). Raw diff Collapse all Expand all
99 #ifndef LLVM_MC_MCINSTPRINTER_H
1010 #define LLVM_MC_MCINSTPRINTER_H
1111
12 #include "llvm/MC/SubtargetFeature.h"
1312 #include "llvm/Support/DataTypes.h"
1413 #include "llvm/Support/Format.h"
1514
4140 const MCRegisterInfo &MRI;
4241
4342 /// The current set of available features.
44 FeatureBitset AvailableFeatures;
43 uint64_t AvailableFeatures;
4544
4645 /// True if we are printing marked up assembly.
4746 bool UseMarkup;
5857 MCInstPrinter(const MCAsmInfo &mai, const MCInstrInfo &mii,
5958 const MCRegisterInfo &mri)
6059 : CommentStream(nullptr), MAI(mai), MII(mii), MRI(mri),
61 AvailableFeatures(), UseMarkup(0), PrintImmHex(0),
60 AvailableFeatures(0), UseMarkup(0), PrintImmHex(0),
6261 PrintHexStyle(HexStyle::C) {}
6362
6463 virtual ~MCInstPrinter();
7877 /// printRegName - Print the assembler register name.
7978 virtual void printRegName(raw_ostream &OS, unsigned RegNo) const;
8079
81 const FeatureBitset& getAvailableFeatures() const { return AvailableFeatures; }
82 void setAvailableFeatures(const FeatureBitset& Value) { AvailableFeatures = Value; }
80 uint64_t getAvailableFeatures() const { return AvailableFeatures; }
81 void setAvailableFeatures(uint64_t Value) { AvailableFeatures = Value; }
8382
8483 bool getUseMarkup() const { return UseMarkup; }
8584 void setUseMarkup(bool Value) { UseMarkup = Value; }
149149 const uint16_t *ImplicitUses; // Registers implicitly read by this instr
150150 const uint16_t *ImplicitDefs; // Registers implicitly defined by this instr
151151 const MCOperandInfo *OpInfo; // 'NumOperands' entries about operands
152 FeatureBitset DeprecatedFeatureMask; // Feature bits that this is deprecated on, if any
152 uint64_t DeprecatedFeatureMask;// Feature bits that this is deprecated on, if any
153153 // A complex method to determine is a certain is deprecated or not, and return
154154 // the reason for deprecation.
155155 bool (*ComplexDeprecationInfo)(MCInst &, MCSubtargetInfo &, std::string &);
172172 std::string &Info) const {
173173 if (ComplexDeprecationInfo)
174174 return ComplexDeprecationInfo(MI, STI, Info);
175 if ((STI.getFeatureBits() & DeprecatedFeatureMask).any()) {
175 if ((DeprecatedFeatureMask & STI.getFeatureBits()) != 0) {
176176 // FIXME: it would be nice to include the subtarget feature here.
177177 Info = "deprecated";
178178 return true;
4141 const InstrStage *Stages; // Instruction itinerary stages
4242 const unsigned *OperandCycles; // Itinerary operand cycles
4343 const unsigned *ForwardingPaths; // Forwarding paths
44 FeatureBitset FeatureBits; // Feature bits for current CPU + FS
44 uint64_t FeatureBits; // Feature bits for current CPU + FS
4545
4646 public:
4747 void InitMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS,
6666
6767 /// getFeatureBits - Return the feature bits.
6868 ///
69 const FeatureBitset& getFeatureBits() const {
69 uint64_t getFeatureBits() const {
7070 return FeatureBits;
7171 }
7272
7373 /// setFeatureBits - Set the feature bits.
7474 ///
75 void setFeatureBits(FeatureBitset& FeatureBits_) { FeatureBits = FeatureBits_; }
75 void setFeatureBits(uint64_t FeatureBits_) { FeatureBits = FeatureBits_; }
7676
7777 /// InitMCProcessorInfo - Set or change the CPU (optionally supplemented with
7878 /// feature string). Recompute feature bits and scheduling model.
8383
8484 /// ToggleFeature - Toggle a feature and returns the re-computed feature
8585 /// bits. This version does not change the implied bits.
86 FeatureBitset ToggleFeature(uint64_t FB);
86 uint64_t ToggleFeature(uint64_t FB);
8787
8888 /// ToggleFeature - Toggle a feature and returns the re-computed feature
89 /// bits. This version does not change the implied bits.
90 FeatureBitset ToggleFeature(const FeatureBitset& FB);
91
92 /// ToggleFeature - Toggle a set of features and returns the re-computed
93 /// feature bits. This version will also change all implied bits.
94 FeatureBitset ToggleFeature(StringRef FS);
89 /// bits. This version will also change all implied bits.
90 uint64_t ToggleFeature(StringRef FS);
9591
9692 /// getSchedModelForCPU - Get the machine model of a CPU.
9793 ///
2020 #include "llvm/ADT/ArrayRef.h"
2121 #include "llvm/ADT/Triple.h"
2222 #include "llvm/Support/DataTypes.h"
23 #include
2423
2524 namespace llvm {
2625 class raw_ostream;
2726 class StringRef;
28
29 // A container class for subtarget features.
30 // This is convenient because std::bitset does not have a constructor
31 // with an initializer list of set bits.
32 const unsigned MAX_SUBTARGET_FEATURES = 64;
33 class FeatureBitset : public std::bitset {
34 public:
35 // Cannot inherit constructors because it's not supported by VC++..
36 FeatureBitset() : bitset() {}
37
38 FeatureBitset(const bitset& B) : bitset(B) {}
39
40 FeatureBitset(std::initializer_list Init) : bitset() {
41 for (auto I = Init.begin() , E = Init.end(); I != E; ++I)
42 set(*I);
43 }
44 };
4527
4628 //===----------------------------------------------------------------------===//
4729 ///
5133 struct SubtargetFeatureKV {
5234 const char *Key; // K-V key string
5335 const char *Desc; // Help descriptor
54 FeatureBitset Value; // K-V integer value
55 FeatureBitset Implies; // K-V bit mask
36 uint64_t Value; // K-V integer value
37 uint64_t Implies; // K-V bit mask
5638
5739 // Compare routine for std::lower_bound
5840 bool operator<(StringRef S) const {
9981
10082 /// ToggleFeature - Toggle a feature and returns the newly updated feature
10183 /// bits.
102 FeatureBitset ToggleFeature(FeatureBitset Bits, StringRef String,
84 uint64_t ToggleFeature(uint64_t Bits, StringRef String,
10385 ArrayRef FeatureTable);
10486
10587 /// Get feature bits of a CPU.
106 FeatureBitset getFeatureBits(StringRef CPU,
88 uint64_t getFeatureBits(StringRef CPU,
10789 ArrayRef CPUTable,
10890 ArrayRef FeatureTable);
10991
6262
6363 /// ToggleFeature - Toggle a feature and returns the re-computed feature
6464 /// bits. This version does not change the implied bits.
65 FeatureBitset MCSubtargetInfo::ToggleFeature(uint64_t FB) {
66 FeatureBits.flip(FB);
67 return FeatureBits;
68 }
69
70 FeatureBitset MCSubtargetInfo::ToggleFeature(const FeatureBitset &FB) {
65 uint64_t MCSubtargetInfo::ToggleFeature(uint64_t FB) {
7166 FeatureBits ^= FB;
7267 return FeatureBits;
7368 }
7469
7570 /// ToggleFeature - Toggle a feature and returns the re-computed feature
7671 /// bits. This version will also change all implied bits.
77 FeatureBitset MCSubtargetInfo::ToggleFeature(StringRef FS) {
72 uint64_t MCSubtargetInfo::ToggleFeature(StringRef FS) {
7873 SubtargetFeatures Features;
7974 FeatureBits = Features.ToggleFeature(FeatureBits, FS, ProcFeatures);
8075 return FeatureBits;
149149 /// feature, set it.
150150 ///
151151 static
152 void SetImpliedBits(FeatureBitset &Bits, const SubtargetFeatureKV *FeatureEntry,
152 void SetImpliedBits(uint64_t &Bits, const SubtargetFeatureKV *FeatureEntry,
153153 ArrayRef FeatureTable) {
154154 for (auto &FE : FeatureTable) {
155155 if (FeatureEntry->Value == FE.Value) continue;
156156
157 if ((FeatureEntry->Implies & FE.Value).any()) {
157 if (FeatureEntry->Implies & FE.Value) {
158158 Bits |= FE.Value;
159159 SetImpliedBits(Bits, &FE, FeatureTable);
160160 }
165165 /// feature, clear it.
166166 ///
167167 static
168 void ClearImpliedBits(FeatureBitset &Bits,
169 const SubtargetFeatureKV *FeatureEntry,
168 void ClearImpliedBits(uint64_t &Bits, const SubtargetFeatureKV *FeatureEntry,
170169 ArrayRef FeatureTable) {
171170 for (auto &FE : FeatureTable) {
172171 if (FeatureEntry->Value == FE.Value) continue;
173172
174 if ((FE.Implies & FeatureEntry->Value).any()) {
173 if (FE.Implies & FeatureEntry->Value) {
175174 Bits &= ~FE.Value;
176175 ClearImpliedBits(Bits, &FE, FeatureTable);
177176 }
180179
181180 /// ToggleFeature - Toggle a feature and returns the newly updated feature
182181 /// bits.
183 FeatureBitset
184 SubtargetFeatures::ToggleFeature(FeatureBitset Bits, StringRef Feature,
182 uint64_t
183 SubtargetFeatures::ToggleFeature(uint64_t Bits, StringRef Feature,
185184 ArrayRef FeatureTable) {
186185
187186 // Find feature in table.
191190 if (FeatureEntry) {
192191 if ((Bits & FeatureEntry->Value) == FeatureEntry->Value) {
193192 Bits &= ~FeatureEntry->Value;
193
194194 // For each feature that implies this, clear it.
195195 ClearImpliedBits(Bits, FeatureEntry, FeatureTable);
196196 } else {
211211
212212 /// getFeatureBits - Get feature bits a CPU.
213213 ///
214 FeatureBitset
214 uint64_t
215215 SubtargetFeatures::getFeatureBits(StringRef CPU,
216216 ArrayRef CPUTable,
217217 ArrayRef FeatureTable) {
218218
219219 if (CPUTable.empty() || FeatureTable.empty())
220 return FeatureBitset();
220 return 0;
221221
222222 #ifndef NDEBUG
223223 for (size_t i = 1, e = CPUTable.size(); i != e; ++i) {
229229 "CPU features table is not sorted");
230230 }
231231 #endif
232 // Resulting bits
233 FeatureBitset Bits;
232 uint64_t Bits = 0; // Resulting bits
234233
235234 // Check if help is needed
236235 if (CPU == "help")
247246
248247 // Set the feature implied by this CPU feature, if any.
249248 for (auto &FE : FeatureTable) {
250 if ((CPUEntry->Value & FE.Value).any())
249 if (CPUEntry->Value & FE.Value)
251250 SetImpliedBits(Bits, &FE, FeatureTable);
252251 }
253252 } else {
1313 #include "llvm/ADT/APFloat.h"
1414 #include "llvm/ADT/SmallVector.h"
1515 #include "llvm/ADT/StringExtras.h"
16 #include "llvm/MC/SubtargetFeature.h"
1716 #include "llvm/Support/Regex.h"
1817
1918 using namespace llvm;
245244 {"ich_elsr_el2", ICH_ELSR_EL2}
246245 };
247246
248 AArch64SysReg::MRSMapper::MRSMapper(const FeatureBitset &FeatureBits)
247 AArch64SysReg::MRSMapper::MRSMapper(uint64_t FeatureBits)
249248 : SysRegMapper(FeatureBits) {
250249 InstPairs = &MRSPairs[0];
251250 NumInstPairs = llvm::array_lengthof(MRSPairs);
269268 {"icc_sgi0r_el1", ICC_SGI0R_EL1}
270269 };
271270
272 AArch64SysReg::MSRMapper::MSRMapper(const FeatureBitset &FeatureBits)
271 AArch64SysReg::MSRMapper::MSRMapper(uint64_t FeatureBits)
273272 : SysRegMapper(FeatureBits) {
274273 InstPairs = &MSRPairs[0];
275274 NumInstPairs = llvm::array_lengthof(MSRPairs);
773772 }
774773
775774 // Next search for target specific registers
776 if (FeatureBits[AArch64::ProcCyclone]) {
775 if (FeatureBits & AArch64::ProcCyclone) {
777776 for (unsigned i = 0; i < array_lengthof(CycloneSysRegPairs); ++i) {
778777 if (CycloneSysRegPairs[i].Name == NameLower) {
779778 Valid = true;
823822 }
824823
825824 // Next search for target specific registers
826 if (FeatureBits[AArch64::ProcCyclone]) {
825 if (FeatureBits & AArch64::ProcCyclone) {
827826 for (unsigned i = 0; i < array_lengthof(CycloneSysRegPairs); ++i) {
828827 if (CycloneSysRegPairs[i].Value == Bits) {
829828 return CycloneSysRegPairs[i].Name;
2424 #include "llvm/Support/ErrorHandling.h"
2525
2626 namespace llvm {
27
28 class FeatureBitset;
2927
3028 inline static unsigned getWRegFromXReg(unsigned Reg) {
3129 switch (Reg) {
11401138
11411139 const AArch64NamedImmMapper::Mapping *InstPairs;
11421140 size_t NumInstPairs;
1143 const FeatureBitset &FeatureBits;
1144
1145 SysRegMapper(const FeatureBitset &FeatureBits) : FeatureBits(FeatureBits) { }
1141 uint64_t FeatureBits;
1142
1143 SysRegMapper(uint64_t FeatureBits) : FeatureBits(FeatureBits) { }
11461144 uint32_t fromString(StringRef Name, bool &Valid) const;
11471145 std::string toString(uint32_t Bits) const;
11481146 };
11491147
11501148 struct MSRMapper : SysRegMapper {
11511149 static const AArch64NamedImmMapper::Mapping MSRPairs[];
1152 MSRMapper(const FeatureBitset &FeatureBits);
1150 MSRMapper(uint64_t FeatureBits);
11531151 };
11541152
11551153 struct MRSMapper : SysRegMapper {
11561154 static const AArch64NamedImmMapper::Mapping MRSPairs[];
1157 MRSMapper(const FeatureBitset &FeatureBits);
1155 MRSMapper(uint64_t FeatureBits);
11581156 };
11591157
11601158 uint32_t ParseGenericRegister(StringRef Name, bool &Valid);
421421 }
422422
423423 static bool isThumb(const MCSubtargetInfo& STI) {
424 return STI.getFeatureBits()[ARM::ModeThumb];
424 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
425425 }
426426
427427 void ARMAsmPrinter::emitInlineAsmEnd(const MCSubtargetInfo &StartInfo,
45064506 }
45074507
45084508 bool ARMBaseInstrInfo::hasNOP() const {
4509 return Subtarget.getFeatureBits()[ARM::HasV6T2Ops];
4509 return (Subtarget.getFeatureBits() & ARM::HasV6T2Ops) != 0;
45104510 }
45114511
45124512 bool ARMBaseInstrInfo::isSwiftFastImmShift(const MachineInstr *MI) const {
261261 }
262262
263263 // NEON f32 ops are non-IEEE 754 compliant. Darwin is ok with it by default.
264 const FeatureBitset &Bits = getFeatureBits();
265 if ((Bits[ARM::ProcA5] || Bits[ARM::ProcA8]) && // Where this matters
264 uint64_t Bits = getFeatureBits();
265 if ((Bits & ARM::ProcA5 || Bits & ARM::ProcA8) && // Where this matters
266266 (Options.UnsafeFPMath || isTargetDarwin()))
267267 UseNEONForSinglePrecisionFP = true;
268268 }
243243
244244 bool isThumb() const {
245245 // FIXME: Can tablegen auto-generate this?
246 return STI.getFeatureBits()[ARM::ModeThumb];
246 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
247247 }
248248 bool isThumbOne() const {
249 return isThumb() && !STI.getFeatureBits()[ARM::FeatureThumb2];
249 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
250250 }
251251 bool isThumbTwo() const {
252 return isThumb() && STI.getFeatureBits()[ARM::FeatureThumb2];
252 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
253253 }
254254 bool hasThumb() const {
255 return STI.getFeatureBits()[ARM::HasV4TOps];
255 return STI.getFeatureBits() & ARM::HasV4TOps;
256256 }
257257 bool hasV6Ops() const {
258 return STI.getFeatureBits()[ARM::HasV6Ops];
258 return STI.getFeatureBits() & ARM::HasV6Ops;
259259 }
260260 bool hasV6MOps() const {
261 return STI.getFeatureBits()[ARM::HasV6MOps];
261 return STI.getFeatureBits() & ARM::HasV6MOps;
262262 }
263263 bool hasV7Ops() const {
264 return STI.getFeatureBits()[ARM::HasV7Ops];
264 return STI.getFeatureBits() & ARM::HasV7Ops;
265265 }
266266 bool hasV8Ops() const {
267 return STI.getFeatureBits()[ARM::HasV8Ops];
267 return STI.getFeatureBits() & ARM::HasV8Ops;
268268 }
269269 bool hasARM() const {
270 return !STI.getFeatureBits()[ARM::FeatureNoARM];
270 return !(STI.getFeatureBits() & ARM::FeatureNoARM);
271271 }
272272 bool hasThumb2DSP() const {
273 return STI.getFeatureBits()[ARM::FeatureDSPThumb2];
273 return STI.getFeatureBits() & ARM::FeatureDSPThumb2;
274274 }
275275 bool hasD16() const {
276 return STI.getFeatureBits()[ARM::FeatureD16];
276 return STI.getFeatureBits() & ARM::FeatureD16;
277277 }
278278
279279 void SwitchMode() {
281281 setAvailableFeatures(FB);
282282 }
283283 bool isMClass() const {
284 return STI.getFeatureBits()[ARM::FeatureMClass];
284 return STI.getFeatureBits() & ARM::FeatureMClass;
285285 }
286286
287287 /// @name Auto-generated Match Functions
91859185 // tools/clang/lib/Driver/Tools.cpp
91869186 static const struct {
91879187 const unsigned ID;
9188 const FeatureBitset Enabled;
9189 const FeatureBitset Disabled;
9188 const uint64_t Enabled;
9189 const uint64_t Disabled;
91909190 } FPUs[] = {
9191 {/* ID */ ARM::VFP,
9192 /* Enabled */ {ARM::FeatureVFP2},
9193 /* Disabled */ {ARM::FeatureNEON}},
9194 {/* ID */ ARM::VFPV2,
9195 /* Enabled */ {ARM::FeatureVFP2},
9196 /* Disabled */ {ARM::FeatureNEON}},
9197 {/* ID */ ARM::VFPV3,
9198 /* Enabled */ {ARM::FeatureVFP2, ARM::FeatureVFP3},
9199 /* Disabled */ {ARM::FeatureNEON, ARM::FeatureD16}},
9200 {/* ID */ ARM::VFPV3_D16,
9201 /* Enabled */ {ARM::FeatureVFP2, ARM::FeatureVFP3, ARM::FeatureD16},
9202 /* Disabled */ {ARM::FeatureNEON}},
9203 {/* ID */ ARM::VFPV4,
9204 /* Enabled */ {ARM::FeatureVFP2, ARM::FeatureVFP3, ARM::FeatureVFP4},
9205 /* Disabled */ {ARM::FeatureNEON, ARM::FeatureD16}},
9206 {/* ID */ ARM::VFPV4_D16,
9207 /* Enabled */ {ARM::FeatureVFP2, ARM::FeatureVFP3, ARM::FeatureVFP4,
9208 ARM::FeatureD16},
9209 /* Disabled */ {ARM::FeatureNEON}},
9210 {/* ID */ ARM::FPV5_D16,
9211 /* Enabled */ {ARM::FeatureVFP2, ARM::FeatureVFP3, ARM::FeatureVFP4,
9212 ARM::FeatureFPARMv8, ARM::FeatureD16},
9213 /* Disabled */ {ARM::FeatureNEON, ARM::FeatureCrypto}},
9214 {/* ID */ ARM::FP_ARMV8,
9215 /* Enabled */ {ARM::FeatureVFP2, ARM::FeatureVFP3, ARM::FeatureVFP4,
9216 ARM::FeatureFPARMv8},
9217 /* Disabled */ {ARM::FeatureNEON, ARM::FeatureCrypto, ARM::FeatureD16}},
9218 {/* ID */ ARM::NEON,
9219 /* Enabled */ {ARM::FeatureVFP2, ARM::FeatureVFP3, ARM::FeatureNEON},
9220 /* Disabled */ {ARM::FeatureD16}},
9221 {/* ID */ ARM::NEON_VFPV4,
9222 /* Enabled */ {ARM::FeatureVFP2, ARM::FeatureVFP3, ARM::FeatureVFP4,
9223 ARM::FeatureNEON},
9224 /* Disabled */ {ARM::FeatureD16}},
9225 {/* ID */ ARM::NEON_FP_ARMV8,
9226 /* Enabled */ {ARM::FeatureVFP2, ARM::FeatureVFP3, ARM::FeatureVFP4,
9227 ARM::FeatureFPARMv8, ARM::FeatureNEON},
9228 /* Disabled */ {ARM::FeatureCrypto, ARM::FeatureD16}},
9229 {/* ID */ ARM::CRYPTO_NEON_FP_ARMV8,
9230 /* Enabled */ {ARM::FeatureVFP2, ARM::FeatureVFP3, ARM::FeatureVFP4,
9231 ARM::FeatureFPARMv8, ARM::FeatureNEON,
9232 ARM::FeatureCrypto},
9233 /* Disabled */ {ARM::FeatureD16}},
9234 {ARM::SOFTVFP, {}, {}},
9191 {/* ID */ ARM::VFP,
9192 /* Enabled */ ARM::FeatureVFP2,
9193 /* Disabled */ ARM::FeatureNEON},
9194 {/* ID */ ARM::VFPV2,
9195 /* Enabled */ ARM::FeatureVFP2,
9196 /* Disabled */ ARM::FeatureNEON},
9197 {/* ID */ ARM::VFPV3,
9198 /* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3,
9199 /* Disabled */ ARM::FeatureNEON | ARM::FeatureD16},
9200 {/* ID */ ARM::VFPV3_D16,
9201 /* Enable */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureD16,
9202 /* Disabled */ ARM::FeatureNEON},
9203 {/* ID */ ARM::VFPV4,
9204 /* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureVFP4,
9205 /* Disabled */ ARM::FeatureNEON | ARM::FeatureD16},
9206 {/* ID */ ARM::VFPV4_D16,
9207 /* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureVFP4 |
9208 ARM::FeatureD16,
9209 /* Disabled */ ARM::FeatureNEON},
9210 {/* ID */ ARM::FPV5_D16,
9211 /* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureVFP4 |
9212 ARM::FeatureFPARMv8 | ARM::FeatureD16,
9213 /* Disabled */ ARM::FeatureNEON | ARM::FeatureCrypto},
9214 {/* ID */ ARM::FP_ARMV8,
9215 /* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureVFP4 |
9216 ARM::FeatureFPARMv8,
9217 /* Disabled */ ARM::FeatureNEON | ARM::FeatureCrypto | ARM::FeatureD16},
9218 {/* ID */ ARM::NEON,
9219 /* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureNEON,
9220 /* Disabled */ ARM::FeatureD16},
9221 {/* ID */ ARM::NEON_VFPV4,
9222 /* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureVFP4 |
9223 ARM::FeatureNEON,
9224 /* Disabled */ ARM::FeatureD16},
9225 {/* ID */ ARM::NEON_FP_ARMV8,
9226 /* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureVFP4 |
9227 ARM::FeatureFPARMv8 | ARM::FeatureNEON,
9228 /* Disabled */ ARM::FeatureCrypto | ARM::FeatureD16},
9229 {/* ID */ ARM::CRYPTO_NEON_FP_ARMV8,
9230 /* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureVFP4 |
9231 ARM::FeatureFPARMv8 | ARM::FeatureNEON | ARM::FeatureCrypto,
9232 /* Disabled */ ARM::FeatureD16},
9233 {ARM::SOFTVFP, 0, 0},
92359234 };
92369235
92379236 /// parseDirectiveFPU
92569255
92579256 // Need to toggle features that should be on but are off and that
92589257 // should off but are on.
9259 FeatureBitset Toggle = (Entry.Enabled & ~STI.getFeatureBits()) |
9260 (Entry.Disabled & STI.getFeatureBits());
9258 uint64_t Toggle = (Entry.Enabled & ~STI.getFeatureBits()) |
9259 (Entry.Disabled & STI.getFeatureBits());
92619260 setAvailableFeatures(ComputeAvailableFeatures(STI.ToggleFeature(Toggle)));
92629261 break;
92639262 }
99949993 static const struct {
99959994 const char *Name;
99969995 const unsigned ArchCheck;
9997 const FeatureBitset Features;
9996 const uint64_t Features;
99989997 } Extensions[] = {
9999 { "crc", Feature_HasV8, {ARM::FeatureCRC} },
9998 { "crc", Feature_HasV8, ARM::FeatureCRC },
100009999 { "crypto", Feature_HasV8,
10001 {ARM::FeatureCrypto, ARM::FeatureNEON, ARM::FeatureFPARMv8} },
10002 { "fp", Feature_HasV8, {ARM::FeatureFPARMv8} },
10000 ARM::FeatureCrypto | ARM::FeatureNEON | ARM::FeatureFPARMv8 },
10001 { "fp", Feature_HasV8, ARM::FeatureFPARMv8 },
1000310002 { "idiv", Feature_HasV7 | Feature_IsNotMClass,
10004 {ARM::FeatureHWDiv, ARM::FeatureHWDivARM} },
10003 ARM::FeatureHWDiv | ARM::FeatureHWDivARM },
1000510004 // FIXME: iWMMXT not supported
10006 { "iwmmxt", Feature_None, {} },
10005 { "iwmmxt", Feature_None, 0 },
1000710006 // FIXME: iWMMXT2 not supported
10008 { "iwmmxt2", Feature_None, {} },
10007 { "iwmmxt2", Feature_None, 0 },
1000910008 // FIXME: Maverick not supported
10010 { "maverick", Feature_None, {} },
10011 { "mp", Feature_HasV7 | Feature_IsNotMClass, {ARM::FeatureMP} },
10009 { "maverick", Feature_None, 0 },
10010 { "mp", Feature_HasV7 | Feature_IsNotMClass, ARM::FeatureMP },
1001210011 // FIXME: ARMv6-m OS Extensions feature not checked
10013 { "os", Feature_None, {} },
10012 { "os", Feature_None, 0 },
1001410013 // FIXME: Also available in ARMv6-K
10015 { "sec", Feature_HasV7, {ARM::FeatureTrustZone} },
10016 { "simd", Feature_HasV8, {ARM::FeatureNEON, ARM::FeatureFPARMv8} },
10014 { "sec", Feature_HasV7, ARM::FeatureTrustZone },
10015 { "simd", Feature_HasV8, ARM::FeatureNEON | ARM::FeatureFPARMv8 },
1001710016 // FIXME: Only available in A-class, isel not predicated
10018 { "virt", Feature_HasV7, {ARM::FeatureVirtualization} },
10017 { "virt", Feature_HasV7, ARM::FeatureVirtualization },
1001910018 // FIXME: xscale not supported
10020 { "xscale", Feature_None, {} },
10019 { "xscale", Feature_None, 0 },
1002110020 };
1002210021
1002310022 /// parseDirectiveArchExtension
1004510044 if (Extension.Name != Name)
1004610045 continue;
1004710046
10048 if (Extension.Features.none())
10047 if (!Extension.Features)
1004910048 report_fatal_error("unsupported architectural extension: " + Name);
1005010049
1005110050 if ((getAvailableFeatures() & Extension.ArchCheck) != Extension.ArchCheck) {
1005410053 return false;
1005510054 }
1005610055
10057 FeatureBitset ToggleFeatures = EnableFeature
10058 ? (~STI.getFeatureBits() & Extension.Features)
10059 : ( STI.getFeatureBits() & Extension.Features);
10060
10056 uint64_t ToggleFeatures = EnableFeature
10057 ? (~STI.getFeatureBits() & Extension.Features)
10058 : ( STI.getFeatureBits() & Extension.Features);
1006110059 uint64_t Features =
1006210060 ComputeAvailableFeatures(STI.ToggleFeature(ToggleFeatures));
1006310061 setAvailableFeatures(Features);
430430 raw_ostream &CS) const {
431431 CommentStream = &CS;
432432
433 assert(!STI.getFeatureBits()[ARM::ModeThumb] &&
433 assert(!(STI.getFeatureBits() & ARM::ModeThumb) &&
434434 "Asked to disassemble an ARM instruction but Subtarget is in Thumb "
435435 "mode!");
436436
695695 raw_ostream &CS) const {
696696 CommentStream = &CS;
697697
698 assert(STI.getFeatureBits()[ARM::ModeThumb] &&
698 assert((STI.getFeatureBits() & ARM::ModeThumb) &&
699699 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
700700
701701 // We want to read exactly 2 bytes of data.
10211021
10221022 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
10231023 uint64_t Address, const void *Decoder) {
1024 const FeatureBitset &featureBits =
1025 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
1026
1027 bool hasD16 = featureBits[ARM::FeatureD16];
1024 uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
1025 .getFeatureBits();
1026 bool hasD16 = featureBits & ARM::FeatureD16;
10281027
10291028 if (RegNo > 31 || (hasD16 && RegNo > 15))
10301029 return MCDisassembler::Fail;
13691368 break;
13701369 }
13711370
1372 const FeatureBitset &featureBits =
1373 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
1374 if (featureBits[ARM::HasV8Ops] && (coproc != 14))
1371 uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
1372 .getFeatureBits();
1373 if ((featureBits & ARM::HasV8Ops) && (coproc != 14))
13751374 return MCDisassembler::Fail;
13761375
13771376 Inst.addOperand(MCOperand::CreateImm(coproc));
32673266 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
32683267 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
32693268
3270 const FeatureBitset &featureBits =
3271 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3272
3273 bool hasMP = featureBits[ARM::FeatureMP];
3274 bool hasV7Ops = featureBits[ARM::HasV7Ops];
3269 uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
3270 .getFeatureBits();
3271 bool hasMP = featureBits & ARM::FeatureMP;
3272 bool hasV7Ops = featureBits & ARM::HasV7Ops;
32753273
32763274 if (Rn == 15) {
32773275 switch (Inst.getOpcode()) {
33543352 imm |= (Rn << 9);
33553353 unsigned add = fieldFromInstruction(Insn, 9, 1);
33563354
3357 const FeatureBitset &featureBits =
3358 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3359
3360 bool hasMP = featureBits[ARM::FeatureMP];
3361 bool hasV7Ops = featureBits[ARM::HasV7Ops];
3355 uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
3356 .getFeatureBits();
3357 bool hasMP = featureBits & ARM::FeatureMP;
3358 bool hasV7Ops = featureBits & ARM::HasV7Ops;
33623359
33633360 if (Rn == 15) {
33643361 switch (Inst.getOpcode()) {
34353432 unsigned imm = fieldFromInstruction(Insn, 0, 12);
34363433 imm |= (Rn << 13);
34373434
3438 const FeatureBitset &featureBits =
3439 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3440
3441 bool hasMP = featureBits[ARM::FeatureMP];
3442 bool hasV7Ops = featureBits[ARM::HasV7Ops];
3435 uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
3436 .getFeatureBits();
3437 bool hasMP = (featureBits & ARM::FeatureMP);
3438 bool hasV7Ops = (featureBits & ARM::HasV7Ops);
34433439
34443440 if (Rn == 15) {
34453441 switch (Inst.getOpcode()) {
35533549 unsigned U = fieldFromInstruction(Insn, 23, 1);
35543550 int imm = fieldFromInstruction(Insn, 0, 12);
35553551
3556 const FeatureBitset &featureBits =
3557 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3558
3559 bool hasV7Ops = featureBits[ARM::HasV7Ops];
3552 uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
3553 .getFeatureBits();
3554 bool hasV7Ops = (featureBits & ARM::HasV7Ops);
35603555
35613556 if (Rt == 15) {
35623557 switch (Inst.getOpcode()) {
38773872 if (Val == 0xA || Val == 0xB)
38783873 return MCDisassembler::Fail;
38793874
3880 const FeatureBitset &featureBits =
3881 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3882
3883 if (featureBits[ARM::HasV8Ops] && !(Val == 14 || Val == 15))
3875 uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
3876 .getFeatureBits();
3877 if ((featureBits & ARM::HasV8Ops) && !(Val == 14 || Val == 15))
38843878 return MCDisassembler::Fail;
38853879
38863880 Inst.addOperand(MCOperand::CreateImm(Val));
40304024 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val,
40314025 uint64_t Address, const void *Decoder) {
40324026 DecodeStatus S = MCDisassembler::Success;
4033 const FeatureBitset &FeatureBits =
4034 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
4035
4036 if (FeatureBits[ARM::FeatureMClass]) {
4027 uint64_t FeatureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
4028 .getFeatureBits();
4029 if (FeatureBits & ARM::FeatureMClass) {
40374030 unsigned ValLow = Val & 0xff;
40384031
40394032 // Validate the SYSm value first.
40534046 case 17: // basepri
40544047 case 18: // basepri_max
40554048 case 19: // faultmask
4056 if (!(FeatureBits[ARM::HasV7Ops]))
4049 if (!(FeatureBits & ARM::HasV7Ops))
40574050 // Values basepri, basepri_max and faultmask are only valid for v7m.
40584051 return MCDisassembler::Fail;
40594052 break;
40634056
40644057 if (Inst.getOpcode() == ARM::t2MSR_M) {
40654058 unsigned Mask = fieldFromInstruction(Val, 10, 2);
4066 if (!(FeatureBits[ARM::HasV7Ops])) {
4059 if (!(FeatureBits & ARM::HasV7Ops)) {
40674060 // The ARMv6-M MSR bits {11-10} can be only 0b10, other values are
40684061 // unpredictable.
40694062 if (Mask != 2)
40774070 // indicates the move for the GE{3:0} bits, the mask{0} bit can be set
40784071 // only if the processor includes the DSP extension.
40794072 if (Mask == 0 || (Mask != 2 && ValLow > 3) ||
4080 (!(FeatureBits[ARM::FeatureDSPThumb2]) && (Mask & 1)))
4073 (!(FeatureBits & ARM::FeatureDSPThumb2) && (Mask & 1)))
40814074 S = MCDisassembler::SoftFail;
40824075 }
40834076 }
8989 case 3: O << "\twfi"; break;
9090 case 4: O << "\tsev"; break;
9191 case 5:
92 if (getAvailableFeatures()[ARM::HasV8Ops]) {
92 if ((getAvailableFeatures() & ARM::HasV8Ops)) {
9393 O << "\tsevl";
9494 break;
9595 } // Fallthrough for non-v8
298298 if (MI->getNumOperands() == 3 &&
299299 MI->getOperand(0).isImm() &&
300300 MI->getOperand(0).getImm() == 0 &&
301 getAvailableFeatures()[ARM::FeatureVirtualization]) {
301 (getAvailableFeatures() & ARM::FeatureVirtualization)) {
302302 O << "\teret";
303303 printPredicateOperand(MI, 1, O);
304304 printAnnotation(O, Annot);
697697 void ARMInstPrinter::printMemBOption(const MCInst *MI, unsigned OpNum,
698698 raw_ostream &O) {
699699 unsigned val = MI->getOperand(OpNum).getImm();
700 O << ARM_MB::MemBOptToString(val, getAvailableFeatures()[ARM::HasV8Ops]);
700 O << ARM_MB::MemBOptToString(val, (getAvailableFeatures() & ARM::HasV8Ops));
701701 }
702702
703703 void ARMInstPrinter::printInstSyncBOption(const MCInst *MI, unsigned OpNum,
795795 const MCOperand &Op = MI->getOperand(OpNum);
796796 unsigned SpecRegRBit = Op.getImm() >> 4;
797797 unsigned Mask = Op.getImm() & 0xf;
798 const FeatureBitset &FeatureBits = getAvailableFeatures();
799
800 if (FeatureBits[ARM::FeatureMClass]) {
798 uint64_t FeatureBits = getAvailableFeatures();
799
800 if (FeatureBits & ARM::FeatureMClass) {
801801 unsigned SYSm = Op.getImm();
802802 unsigned Opcode = MI->getOpcode();
803803
804804 // For writes, handle extended mask bits if the DSP extension is present.
805 if (Opcode == ARM::t2MSR_M && FeatureBits[ARM::FeatureDSPThumb2]) {
805 if (Opcode == ARM::t2MSR_M && (FeatureBits & ARM::FeatureDSPThumb2)) {
806806 switch (SYSm) {
807807 case 0x400: O << "apsr_g"; return;
808808 case 0xc00: O << "apsr_nzcvqg"; return;
818818 // Handle the basic 8-bit mask.
819819 SYSm &= 0xff;
820820
821 if (Opcode == ARM::t2MSR_M && FeatureBits [ARM::HasV7Ops]) {
821 if (Opcode == ARM::t2MSR_M && (FeatureBits & ARM::HasV7Ops)) {
822822 // ARMv7-M deprecates using MSR APSR without a _ qualifier as an
823823 // alias for MSR APSR_nzcvq.
824824 switch (SYSm) {
3232 return ARM::NumTargetFixupKinds;
3333 }
3434
35 bool hasNOP() const { return STI->getFeatureBits()[ARM::HasV6T2Ops]; }
35 bool hasNOP() const { return (STI->getFeatureBits() & ARM::HasV6T2Ops) != 0; }
3636
3737 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override;
3838
5050 ~ARMMCCodeEmitter() {}
5151
5252 bool isThumb(const MCSubtargetInfo &STI) const {
53 return STI.getFeatureBits()[ARM::ModeThumb];
53 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
5454 }
5555 bool isThumb2(const MCSubtargetInfo &STI) const {
56 return isThumb(STI) && STI.getFeatureBits()[ARM::FeatureThumb2];
56 return isThumb(STI) && (STI.getFeatureBits() & ARM::FeatureThumb2) != 0;
5757 }
5858 bool isTargetMachO(const MCSubtargetInfo &STI) const {
5959 Triple TT(STI.getTargetTriple());
3232
3333 static bool getMCRDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI,
3434 std::string &Info) {
35 if (STI.getFeatureBits()[llvm::ARM::HasV7Ops] &&
35 if (STI.getFeatureBits() & llvm::ARM::HasV7Ops &&
3636 (MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 15) &&
3737 (MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0) &&
3838 // Checks for the deprecated CP15ISB encoding:
6464
6565 static bool getITDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI,
6666 std::string &Info) {
67 if (STI.getFeatureBits()[llvm::ARM::HasV8Ops] && MI.getOperand(1).isImm() &&
67 if (STI.getFeatureBits() & llvm::ARM::HasV8Ops && MI.getOperand(1).isImm() &&
6868 MI.getOperand(1).getImm() != 8) {
6969 Info = "applying IT instruction to more than one subsequent instruction is "
7070 "deprecated";
7676
7777 static bool getARMStoreDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI,
7878 std::string &Info) {
79 assert(!STI.getFeatureBits()[llvm::ARM::ModeThumb] &&
79 assert((~STI.getFeatureBits() & llvm::ARM::ModeThumb) &&
8080 "cannot predicate thumb instructions");
8181
8282 assert(MI.getNumOperands() >= 4 && "expected >= 4 arguments");
9393
9494 static bool getARMLoadDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI,
9595 std::string &Info) {
96 assert(!STI.getFeatureBits()[llvm::ARM::ModeThumb] &&
96 assert((~STI.getFeatureBits() & llvm::ARM::ModeThumb) &&
9797 "cannot predicate thumb instructions");
9898
9999 assert(MI.getNumOperands() >= 4 && "expected >= 4 arguments");
7070 // The full table can be found in MipsGenSubtargetInfo.inc (MipsFeatureKV[]).
7171 // The reason we need this mask is explained in the selectArch function.
7272 // FIXME: Ideally we would like TableGen to generate this information.
73 static const FeatureBitset AllArchRelatedMask;
73 static const uint64_t AllArchRelatedMask =
74 Mips::FeatureMips1 | Mips::FeatureMips2 | Mips::FeatureMips3 |
75 Mips::FeatureMips3_32 | Mips::FeatureMips3_32r2 | Mips::FeatureMips4 |
76 Mips::FeatureMips4_32 | Mips::FeatureMips4_32r2 | Mips::FeatureMips5 |
77 Mips::FeatureMips5_32r2 | Mips::FeatureMips32 | Mips::FeatureMips32r2 |
78 Mips::FeatureMips32r3 | Mips::FeatureMips32r5 | Mips::FeatureMips32r6 |
79 Mips::FeatureMips64 | Mips::FeatureMips64r2 | Mips::FeatureMips64r3 |
80 Mips::FeatureMips64r5 | Mips::FeatureMips64r6 | Mips::FeatureCnMips |
81 Mips::FeatureFP64Bit | Mips::FeatureGP64Bit | Mips::FeatureNaN2008;
7482
7583 private:
7684 unsigned ATReg;
7987 uint64_t Features;
8088 };
8189 }
82
83 const FeatureBitset MipsAssemblerOptions::AllArchRelatedMask = {
84 Mips::FeatureMips1, Mips::FeatureMips2, Mips::FeatureMips3,
85 Mips::FeatureMips3_32, Mips::FeatureMips3_32r2, Mips::FeatureMips4,
86 Mips::FeatureMips4_32, Mips::FeatureMips4_32r2, Mips::FeatureMips5,
87 Mips::FeatureMips5_32r2, Mips::FeatureMips32, Mips::FeatureMips32r2,
88 Mips::FeatureMips32r3, Mips::FeatureMips32r5, Mips::FeatureMips32r6,
89 Mips::FeatureMips64, Mips::FeatureMips64r2, Mips::FeatureMips64r3,
90 Mips::FeatureMips64r5, Mips::FeatureMips64r6, Mips::FeatureCnMips,
91 Mips::FeatureFP64Bit, Mips::FeatureGP64Bit, Mips::FeatureNaN2008
92 };
9390
9491 namespace {
9592 class MipsAsmParser : public MCTargetAsmParser {
295292 // FeatureMipsGP64 | FeatureMips1)
296293 // Clearing Mips3 is equivalent to clear (FeatureMips3 | FeatureMips4).
297294 void selectArch(StringRef ArchFeature) {
298 FeatureBitset FeatureBits = STI.getFeatureBits();
295 uint64_t FeatureBits = STI.getFeatureBits();
299296 FeatureBits &= ~MipsAssemblerOptions::AllArchRelatedMask;
300297 STI.setFeatureBits(FeatureBits);
301298 setAvailableFeatures(
304301 }
305302
306303 void setFeatureBits(uint64_t Feature, StringRef FeatureString) {
307 if (!(STI.getFeatureBits()[Feature])) {
304 if (!(STI.getFeatureBits() & Feature)) {
308305 setAvailableFeatures(
309306 ComputeAvailableFeatures(STI.ToggleFeature(FeatureString)));
310307 }
312309 }
313310
314311 void clearFeatureBits(uint64_t Feature, StringRef FeatureString) {
315 if (STI.getFeatureBits()[Feature]) {
312 if (STI.getFeatureBits() & Feature) {
316313 setAvailableFeatures(
317314 ComputeAvailableFeatures(STI.ToggleFeature(FeatureString)));
318315 }
357354 /// True if all of $fcc0 - $fcc7 exist for the current ISA.
358355 bool hasEightFccRegisters() const { return hasMips4() || hasMips32(); }
359356
360 bool isGP64bit() const { return STI.getFeatureBits()[Mips::FeatureGP64Bit]; }
361 bool isFP64bit() const { return STI.getFeatureBits()[Mips::FeatureFP64Bit]; }
357 bool isGP64bit() const { return STI.getFeatureBits() & Mips::FeatureGP64Bit; }
358 bool isFP64bit() const { return STI.getFeatureBits() & Mips::FeatureFP64Bit; }
362359 const MipsABIInfo &getABI() const { return ABI; }
363360 bool isABI_N32() const { return ABI.IsN32(); }
364361 bool isABI_N64() const { return ABI.IsN64(); }
365362 bool isABI_O32() const { return ABI.IsO32(); }
366 bool isABI_FPXX() const { return STI.getFeatureBits()[Mips::FeatureFPXX]; }
363 bool isABI_FPXX() const { return STI.getFeatureBits() & Mips::FeatureFPXX; }
367364
368365 bool useOddSPReg() const {
369 return !(STI.getFeatureBits()[Mips::FeatureNoOddSPReg]);
366 return !(STI.getFeatureBits() & Mips::FeatureNoOddSPReg);
370367 }
371368
372369 bool inMicroMipsMode() const {
373 return STI.getFeatureBits()[Mips::FeatureMicroMips];
374 }
375 bool hasMips1() const { return STI.getFeatureBits()[Mips::FeatureMips1]; }
376 bool hasMips2() const { return STI.getFeatureBits()[Mips::FeatureMips2]; }
377 bool hasMips3() const { return STI.getFeatureBits()[Mips::FeatureMips3]; }
378 bool hasMips4() const { return STI.getFeatureBits()[Mips::FeatureMips4]; }
379 bool hasMips5() const { return STI.getFeatureBits()[Mips::FeatureMips5]; }
370 return STI.getFeatureBits() & Mips::FeatureMicroMips;
371 }
372 bool hasMips1() const { return STI.getFeatureBits() & Mips::FeatureMips1; }
373 bool hasMips2() const { return STI.getFeatureBits() & Mips::FeatureMips2; }
374 bool hasMips3() const { return STI.getFeatureBits() & Mips::FeatureMips3; }
375 bool hasMips4() const { return STI.getFeatureBits() & Mips::FeatureMips4; }
376 bool hasMips5() const { return STI.getFeatureBits() & Mips::FeatureMips5; }
380377 bool hasMips32() const {
381 return STI.getFeatureBits()[Mips::FeatureMips32];
378 return (STI.getFeatureBits() & Mips::FeatureMips32);
382379 }
383380 bool hasMips64() const {
384 return STI.getFeatureBits()[Mips::FeatureMips64];
381 return (STI.getFeatureBits() & Mips::FeatureMips64);
385382 }
386383 bool hasMips32r2() const {
387 return STI.getFeatureBits()[Mips::FeatureMips32r2];
384 return (STI.getFeatureBits() & Mips::FeatureMips32r2);
388385 }
389386 bool hasMips64r2() const {
390 return STI.getFeatureBits()[Mips::FeatureMips64r2];
387 return (STI.getFeatureBits() & Mips::FeatureMips64r2);
391388 }
392389 bool hasMips32r3() const {
393 return (STI.getFeatureBits()[Mips::FeatureMips32r3]);
390 return (STI.getFeatureBits() & Mips::FeatureMips32r3);
394391 }
395392 bool hasMips64r3() const {
396 return (STI.getFeatureBits()[Mips::FeatureMips64r3]);
393 return (STI.getFeatureBits() & Mips::FeatureMips64r3);
397394 }
398395 bool hasMips32r5() const {
399 return (STI.getFeatureBits()[Mips::FeatureMips32r5]);
396 return (STI.getFeatureBits() & Mips::FeatureMips32r5);
400397 }
401398 bool hasMips64r5() const {
402 return (STI.getFeatureBits()[Mips::FeatureMips64r5]);
399 return (STI.getFeatureBits() & Mips::FeatureMips64r5);
403400 }
404401 bool hasMips32r6() const {
405 return STI.getFeatureBits()[Mips::FeatureMips32r6];
402 return (STI.getFeatureBits() & Mips::FeatureMips32r6);
406403 }
407404 bool hasMips64r6() const {
408 return STI.getFeatureBits()[Mips::FeatureMips64r6];
409 }
410
411 bool hasDSP() const { return STI.getFeatureBits()[Mips::FeatureDSP]; }
412 bool hasDSPR2() const { return STI.getFeatureBits()[Mips::FeatureDSPR2]; }
413 bool hasMSA() const { return STI.getFeatureBits()[Mips::FeatureMSA]; }
405 return (STI.getFeatureBits() & Mips::FeatureMips64r6);
406 }
414407 bool hasCnMips() const {
415 return (STI.getFeatureBits()[Mips::FeatureCnMips]);
416 }
408 return (STI.getFeatureBits() & Mips::FeatureCnMips);
409 }
410 bool hasDSP() const { return (STI.getFeatureBits() & Mips::FeatureDSP); }
411 bool hasDSPR2() const { return (STI.getFeatureBits() & Mips::FeatureDSPR2); }
412 bool hasMSA() const { return (STI.getFeatureBits() & Mips::FeatureMSA); }
417413
418414 bool inMips16Mode() const {
419 return STI.getFeatureBits()[Mips::FeatureMips16];
415 return STI.getFeatureBits() & Mips::FeatureMips16;
420416 }
421417 // TODO: see how can we get this info.
422418 bool abiUsesSoftFloat() const { return false; }
3535 public:
3636 MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool IsBigEndian)
3737 : MCDisassembler(STI, Ctx),
38 IsMicroMips(STI.getFeatureBits()[Mips::FeatureMicroMips]),
38 IsMicroMips(STI.getFeatureBits() & Mips::FeatureMicroMips),
3939 IsBigEndian(IsBigEndian) {}
4040
41 bool hasMips3() const { return STI.getFeatureBits()[Mips::FeatureMips3]; }
42 bool hasMips32() const { return STI.getFeatureBits()[Mips::FeatureMips32]; }
41 bool hasMips3() const { return STI.getFeatureBits() & Mips::FeatureMips3; }
42 bool hasMips32() const { return STI.getFeatureBits() & Mips::FeatureMips32; }
4343 bool hasMips32r6() const {
44 return STI.getFeatureBits()[Mips::FeatureMips32r6];
45 }
46
47 bool isGP64() const { return STI.getFeatureBits()[Mips::FeatureGP64Bit]; }
44 return STI.getFeatureBits() & Mips::FeatureMips32r6;
45 }
46
47 bool isGP64() const { return STI.getFeatureBits() & Mips::FeatureGP64Bit; }
4848
4949 bool hasCOP3() const {
5050 // Only present in MIPS-I and MIPS-II
113113 }
114114
115115 bool MipsMCCodeEmitter::isMicroMips(const MCSubtargetInfo &STI) const {
116 return STI.getFeatureBits()[Mips::FeatureMicroMips];
116 return STI.getFeatureBits() & Mips::FeatureMicroMips;
117117 }
118118
119119 void MipsMCCodeEmitter::EmitByte(unsigned char C, raw_ostream &OS) const {
176176 (Opcode != Mips::SLL_MM) && !Binary)
177177 llvm_unreachable("unimplemented opcode in EncodeInstruction()");
178178
179 if (STI.getFeatureBits()[Mips::FeatureMicroMips]) {
179 if (STI.getFeatureBits() & Mips::FeatureMicroMips) {
180180 int NewOpcode = Mips::Std2MicroMips (Opcode, Mips::Arch_micromips);
181181 if (NewOpcode != -1) {
182182 if (Fixups.size() > N)
366366 const MCSubtargetInfo &STI)
367367 : MipsTargetStreamer(S), MicroMipsEnabled(false), STI(STI) {
368368 MCAssembler &MCA = getStreamer().getAssembler();
369
370369 Triple T(STI.getTargetTriple());
371370 Pic = (MCA.getContext().getObjectFileInfo()->getRelocM() == Reloc::PIC_)
372371 ? true
373372 : false;
374373
375 const FeatureBitset &Features = STI.getFeatureBits();
374 uint64_t Features = STI.getFeatureBits();
376375
377376 // Set the header flags that we can in the constructor.
378377 // FIXME: This is a fairly terrible hack. We set the rest
388387 unsigned EFlags = MCA.getELFHeaderEFlags();
389388
390389 // Architecture
391 if (Features[Mips::FeatureMips64r6])
390 if (Features & Mips::FeatureMips64r6)
392391 EFlags |= ELF::EF_MIPS_ARCH_64R6;
393 else if (Features[Mips::FeatureMips64r2] ||
394 Features[Mips::FeatureMips64r3] ||
395 Features[Mips::FeatureMips64r5])
392 else if (Features & Mips::FeatureMips64r2 ||
393 Features & Mips::FeatureMips64r3 ||
394 Features & Mips::FeatureMips64r5)
396395 EFlags |= ELF::EF_MIPS_ARCH_64R2;
397 else if (Features[Mips::FeatureMips64])
396 else if (Features & Mips::FeatureMips64)
398397 EFlags |= ELF::EF_MIPS_ARCH_64;
399 else if (Features[Mips::FeatureMips5])
398 else if (Features & Mips::FeatureMips5)
400399 EFlags |= ELF::EF_MIPS_ARCH_5;
401 else if (Features[Mips::FeatureMips4])
400 else if (Features & Mips::FeatureMips4)
402401 EFlags |= ELF::EF_MIPS_ARCH_4;
403 else if (Features[Mips::FeatureMips3])
402 else if (Features & Mips::FeatureMips3)
404403 EFlags |= ELF::EF_MIPS_ARCH_3;
405 else if (Features[Mips::FeatureMips32r6])
404 else if (Features & Mips::FeatureMips32r6)
406405 EFlags |= ELF::EF_MIPS_ARCH_32R6;
407 else if (Features[Mips::FeatureMips32r2] ||
408 Features[Mips::FeatureMips32r3] ||
409 Features[Mips::FeatureMips32r5])
406 else if (Features & Mips::FeatureMips32r2 ||
407 Features & Mips::FeatureMips32r3 ||
408 Features & Mips::FeatureMips32r5)
410409 EFlags |= ELF::EF_MIPS_ARCH_32R2;
411 else if (Features[Mips::FeatureMips32])
410 else if (Features & Mips::FeatureMips32)
412411 EFlags |= ELF::EF_MIPS_ARCH_32;
413 else if (Features[Mips::FeatureMips2])
412 else if (Features & Mips::FeatureMips2)
414413 EFlags |= ELF::EF_MIPS_ARCH_2;
415414 else
416415 EFlags |= ELF::EF_MIPS_ARCH_1;
417416
418417 // Other options.
419 if (Features[Mips::FeatureNaN2008])
418 if (Features & Mips::FeatureNaN2008)
420419 EFlags |= ELF::EF_MIPS_NAN2008;
421420
422421 // -mabicalls and -mplt are not implemented but we should act as if they were
456455 DataSectionData.setAlignment(std::max(16u, DataSectionData.getAlignment()));
457456 BSSSectionData.setAlignment(std::max(16u, BSSSectionData.getAlignment()));
458457
459 const FeatureBitset &Features = STI.getFeatureBits();
458 uint64_t Features = STI.getFeatureBits();
460459
461460 // Update e_header flags. See the FIXME and comment above in
462461 // the constructor for a full rundown on this.
469468 else if (getABI().IsN32())
470469 EFlags |= ELF::EF_MIPS_ABI2;
471470
472 if (Features[Mips::FeatureGP64Bit]) {
471 if (Features & Mips::FeatureGP64Bit) {
473472 if (getABI().IsO32())
474473 EFlags |= ELF::EF_MIPS_32BITMODE; /* Compatibility Mode */
475 } else if (Features[Mips::FeatureMips64r2] || Features[Mips::FeatureMips64])
474 } else if (Features & Mips::FeatureMips64r2 || Features & Mips::FeatureMips64)
476475 EFlags |= ELF::EF_MIPS_32BITMODE;
477476
478477 // If we've set the cpic eflag and we're n64, go ahead and set the pic
7575 const MCRegisterInfo &MRI,
7676 const MCSubtargetInfo &STI,
7777 MCContext &Ctx) {
78 if (STI.getFeatureBits()[AMDGPU::Feature64BitPtr]) {
78 if (STI.getFeatureBits() & AMDGPU::Feature64BitPtr) {
7979 return createSIMCCodeEmitter(MCII, MRI, STI, Ctx);
8080 } else {
8181 return createR600MCCodeEmitter(MCII, MRI, STI);
9898 } else if (IS_VTX(Desc)) {
9999 uint64_t InstWord01 = getBinaryCodeForInstr(MI, Fixups, STI);
100100 uint32_t InstWord2 = MI.getOperand(2).getImm(); // Offset
101 if (!(STI.getFeatureBits()[AMDGPU::FeatureCaymanISA])) {
101 if (!(STI.getFeatureBits() & AMDGPU::FeatureCaymanISA)) {
102102 InstWord2 |= 1 << 19; // Mega-Fetch bit
103103 }
104104
131131 Emit((uint32_t) 0, OS);
132132 } else {
133133 uint64_t Inst = getBinaryCodeForInstr(MI, Fixups, STI);
134 if ((STI.getFeatureBits()[AMDGPU::FeatureR600ALUInst]) &&
134 if ((STI.getFeatureBits() & AMDGPU::FeatureR600ALUInst) &&
135135 ((Desc.TSFlags & R600_InstFlag::OP1) ||
136136 Desc.TSFlags & R600_InstFlag::OP2)) {
137137 uint64_t ISAOpCode = Inst & (0x3FFULL << 39);
3434 #include "SparcGenAsmWriter.inc"
3535
3636 bool SparcInstPrinter::isV9() const {
37 return (STI.getFeatureBits()[Sparc::FeatureV9]) != 0;
37 return (STI.getFeatureBits() & Sparc::FeatureV9) != 0;
3838 }
3939
4040 void SparcInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const
261261 MCContext &Ctx, int64_t *Residue);
262262
263263 bool is64BitMode() const {
264 return STI.getFeatureBits()[X86::Mode64Bit];
264 return (STI.getFeatureBits() & X86::Mode64Bit) != 0;
265265 }
266266 bool is32BitMode() const {
267 return STI.getFeatureBits()[X86::Mode32Bit];
267 return (STI.getFeatureBits() & X86::Mode32Bit) != 0;
268268 }
269269 bool is16BitMode() const {
270 return STI.getFeatureBits()[X86::Mode16Bit];
270 return (STI.getFeatureBits() & X86::Mode16Bit) != 0;
271271 }
272272
273273 unsigned getPointerWidth() {
10721072 const bool hasCompilerRTSupport = T.isOSLinux();
10731073 if (ClAsanInstrumentAssembly && hasCompilerRTSupport &&
10741074 MCOptions.SanitizeAddress) {
1075 if (STI.getFeatureBits()[X86::Mode32Bit] != 0)
1075 if ((STI.getFeatureBits() & X86::Mode32Bit) != 0)
10761076 return new X86AddressSanitizer32(STI);
1077 if (STI.getFeatureBits()[X86::Mode64Bit] != 0)
1077 if ((STI.getFeatureBits() & X86::Mode64Bit) != 0)
10781078 return new X86AddressSanitizer64(STI);
10791079 }
10801080 return new X86AsmInstrumentation(STI);
726726
727727 bool is64BitMode() const {
728728 // FIXME: Can tablegen auto-generate this?
729 return STI.getFeatureBits()[X86::Mode64Bit];
729 return (STI.getFeatureBits() & X86::Mode64Bit) != 0;
730730 }
731731 bool is32BitMode() const {
732732 // FIXME: Can tablegen auto-generate this?
733 return STI.getFeatureBits()[X86::Mode32Bit];
733 return (STI.getFeatureBits() & X86::Mode32Bit) != 0;
734734 }
735735 bool is16BitMode() const {
736736 // FIXME: Can tablegen auto-generate this?
737 return STI.getFeatureBits()[X86::Mode16Bit];
738 }
739 void SwitchMode(unsigned mode) {
740 FeatureBitset AllModes({X86::Mode64Bit, X86::Mode32Bit, X86::Mode16Bit});
741 FeatureBitset OldMode = STI.getFeatureBits() & AllModes;
742 unsigned FB = ComputeAvailableFeatures(
743 STI.ToggleFeature(OldMode.flip(mode)));
737 return (STI.getFeatureBits() & X86::Mode16Bit) != 0;
738 }
739 void SwitchMode(uint64_t mode) {
740 uint64_t oldMode = STI.getFeatureBits() &
741 (X86::Mode64Bit | X86::Mode32Bit | X86::Mode16Bit);
742 unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(oldMode | mode));
744743 setAvailableFeatures(FB);
745
746 assert(FeatureBitset({mode}) == (STI.getFeatureBits() & AllModes));
744 assert(mode == (STI.getFeatureBits() &
745 (X86::Mode64Bit | X86::Mode32Bit | X86::Mode16Bit)));
747746 }
748747
749748 unsigned getPointerWidth() {
17141713 bool X86AsmParser::HandleAVX512Operand(OperandVector &Operands,
17151714 const MCParsedAsmOperand &Op) {
17161715 MCAsmParser &Parser = getParser();
1717 if(STI.getFeatureBits()[X86::FeatureAVX512]) {
1716 if(STI.getFeatureBits() & X86::FeatureAVX512) {
17181717 if (getLexer().is(AsmToken::LCurly)) {
17191718 // Eat "{" and mark the current place.
17201719 const SMLoc consumedToken = consumeToken();
7979 MCContext &Ctx,
8080 std::unique_ptr MII)
8181 : MCDisassembler(STI, Ctx), MII(std::move(MII)) {
82 const FeatureBitset &FB = STI.getFeatureBits();
83 if (FB[X86::Mode16Bit]) {
82 switch (STI.getFeatureBits() &
83 (X86::Mode16Bit | X86::Mode32Bit | X86::Mode64Bit)) {
84 case X86::Mode16Bit:
8485 fMode = MODE_16BIT;
85 return;
86 } else if (FB[X86::Mode32Bit]) {
86 break;
87 case X86::Mode32Bit:
8788 fMode = MODE_32BIT;
88 return;
89 } else if (FB[X86::Mode64Bit]) {
89 break;
90 case X86::Mode64Bit:
9091 fMode = MODE_64BIT;
91 return;
92 }
93
94 llvm_unreachable("Invalid CPU mode");
92 break;
93 default:
94 llvm_unreachable("Invalid CPU mode");
95 }
9596 }
9697
9798 struct Region {
5959 // InstrInfo.td as soon as Requires clause is supported properly
6060 // for InstAlias.
6161 if (MI->getOpcode() == X86::CALLpcrel32 &&
62 getAvailableFeatures()[X86::Mode64Bit]) {
62 (getAvailableFeatures() & X86::Mode64Bit) != 0) {
6363 OS << "\tcallq\t";
6464 printPCRelImm(MI, 0, OS);
6565 }
4141 ~X86MCCodeEmitter() {}
4242
4343 bool is64BitMode(const MCSubtargetInfo &STI) const {
44 return STI.getFeatureBits()[X86::Mode64Bit];
44 return (STI.getFeatureBits() & X86::Mode64Bit) != 0;
4545 }
4646
4747 bool is32BitMode(const MCSubtargetInfo &STI) const {
48 return STI.getFeatureBits()[X86::Mode32Bit];
48 return (STI.getFeatureBits() & X86::Mode32Bit) != 0;
4949 }
5050
5151 bool is16BitMode(const MCSubtargetInfo &STI) const {
52 return STI.getFeatureBits()[X86::Mode16Bit];
52 return (STI.getFeatureBits() & X86::Mode16Bit) != 0;
5353 }
5454
5555 /// Is16BitMemOperand - Return true if the specified instruction has
22412241 Info.AsmParser->getValueAsString("AsmParserClassName");
22422242
22432243 OS << "uint64_t " << Info.Target.getName() << ClassName << "::\n"
2244 << "ComputeAvailableFeatures(const FeatureBitset& FB) const {\n";
2244 << "ComputeAvailableFeatures(uint64_t FB) const {\n";
22452245 OS << " uint64_t Features = 0;\n";
22462246 for (const auto &SF : Info.SubtargetFeatures) {
22472247 const SubtargetFeatureInfo &SFI = SF.second;
22632263 Cond = Cond.substr(1);
22642264 }
22652265
2266 OS << "(";
2266 OS << "((FB & " << Info.Target.getName() << "::" << Cond << ")";
22672267 if (Neg)
2268 OS << "!";
2269 OS << "FB[" << Info.Target.getName() << "::" << Cond << "])";
2268 OS << " == 0";
2269 else
2270 OS << " != 0";
2271 OS << ")";
22702272
22712273 if (Comma.second.empty())
22722274 break;
26362638 OS << "#undef GET_ASSEMBLER_HEADER\n";
26372639 OS << " // This should be included into the middle of the declaration of\n";
26382640 OS << " // your subclasses implementation of MCTargetAsmParser.\n";
2639 OS << " uint64_t ComputeAvailableFeatures(const FeatureBitset& FB) const;\n";
2641 OS << " uint64_t ComputeAvailableFeatures(uint64_t FeatureBits) const;\n";
26402642 OS << " void convertToMCInst(unsigned Kind, MCInst &Inst, "
26412643 << "unsigned Opcode,\n"
26422644 << " const OperandVector "
847847 // The predicate function is just a big switch statement based on the
848848 // input predicate index.
849849 OS.indent(Indentation) << "static bool checkDecoderPredicate(unsigned Idx, "
850 << "const FeatureBitset& Bits) {\n";
850 << "uint64_t Bits) {\n";
851851 Indentation += 2;
852852 if (!Predicates.empty()) {
853853 OS.indent(Indentation) << "switch (Idx) {\n";
11011101 static void emitSinglePredicateMatch(raw_ostream &o, StringRef str,
11021102 const std::string &PredicateNamespace) {
11031103 if (str[0] == '!')
1104 o << "!Bits[" << PredicateNamespace << "::"
1105 << str.slice(1,str.size()) << "]";
1104 o << "!(Bits & " << PredicateNamespace << "::"
1105 << str.slice(1,str.size()) << ")";
11061106 else
1107 o << "Bits[" << PredicateNamespace << "::" << str << "]";
1107 o << "(Bits & " << PredicateNamespace << "::" << str << ")";
11081108 }
11091109
11101110 bool FilterChooser::emitPredicateMatch(raw_ostream &o, unsigned &Indentation,
20092009 << " InsnType insn, uint64_t Address,\n"
20102010 << " const void *DisAsm,\n"
20112011 << " const MCSubtargetInfo &STI) {\n"
2012 << " const FeatureBitset& Bits = STI.getFeatureBits();\n"
2012 << " uint64_t Bits = STI.getFeatureBits();\n"
20132013 << "\n"
20142014 << " const uint8_t *Ptr = DecodeTable;\n"
20152015 << " uint32_t CurFieldValue = 0;\n"
546546 CodeGenTarget &Target = CDP.getTargetInfo();
547547 if (Inst.HasComplexDeprecationPredicate)
548548 // Emit a function pointer to the complex predicate method.
549 OS << ", { } "
549 OS << ",0"
550550 << ",&get" << Inst.DeprecatedReason << "DeprecationInfo";
551551 else if (!Inst.DeprecatedReason.empty())
552552 // Emit the Subtarget feature.
553 OS << ", { " << Target.getInstNamespace() << "::" << Inst.DeprecatedReason
554 << "} ,nullptr";
553 OS << "," << Target.getInstNamespace() << "::" << Inst.DeprecatedReason
554 << ",nullptr";
555555 else
556556 // Instruction isn't deprecated.
557 OS << ", { } ,nullptr";
557 OS << ",0,nullptr";
558558
559559 OS << " }, // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n";
560560 }
1515 #include "llvm/ADT/STLExtras.h"
1616 #include "llvm/ADT/StringExtras.h"
1717 #include "llvm/MC/MCInstrItineraries.h"
18 #include "llvm/MC/SubtargetFeature.h"
1918 #include "llvm/Support/Debug.h"
2019 #include "llvm/Support/Format.h"
2120 #include "llvm/TableGen/Error.h"
6261 CodeGenSchedModels &SchedModels;
6362 std::string Target;
6463
65 void Enumeration(raw_ostream &OS, const char *ClassName);
64 void Enumeration(raw_ostream &OS, const char *ClassName, bool isBits);
6665 unsigned FeatureKeyValues(raw_ostream &OS);
6766 unsigned CPUKeyValues(raw_ostream &OS);
6867 void FormItineraryStageString(const std::string &Names,
112111 // Enumeration - Emit the specified class as an enumeration.
113112 //
114113 void SubtargetEmitter::Enumeration(raw_ostream &OS,
115 const char *ClassName) {
114 const char *ClassName,
115 bool isBits) {
116116 // Get all records of class and sort
117117 std::vector DefList = Records.getAllDerivedDefinitions(ClassName);
118118 std::sort(DefList.begin(), DefList.end(), LessRecord());
120120 unsigned N = DefList.size();
121121 if (N == 0)
122122 return;
123 if (N > MAX_SUBTARGET_FEATURES) {
124 errs() << "Too many subtarget features! Bump MAX_SUBTARGET_FEATURES.";
123 if (N > 64) {
124 errs() << "Too many (> 64) subtarget features!\n";
125125 exit(1);
126126 }
127127
128128 OS << "namespace " << Target << " {\n";
129129
130 // Open enumeration
131 OS << "enum {\n";
132
133 // For each record
134 for (unsigned i = 0; i < N;) {
135 // Next record
136 Record *Def = DefList[i];
137
138 // Get and emit name
139 OS << " " << Def->getName() << " = " << i;
140 if (++i < N) OS << ",";
141
142 OS << "\n";
143 }
144
145 // Close enumeration and namespace
146 OS << "};\n}\n";
130 // For bit flag enumerations with more than 32 items, emit constants.
131 // Emit an enum for everything else.
132 if (isBits && N > 32) {
133 // For each record
134 for (unsigned i = 0; i < N; i++) {
135 // Next record
136 Record *Def = DefList[i];
137
138 // Get and emit name and expression (1 << i)
139 OS << " const uint64_t " << Def->getName() << " = 1ULL << " << i << ";\n";
140 }
141 } else {
142 // Open enumeration
143 OS << "enum {\n";
144
145 // For each record
146 for (unsigned i = 0; i < N;) {
147 // Next record
148 Record *Def = DefList[i];
149
150 // Get and emit name
151 OS << " " << Def->getName();
152
153 // If bit flags then emit expression (1 << i)
154 if (isBits) OS << " = " << " 1ULL << " << i;
155
156 // Depending on 'if more in the list' emit comma
157 if (++i < N) OS << ",";
158
159 OS << "\n";
160 }
161
162 // Close enumeration
163 OS << "};\n";
164 }
165
166 OS << "}\n";
147167 }
148168
149169 //
177197
178198 if (CommandLineName.empty()) continue;
179199
180 // Emit as { "feature", "description", { featureEnum }, { i1 , i2 , ... , in } }
200 // Emit as { "feature", "description", featureEnum, i1 | i2 | ... | in }
181201 OS << " { "
182202 << "\"" << CommandLineName << "\", "
183203 << "\"" << Desc << "\", "
184 << "{ " << Target << "::" << Name << " }, ";
204 << Target << "::" << Name << ", ";
185205
186206 const std::vector &ImpliesList =
187207 Feature->getValueAsListOfDefs("Implies");
188208
189209 if (ImpliesList.empty()) {
190 OS << "{ }";
210 OS << "0ULL";
191211 } else {
192 OS << "{ ";
193212 for (unsigned j = 0, M = ImpliesList.size(); j < M;) {
194213 OS << Target << "::" << ImpliesList[j]->getName();
195 if (++j < M) OS << ", ";
196 }
197 OS << " }";
214 if (++j < M) OS << " | ";
215 }
198216 }
199217
200218 OS << " }";
236254 const std::vector &FeatureList =
237255 Processor->getValueAsListOfDefs("Features");
238256
239 // Emit as { "cpu", "description", { f1 , f2 , ... fn } },
257 // Emit as { "cpu", "description", f1 | f2 | ... fn },
240258 OS << " { "
241259 << "\"" << Name << "\", "
242260 << "\"Select the " << Name << " processor\", ";
243261
244262 if (FeatureList.empty()) {
245 OS << "{ }";
263 OS << "0ULL";
246264 } else {
247 OS << "{ ";
248265 for (unsigned j = 0, M = FeatureList.size(); j < M;) {
249266 OS << Target << "::" << FeatureList[j]->getName();
250 if (++j < M) OS << ", ";
251 }
252 OS << " }";
253 }
254
255 // The { } is for the "implies" section of this data structure.
256 OS << ", { } }";
267 if (++j < M) OS << " | ";
268 }
269 }
270
271 // The "0" is for the "implies" section of this data structure.
272 OS << ", 0ULL }";
257273
258274 // Depending on 'if more in the list' emit comma
259275 if (++i < N) OS << ",";
13811397 }
13821398
13831399 OS << " InitMCProcessorInfo(CPU, FS);\n"
1384 << " const FeatureBitset& Bits = getFeatureBits();\n";
1400 << " uint64_t Bits = getFeatureBits();\n";
13851401
13861402 for (unsigned i = 0; i < Features.size(); i++) {
13871403 // Next record
13911407 const std::string &Attribute = R->getValueAsString("Attribute");
13921408
13931409 if (Value=="true" || Value=="false")
1394 OS << " if (Bits[" << Target << "::"
1395 << Instance << "]) "
1410 OS << " if ((Bits & " << Target << "::"
1411 << Instance << ") != 0) "
13961412 << Attribute << " = " << Value << ";\n";
13971413 else
1398 OS << " if (Bits[" << Target << "::"
1399 << Instance << "] && "
1414 OS << " if ((Bits & " << Target << "::"
1415 << Instance << ") != 0 && "
14001416 << Attribute << " < " << Value << ") "
14011417 << Attribute << " = " << Value << ";\n";
14021418 }
14141430 OS << "#undef GET_SUBTARGETINFO_ENUM\n";
14151431
14161432 OS << "namespace llvm {\n";
1417 Enumeration(OS, "SubtargetFeature");
1433 Enumeration(OS, "SubtargetFeature", true);
14181434 OS << "} // End llvm namespace \n";
14191435 OS << "#endif // GET_SUBTARGETINFO_ENUM\n\n";
14201436