llvm.org GIT mirror llvm / 2b2fb7f
Scheduler / Regalloc: use unique_ptr[] instead of std::vector vector.resize() is significantly slower than memset in many STLs and the cost of initializing these vectors is significant on targets with many registers. Since we don't need the overhead of a vector, use a simple unique_ptr instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254526 91177308-0d34-0410-b5e6-96231b3b80d8 Fiona Glaser 4 years ago
3 changed file(s) with 17 addition(s) and 16 deletion(s). Raw diff Collapse all Expand all
7272
7373 /// PhysRegUseDefLists - This is an array of the head of the use/def list for
7474 /// physical registers.
75 std::vector> PhysRegUseDefLists;
75 std::unique_ptr> PhysRegUseDefLists;
7676
7777 /// getRegUseDefListHead - Return the head pointer for the register use/def
7878 /// list for the specified virtual or physical register.
2626 MachineRegisterInfo::MachineRegisterInfo(const MachineFunction *MF)
2727 : MF(MF), TheDelegate(nullptr), IsSSA(true), TracksLiveness(true),
2828 TracksSubRegLiveness(false) {
29 unsigned NumRegs = getTargetRegisterInfo()->getNumRegs();
2930 VRegInfo.reserve(256);
3031 RegAllocHints.reserve(256);
31 UsedPhysRegMask.resize(getTargetRegisterInfo()->getNumRegs());
32
33 // Create the physreg use/def lists.
34 PhysRegUseDefLists.resize(getTargetRegisterInfo()->getNumRegs(), nullptr);
32 UsedPhysRegMask.resize(NumRegs);
33 PhysRegUseDefLists.reset(new MachineOperand*[NumRegs]());
3534 }
3635
3736 /// setRegClass - Set the register class of the specified virtual register.
140140 /// that are "live". These nodes must be scheduled before any other nodes that
141141 /// modifies the registers can be scheduled.
142142 unsigned NumLiveRegs;
143 std::vector LiveRegDefs;
144 std::vector LiveRegGens;
143 std::unique_ptr LiveRegDefs;
144 std::unique_ptr LiveRegGens;
145145
146146 // Collect interferences between physical register use/defs.
147147 // Each interference is an SUnit and set of physical registers.
327327 NumLiveRegs = 0;
328328 // Allocate slots for each physical register, plus one for a special register
329329 // to track the virtual resource of a calling sequence.
330 LiveRegDefs.resize(TRI->getNumRegs() + 1, nullptr);
331 LiveRegGens.resize(TRI->getNumRegs() + 1, nullptr);
330 LiveRegDefs.reset(new SUnit*[TRI->getNumRegs() + 1]());
331 LiveRegGens.reset(new SUnit*[TRI->getNumRegs() + 1]());
332332 CallSeqEndForStart.clear();
333333 assert(Interferences.empty() && LRegsMap.empty() && "stale Interferences");
334334
12171217 /// CheckForLiveRegDef - Return true and update live register vector if the
12181218 /// specified register def of the specified SUnit clobbers any "live" registers.
12191219 static void CheckForLiveRegDef(SUnit *SU, unsigned Reg,
1220 std::vector &LiveRegDefs,
1220 SUnit **LiveRegDefs,
12211221 SmallSet &RegAdded,
12221222 SmallVectorImpl &LRegs,
12231223 const TargetRegisterInfo *TRI) {
12391239 /// CheckForLiveRegDefMasked - Check for any live physregs that are clobbered
12401240 /// by RegMask, and add them to LRegs.
12411241 static void CheckForLiveRegDefMasked(SUnit *SU, const uint32_t *RegMask,
1242 std::vector &LiveRegDefs,
1242 ArrayRef LiveRegDefs,
12431243 SmallSet &RegAdded,
12441244 SmallVectorImpl &LRegs) {
12451245 // Look at all live registers. Skip Reg0 and the special CallResource.
1246 for (unsigned i = 1, e = LiveRegDefs.size()-1; i != e; ++i) {
1246 for (unsigned i = 1, e = LiveRegDefs.size(); i != e; ++i) {
12471247 if (!LiveRegDefs[i]) continue;
12481248 if (LiveRegDefs[i] == SU) continue;
12491249 if (!MachineOperand::clobbersPhysReg(RegMask, i)) continue;
12771277 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
12781278 I != E; ++I) {
12791279 if (I->isAssignedRegDep() && LiveRegDefs[I->getReg()] != SU)
1280 CheckForLiveRegDef(I->getSUnit(), I->getReg(), LiveRegDefs,
1280 CheckForLiveRegDef(I->getSUnit(), I->getReg(), LiveRegDefs.get(),
12811281 RegAdded, LRegs, TRI);
12821282 }
12831283
13011301 for (; NumVals; --NumVals, ++i) {
13021302 unsigned Reg = cast(Node->getOperand(i))->getReg();
13031303 if (TargetRegisterInfo::isPhysicalRegister(Reg))
1304 CheckForLiveRegDef(SU, Reg, LiveRegDefs, RegAdded, LRegs, TRI);
1304 CheckForLiveRegDef(SU, Reg, LiveRegDefs.get(), RegAdded, LRegs, TRI);
13051305 }
13061306 } else
13071307 i += NumVals;
13271327 }
13281328 }
13291329 if (const uint32_t *RegMask = getNodeRegMask(Node))
1330 CheckForLiveRegDefMasked(SU, RegMask, LiveRegDefs, RegAdded, LRegs);
1330 CheckForLiveRegDefMasked(SU, RegMask,
1331 makeArrayRef(LiveRegDefs.get(), TRI->getNumRegs()),
1332 RegAdded, LRegs);
13311333
13321334 const MCInstrDesc &MCID = TII->get(Node->getMachineOpcode());
13331335 if (!MCID.ImplicitDefs)
13341336 continue;
13351337 for (const uint16_t *Reg = MCID.getImplicitDefs(); *Reg; ++Reg)
1336 CheckForLiveRegDef(SU, *Reg, LiveRegDefs, RegAdded, LRegs, TRI);
1338 CheckForLiveRegDef(SU, *Reg, LiveRegDefs.get(), RegAdded, LRegs, TRI);
13371339 }
13381340
13391341 return !LRegs.empty();