llvm.org GIT mirror llvm / 2addf06
MachineRegisterInfo: Remove UsedPhysReg infrastructure We have a detailed def/use lists for every physical register in MachineRegisterInfo anyway, so there is little use in maintaining an additional bitset of which ones are used. Removing it frees us from extra book keeping. This simplifies VirtRegMap. Differential Revision: http://reviews.llvm.org/D10911 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242173 91177308-0d34-0410-b5e6-96231b3b80d8 Matthias Braun 5 years ago
18 changed file(s) with 25 addition(s) and 181 deletion(s). Raw diff Collapse all Expand all
3131
3232 class LiveInterval;
3333 class LiveIntervalAnalysis;
34 class MachineRegisterInfo;
3534 class TargetRegisterInfo;
3635 class VirtRegMap;
3736
3837 class LiveRegMatrix : public MachineFunctionPass {
3938 const TargetRegisterInfo *TRI;
40 MachineRegisterInfo *MRI;
4139 LiveIntervals *LIS;
4240 VirtRegMap *VRM;
4341
9494 return MO->Contents.Reg.Next;
9595 }
9696
97 /// UsedRegUnits - This is a bit vector that is computed and set by the
98 /// register allocator, and must be kept up to date by passes that run after
99 /// register allocation (though most don't modify this). This is used
100 /// so that the code generator knows which callee save registers to save and
101 /// for other target specific uses.
102 /// This vector has bits set for register units that are modified in the
103 /// current function. It doesn't include registers clobbered by function
104 /// calls with register mask operands.
105 BitVector UsedRegUnits;
106
10797 /// UsedPhysRegMask - Additional used physregs including aliases.
10898 /// This bit vector represents all the registers clobbered by function calls.
109 /// It can model things that UsedRegUnits can't, such as function calls that
110 /// clobber ymm7 but preserve the low half in xmm7.
11199 BitVector UsedPhysRegMask;
112100
113101 /// ReservedRegs - This is a bit vector of reserved registers. The target
652640 /// ignored.
653641 bool isPhysRegModified(unsigned PhysReg) const;
654642
655 //===--------------------------------------------------------------------===//
656 // Physical Register Use Info
657 //===--------------------------------------------------------------------===//
658
659 /// isPhysRegUsed - Return true if the specified register is used in this
660 /// function. Also check for clobbered aliases and registers clobbered by
661 /// function calls with register mask operands.
662 ///
663 /// This only works after register allocation.
664 bool isPhysRegUsed(unsigned Reg) const {
665 if (UsedPhysRegMask.test(Reg))
666 return true;
667 for (MCRegUnitIterator Units(Reg, getTargetRegisterInfo());
668 Units.isValid(); ++Units)
669 if (UsedRegUnits.test(*Units))
670 return true;
671 return false;
672 }
673
674 /// Mark the specified register unit as used in this function.
675 /// This should only be called during and after register allocation.
676 void setRegUnitUsed(unsigned RegUnit) {
677 UsedRegUnits.set(RegUnit);
678 }
679
680 /// setPhysRegUsed - Mark the specified register used in this function.
681 /// This should only be called during and after register allocation.
682 void setPhysRegUsed(unsigned Reg) {
683 for (MCRegUnitIterator Units(Reg, getTargetRegisterInfo());
684 Units.isValid(); ++Units)
685 UsedRegUnits.set(*Units);
686 }
687
688643 /// addPhysRegsUsedFromRegMask - Mark any registers not in RegMask as used.
689644 /// This corresponds to the bit mask attached to register mask operands.
690645 void addPhysRegsUsedFromRegMask(const uint32_t *RegMask) {
691646 UsedPhysRegMask.setBitsNotInMask(RegMask);
692647 }
693
694 /// setPhysRegUnused - Mark the specified register unused in this function.
695 /// This should only be called during and after register allocation.
696 void setPhysRegUnused(unsigned Reg) {
697 UsedPhysRegMask.reset(Reg);
698 for (MCRegUnitIterator Units(Reg, getTargetRegisterInfo());
699 Units.isValid(); ++Units)
700 UsedRegUnits.reset(*Units);
701 }
702
703648
704649 //===--------------------------------------------------------------------===//
705650 // Reserved Register Info
732732 // If no relevant registers are used in the function, we can skip it
733733 // completely.
734734 bool anyregs = false;
735 const MachineRegisterInfo &MRI = mf.getRegInfo();
735736 for (TargetRegisterClass::const_iterator I = RC->begin(), E = RC->end();
736 I != E; ++I)
737 if (MF->getRegInfo().isPhysRegUsed(*I)) {
738 anyregs = true;
739 break;
740 }
737 I != E && !anyregs; ++I)
738 for (MCRegAliasIterator AI(*I, TRI, true); AI.isValid(); ++AI)
739 if (!MRI.reg_nodbg_empty(*AI)) {
740 anyregs = true;
741 break;
742 }
741743 if (!anyregs) return false;
742744
743745 // Initialize the AliasMap on the first use.
1414 #include "RegisterCoalescer.h"
1515 #include "llvm/ADT/Statistic.h"
1616 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
17 #include "llvm/CodeGen/MachineRegisterInfo.h"
1817 #include "llvm/CodeGen/VirtRegMap.h"
1918 #include "llvm/Support/Debug.h"
2019 #include "llvm/Support/Format.h"
2120 #include "llvm/Support/raw_ostream.h"
2221 #include "llvm/Target/TargetRegisterInfo.h"
22 #include "llvm/Target/TargetSubtargetInfo.h"
2323
2424 using namespace llvm;
2525
4848
4949 bool LiveRegMatrix::runOnMachineFunction(MachineFunction &MF) {
5050 TRI = MF.getSubtarget().getRegisterInfo();
51 MRI = &MF.getRegInfo();
5251 LIS = &getAnalysis();
5352 VRM = &getAnalysis();
5453
10099 << " to " << PrintReg(PhysReg, TRI) << ':');
101100 assert(!VRM->hasPhys(VirtReg.reg) && "Duplicate VirtReg assignment");
102101 VRM->assignVirt2Phys(VirtReg.reg, PhysReg);
103 MRI->setPhysRegUsed(PhysReg);
104102
105103 foreachUnit(TRI, VirtReg, PhysReg, [&](unsigned Unit,
106104 const LiveRange &Range) {
2828 TracksSubRegLiveness(false) {
2929 VRegInfo.reserve(256);
3030 RegAllocHints.reserve(256);
31 UsedRegUnits.resize(getTargetRegisterInfo()->getNumRegUnits());
3231 UsedPhysRegMask.resize(getTargetRegisterInfo()->getNumRegs());
3332
3433 // Create the physreg use/def lists.
10251025 // Replace this reference to the virtual register with the
10261026 // scratch register.
10271027 assert (ScratchReg && "Missing scratch register!");
1028 MachineRegisterInfo &MRI = Fn.getRegInfo();
10291028 Fn.getRegInfo().replaceRegWith(Reg, ScratchReg);
10301029
1031 // Make sure MRI now accounts this register as used.
1032 MRI.setPhysRegUsed(ScratchReg);
1033
10341030 // Because this instruction was processed by the RS before this
10351031 // register was allocated, make sure that the RS now records the
10361032 // register as being used.
985985 }
986986 }
987987
988 for (UsedInInstrSet::iterator
989 I = UsedInInstr.begin(), E = UsedInInstr.end(); I != E; ++I)
990 MRI->setRegUnitUsed(*I);
991
992988 // Track registers defined by instruction - early clobbers and tied uses at
993989 // this point.
994990 UsedInInstr.clear();
10491045 killVirtReg(VirtDead[i]);
10501046 VirtDead.clear();
10511047
1052 for (UsedInInstrSet::iterator
1053 I = UsedInInstr.begin(), E = UsedInInstr.end(); I != E; ++I)
1054 MRI->setRegUnitUsed(*I);
1055
10561048 if (CopyDst && CopyDst == CopySrc && CopyDstSub == CopySrcSub) {
10571049 DEBUG(dbgs() << "-- coalescing: " << *MI);
10581050 Coalesced.push_back(MI);
11021094 AllocateBasicBlock();
11031095 }
11041096
1105 // Add the clobber lists for all the instructions we skipped earlier.
1106 for (const MCInstrDesc *Desc : SkippedInstrs)
1107 if (const uint16_t *Defs = Desc->getImplicitDefs())
1108 while (*Defs)
1109 MRI->setPhysRegUsed(*Defs++);
1110
11111097 // All machine operands and other references to virtual registers have been
11121098 // replaced. Remove the virtual registers.
11131099 MRI->clearVirtRegs();
162162 SlotIndexes *Indexes;
163163 LiveIntervals *LIS;
164164 VirtRegMap *VRM;
165 SparseSet PhysRegs;
166165
167166 void rewrite();
168167 void addMBBLiveIns();
318317 SmallVector SuperDeads;
319318 SmallVector SuperDefs;
320319 SmallVector SuperKills;
321 SmallPtrSet NoReturnInsts;
322
323 // Here we have a SparseSet to hold which PhysRegs are actually encountered
324 // in the MF we are about to iterate over so that later when we call
325 // setPhysRegUsed, we are only doing it for physRegs that were actually found
326 // in the program and not for all of the possible physRegs for the given
327 // target architecture. If the target has a lot of physRegs, then for a small
328 // program there will be a significant compile time reduction here.
329 PhysRegs.clear();
330 PhysRegs.setUniverse(TRI->getNumRegs());
331
332 // The function with uwtable should guarantee that the stack unwinder
333 // can unwind the stack to the previous frame. Thus, we can't apply the
334 // noreturn optimization if the caller function has uwtable attribute.
335 bool HasUWTable = MF->getFunction()->hasFnAttribute(Attribute::UWTable);
336320
337321 for (MachineFunction::iterator MBBI = MF->begin(), MBBE = MF->end();
338322 MBBI != MBBE; ++MBBI) {
339323 DEBUG(MBBI->print(dbgs(), Indexes));
340 bool IsExitBB = MBBI->succ_empty();
341324 for (MachineBasicBlock::instr_iterator
342325 MII = MBBI->instr_begin(), MIE = MBBI->instr_end(); MII != MIE;) {
343326 MachineInstr *MI = MII;
344327 ++MII;
345328
346 // Check if this instruction is a call to a noreturn function. If this
347 // is a call to noreturn function and we don't need the stack unwinding
348 // functionality (i.e. this function does not have uwtable attribute and
349 // the callee function has the nounwind attribute), then we can ignore
350 // the definitions set by this instruction.
351 if (!HasUWTable && IsExitBB && MI->isCall()) {
352 for (MachineInstr::mop_iterator MOI = MI->operands_begin(),
353 MOE = MI->operands_end(); MOI != MOE; ++MOI) {
354 MachineOperand &MO = *MOI;
355 if (!MO.isGlobal())
356 continue;
357 const Function *Func = dyn_cast(MO.getGlobal());
358 if (!Func || !Func->hasFnAttribute(Attribute::NoReturn) ||
359 // We need to keep correct unwind information
360 // even if the function will not return, since the
361 // runtime may need it.
362 !Func->hasFnAttribute(Attribute::NoUnwind))
363 continue;
364 NoReturnInsts.insert(MI);
365 break;
366 }
367 }
368
369329 for (MachineInstr::mop_iterator MOI = MI->operands_begin(),
370330 MOE = MI->operands_end(); MOI != MOE; ++MOI) {
371331 MachineOperand &MO = *MOI;
373333 // Make sure MRI knows about registers clobbered by regmasks.
374334 if (MO.isRegMask())
375335 MRI->addPhysRegsUsedFromRegMask(MO.getRegMask());
376
377 // If we encounter a VirtReg or PhysReg then get at the PhysReg and add
378 // it to the physreg bitset. Later we use only the PhysRegs that were
379 // actually encountered in the MF to populate the MRI's used physregs.
380 if (MO.isReg() && MO.getReg())
381 PhysRegs.insert(
382 TargetRegisterInfo::isVirtualRegister(MO.getReg()) ?
383 VRM->getPhys(MO.getReg()) :
384 MO.getReg());
385336
386337 if (!MO.isReg() || !TargetRegisterInfo::isVirtualRegister(MO.getReg()))
387338 continue;
469420 }
470421 }
471422 }
472
473 // Tell MRI about physical registers in use.
474 if (NoReturnInsts.empty()) {
475 for (SparseSet::iterator
476 RegI = PhysRegs.begin(), E = PhysRegs.end(); RegI != E; ++RegI)
477 if (!MRI->reg_nodbg_empty(*RegI))
478 MRI->setPhysRegUsed(*RegI);
479 } else {
480 for (SparseSet::iterator
481 I = PhysRegs.begin(), E = PhysRegs.end(); I != E; ++I) {
482 unsigned Reg = *I;
483 if (MRI->reg_nodbg_empty(Reg))
484 continue;
485 // Check if this register has a use that will impact the rest of the
486 // code. Uses in debug and noreturn instructions do not impact the
487 // generated code.
488 for (MachineInstr &It : MRI->reg_nodbg_instructions(Reg)) {
489 if (!NoReturnInsts.count(&It)) {
490 MRI->setPhysRegUsed(Reg);
491 break;
492 }
493 }
494 }
495 }
496 }
497
423 }
424
592592 if (Change) {
593593 Substs[MO.getReg()] = Reg;
594594 MO.setReg(Reg);
595 MRI->setPhysRegUsed(Reg);
596595
597596 Changed = true;
598597 }
353353 if (NumBytes && NeedsRealignment) {
354354 // Use the first callee-saved register as a scratch register.
355355 scratchSPReg = AArch64::X9;
356 MF.getRegInfo().setPhysRegUsed(scratchSPReg);
357356 }
358357
359358 // If we're a leaf function, try using the red zone.
5252 if (!LaneVGPRs.count(LaneVGPRIdx)) {
5353 unsigned LaneVGPR = TRI->findUnusedRegister(MRI, &AMDGPU::VGPR_32RegClass);
5454 LaneVGPRs[LaneVGPRIdx] = LaneVGPR;
55 MRI.setPhysRegUsed(LaneVGPR);
5655
5756 // Add this register as live-in to all blocks to avoid machine verifer
5857 // complaining about use of an undefined physical register.
9090
9191 if (ScratchOffsetReg != AMDGPU::NoRegister) {
9292 // Found an SGPR to use
93 MRI.setPhysRegUsed(ScratchOffsetReg);
9493 BuildMI(*Entry, I, DL, TII->get(AMDGPU::S_MOV_B32), ScratchOffsetReg)
9594 .addReg(ScratchOffsetPreloadReg);
9695 } else {
498498
499499 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
500500 I != E; ++I) {
501 if (!MRI.isPhysRegUsed(*I))
501 if (MRI.reg_nodbg_empty(*I))
502502 return *I;
503503 }
504504 return AMDGPU::NoRegister;
863863 // Check for an unused caller-saved register.
864864 for ( ; *CallerSavedRegs; ++CallerSavedRegs) {
865865 MCPhysReg FreeReg = *CallerSavedRegs;
866 if (MRI.isPhysRegUsed(FreeReg))
866 if (!MRI.reg_nodbg_empty(FreeReg))
867867 continue;
868868
869869 // Check aliased register usage.
870870 bool IsCurrentRegUsed = false;
871871 for (MCRegAliasIterator AI(FreeReg, &HRI, false); AI.isValid(); ++AI)
872 if (MRI.isPhysRegUsed(*AI)) {
872 if (!MRI.reg_nodbg_empty(*AI)) {
873873 IsCurrentRegUsed = true;
874874 break;
875875 }
305305 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
306306 DebugLoc dl = MI->getDebugLoc();
307307
308 const MachineRegisterInfo &MRI = MF->getRegInfo();
308309 unsigned UsedRegMask = 0;
309310 for (unsigned i = 0; i != 32; ++i)
310 if (MF->getRegInfo().isPhysRegUsed(VRRegNo[i]))
311 if (MRI.isPhysRegModified(VRRegNo[i]))
311312 UsedRegMask |= 1 << (31-i);
312313
313314 // Live in and live out values already must be in the mask, so don't bother
189189 {
190190
191191 for (unsigned reg = SP::I0; reg <= SP::I7; ++reg)
192 if (MRI->isPhysRegUsed(reg))
192 if (!MRI->reg_nodbg_empty(reg))
193193 return false;
194194
195195 for (unsigned reg = SP::L0; reg <= SP::L7; ++reg)
196 if (MRI->isPhysRegUsed(reg))
196 if (!MRI->reg_nodbg_empty(reg))
197197 return false;
198198
199199 return true;
205205 MachineRegisterInfo &MRI = MF.getRegInfo();
206206 MachineFrameInfo *MFI = MF.getFrameInfo();
207207
208 return !(MFI->hasCalls() // has calls
209 || MRI.isPhysRegUsed(SP::L0) // Too many registers needed
210 || MRI.isPhysRegUsed(SP::O6) // %SP is used
211 || hasFP(MF)); // need %FP
208 return !(MFI->hasCalls() // has calls
209 || !MRI.reg_nodbg_empty(SP::L0) // Too many registers needed
210 || !MRI.reg_nodbg_empty(SP::O6) // %SP is used
211 || hasFP(MF)); // need %FP
212212 }
213213
214214 void SparcFrameLowering::remapRegsForLeafProc(MachineFunction &MF) const {
217217
218218 // Remap %i[0-7] to %o[0-7].
219219 for (unsigned reg = SP::I0; reg <= SP::I7; ++reg) {
220 if (!MRI.isPhysRegUsed(reg))
220 if (MRI.reg_nodbg_empty(reg))
221221 continue;
222222 unsigned mapped_reg = (reg - SP::I0 + SP::O0);
223 assert(!MRI.isPhysRegUsed(mapped_reg));
223 assert(MRI.reg_nodbg_empty(mapped_reg));
224224
225225 // Replace I register with O register.
226226 MRI.replaceRegWith(reg, mapped_reg);
227
228 // Mark the reg unused.
229 MRI.setPhysRegUnused(reg);
230227 }
231228
232229 // Rewrite MBB's Live-ins.
300300 bool FPIsUsed = false;
301301
302302 static_assert(X86::FP6 == X86::FP0+6, "Register enums aren't sorted right!");
303 const MachineRegisterInfo &MRI = MF.getRegInfo();
303304 for (unsigned i = 0; i <= 6; ++i)
304 if (MF.getRegInfo().isPhysRegUsed(X86::FP0+i)) {
305 if (!MRI.reg_nodbg_empty(X86::FP0 + i)) {
305306 FPIsUsed = true;
306307 break;
307308 }
16811681 .addImm(StackSize);
16821682 BuildMI(allocMBB, DL, TII.get(MOVri), Reg11)
16831683 .addImm(X86FI->getArgumentStackSize());
1684 MF.getRegInfo().setPhysRegUsed(Reg10);
1685 MF.getRegInfo().setPhysRegUsed(Reg11);
16861684 } else {
16871685 BuildMI(allocMBB, DL, TII.get(X86::PUSHi32))
16881686 .addImm(X86FI->getArgumentStackSize());