llvm.org GIT mirror llvm / 2a9df47
Expose the instruction contraint string as an argument to the NLdSt class. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80011 91177308-0d34-0410-b5e6-96231b3b80d8 Bob Wilson 11 years ago
2 changed file(s) with 20 addition(s) and 24 deletion(s). Raw diff Collapse all Expand all
12111211 }
12121212
12131213 class NLdSt
1214 string asm, list pattern>
1215 : NeonI {
1214 string asm, string cstr, list pattern>
1215 : NeonI {
12161216 let Inst{31-24} = 0b11110100;
12171217 }
12181218
182182
183183 // VLD1 : Vector Load (multiple single elements)
184184 class VLD1D
185 : NLdSt<(outs DPR:$dst), (ins addrmode6:$addr),
186 NoItinerary,
187 !strconcat(OpcodeStr, "\t\\{$dst\\}, $addr"),
185 : NLdSt<(outs DPR:$dst), (ins addrmode6:$addr), NoItinerary,
186 !strconcat(OpcodeStr, "\t\\{$dst\\}, $addr"), "",
188187 [(set DPR:$dst, (Ty (IntOp addrmode6:$addr)))]>;
189188 class VLD1Q
190 : NLdSt<(outs QPR:$dst), (ins addrmode6:$addr),
191 NoItinerary,
192 !strconcat(OpcodeStr, "\t${dst:dregpair}, $addr"),
189 : NLdSt<(outs QPR:$dst), (ins addrmode6:$addr), NoItinerary,
190 !strconcat(OpcodeStr, "\t${dst:dregpair}, $addr"), "",
193191 [(set QPR:$dst, (Ty (IntOp addrmode6:$addr)))]>;
194192
195193 def VLD1d8 : VLD1D<"vld1.8", v8i8, int_arm_neon_vld1>;
208206
209207 // VLD2 : Vector Load (multiple 2-element structures)
210208 class VLD2D
211 : NLdSt<(outs DPR:$dst1, DPR:$dst2), (ins addrmode6:$addr),
212 NoItinerary,
213 !strconcat(OpcodeStr, "\t\\{$dst1,$dst2\\}, $addr"), []>;
209 : NLdSt<(outs DPR:$dst1, DPR:$dst2), (ins addrmode6:$addr), NoItinerary,
210 !strconcat(OpcodeStr, "\t\\{$dst1,$dst2\\}, $addr"), "", []>;
214211
215212 def VLD2d8 : VLD2D<"vld2.8">;
216213 def VLD2d16 : VLD2D<"vld2.16">;
220217 class VLD3D
221218 : NLdSt<(outs DPR:$dst1, DPR:$dst2, DPR:$dst3), (ins addrmode6:$addr),
222219 NoItinerary,
223 !strconcat(OpcodeStr, "\t\\{$dst1,$dst2,$dst3\\}, $addr"), []>;
220 !strconcat(OpcodeStr, "\t\\{$dst1,$dst2,$dst3\\}, $addr"), "", []>;
224221
225222 def VLD3d8 : VLD3D<"vld3.8">;
226223 def VLD3d16 : VLD3D<"vld3.16">;
229226 // VLD4 : Vector Load (multiple 4-element structures)
230227 class VLD4D
231228 : NLdSt<(outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
232 (ins addrmode6:$addr),
233 NoItinerary,
234 !strconcat(OpcodeStr, "\t\\{$dst1,$dst2,$dst3,$dst4\\}, $addr"), []>;
229 (ins addrmode6:$addr), NoItinerary,
230 !strconcat(OpcodeStr, "\t\\{$dst1,$dst2,$dst3,$dst4\\}, $addr"),
231 "", []>;
235232
236233 def VLD4d8 : VLD4D<"vld4.8">;
237234 def VLD4d16 : VLD4D<"vld4.16">;
240237
241238 // VST1 : Vector Store (multiple single elements)
242239 class VST1D
243 : NLdSt<(outs), (ins addrmode6:$addr, DPR:$src),
244 NoItinerary,
245 !strconcat(OpcodeStr, "\t\\{$src\\}, $addr"),
240 : NLdSt<(outs), (ins addrmode6:$addr, DPR:$src), NoItinerary,
241 !strconcat(OpcodeStr, "\t\\{$src\\}, $addr"), "",
246242 [(IntOp addrmode6:$addr, (Ty DPR:$src))]>;
247243 class VST1Q
248 : NLdSt<(outs), (ins addrmode6:$addr, QPR:$src),
249 NoItinerary,
250 !strconcat(OpcodeStr, "\t${src:dregpair}, $addr"),
244 : NLdSt<(outs), (ins addrmode6:$addr, QPR:$src), NoItinerary,
245 !strconcat(OpcodeStr, "\t${src:dregpair}, $addr"), "",
251246 [(IntOp addrmode6:$addr, (Ty QPR:$src))]>;
252247
253248 def VST1d8 : VST1D<"vst1.8", v8i8, int_arm_neon_vst1>;
267262 // VST2 : Vector Store (multiple 2-element structures)
268263 class VST2D
269264 : NLdSt<(outs), (ins addrmode6:$addr, DPR:$src1, DPR:$src2), NoItinerary,
270 !strconcat(OpcodeStr, "\t\\{$src1,$src2\\}, $addr"), []>;
265 !strconcat(OpcodeStr, "\t\\{$src1,$src2\\}, $addr"), "", []>;
271266
272267 def VST2d8 : VST2D<"vst2.8">;
273268 def VST2d16 : VST2D<"vst2.16">;
277272 class VST3D
278273 : NLdSt<(outs), (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3),
279274 NoItinerary,
280 !strconcat(OpcodeStr, "\t\\{$src1,$src2,$src3\\}, $addr"), []>;
275 !strconcat(OpcodeStr, "\t\\{$src1,$src2,$src3\\}, $addr"), "", []>;
281276
282277 def VST3d8 : VST3D<"vst3.8">;
283278 def VST3d16 : VST3D<"vst3.16">;
287282 class VST4D
288283 : NLdSt<(outs), (ins addrmode6:$addr,
289284 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4), NoItinerary,
290 !strconcat(OpcodeStr, "\t\\{$src1,$src2,$src3,$src4\\}, $addr"), []>;
285 !strconcat(OpcodeStr, "\t\\{$src1,$src2,$src3,$src4\\}, $addr"),
286 "", []>;
291287
292288 def VST4d8 : VST4D<"vst4.8">;
293289 def VST4d16 : VST4D<"vst4.16">;