llvm.org GIT mirror llvm / 2a9d1ca
Remove custom allocation order boilerplate that is no longer needed. The register allocators automatically filter out reserved registers and place the callee saved registers last in the allocation order, so custom methods are no longer necessary just for that. Some targets still use custom allocation orders: ARM/Thumb: The high registers are removed from GPR in thumb mode. The NEON allocation orders prefer to use non-VFP2 registers first. X86: The GR8 classes omit AH-DH in x86-64 mode to avoid REX trouble. SystemZ: Some of the allocation orders are omitting R12 aliases without explanation. I don't understand this target well enough to fix that. It looks like all the boilerplate could be removed by reserving the right registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132781 91177308-0d34-0410-b5e6-96231b3b80d8 Jakob Stoklund Olesen 8 years ago
14 changed file(s) with 56 addition(s) and 663 deletion(s). Raw diff Collapse all Expand all
120120 // Non-volatile
121121 R9, R10, R11, R12, R13, R14,
122122 // Don't allocate 15, 30, 31
123 R15, R30, R31 ]> //zero
124 {
125 let MethodProtos = [{
126 iterator allocation_order_end(const MachineFunction &MF) const;
127 }];
128 let MethodBodies = [{
129 GPRCClass::iterator
130 GPRCClass::allocation_order_end(const MachineFunction &MF) const {
131 return end()-3;
132 }
133 }];
134 }
123 R15, R30, R31 ]>; //zero
135124
136125 def F4RC : RegisterClass<"Alpha", [f32], 64, [F0, F1,
137126 F10, F11, F12, F13, F14, F15, F16, F17, F18, F19,
138127 F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30,
139128 // Saved:
140129 F2, F3, F4, F5, F6, F7, F8, F9,
141 F31 ]> //zero
142 {
143 let MethodProtos = [{
144 iterator allocation_order_end(const MachineFunction &MF) const;
145 }];
146 let MethodBodies = [{
147 F4RCClass::iterator
148 F4RCClass::allocation_order_end(const MachineFunction &MF) const {
149 return end()-1;
150 }
151 }];
152 }
130 F31 ]>; //zero
153131
154132 def F8RC : RegisterClass<"Alpha", [f64], 64, [F0, F1,
155133 F10, F11, F12, F13, F14, F15, F16, F17, F18, F19,
156134 F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30,
157135 // Saved:
158136 F2, F3, F4, F5, F6, F7, F8, F9,
159 F31 ]> //zero
160 {
161 let MethodProtos = [{
162 iterator allocation_order_end(const MachineFunction &MF) const;
163 }];
164 let MethodBodies = [{
165 F8RCClass::iterator
166 F8RCClass::allocation_order_end(const MachineFunction &MF) const {
167 return end()-1;
168 }
169 }];
170 }
137 F31 ]>; //zero
244244
245245 def P : RegisterClass<"BF", [i32], 32, [P0, P1, P2, P3, P4, P5, FP, SP]> {
246246 let SubRegClasses = [(P16L lo16), (P16H hi16)];
247 let MethodProtos = [{
248 iterator allocation_order_end(const MachineFunction &MF) const;
249 }];
250 let MethodBodies = [{
251 PClass::iterator
252 PClass::allocation_order_end(const MachineFunction &MF) const {
253 const TargetMachine &TM = MF.getTarget();
254 const TargetFrameLowering *TFI = TM.getFrameLowering();
255 return allocation_order_begin(MF)
256 + (TFI->hasFP(MF) ? 7 : 6);
257 }
258 }];
259247 }
260248
261249 def I : RegisterClass<"BF", [i32], 32, [I0, I1, I2, I3]>;
267255 [R0, R1, R2, R3, R4, R5, R6, R7,
268256 P0, P1, P2, P3, P4, P5, FP, SP]> {
269257 let SubRegClasses = [(DP16L lo16), (DP16H hi16)];
270 let MethodProtos = [{
271 iterator allocation_order_end(const MachineFunction &MF) const;
272 }];
273 let MethodBodies = [{
274 DPClass::iterator
275 DPClass::allocation_order_end(const MachineFunction &MF) const {
276 const TargetMachine &TM = MF.getTarget();
277 const TargetFrameLowering *TFI = TM.getFrameLowering();
278 return allocation_order_begin(MF)
279 + (TFI->hasFP(MF) ? 15 : 14);
280 }
281 }];
282258 }
283259
284260 def GR : RegisterClass<"BF", [i32], 32,
286262 P0, P1, P2, P3, P4, P5,
287263 I0, I1, I2, I3, M0, M1, M2, M3,
288264 B0, B1, B2, B3, L0, L1, L2, L3,
289 FP, SP]> {
290 let MethodProtos = [{
291 iterator allocation_order_end(const MachineFunction &MF) const;
292 }];
293 let MethodBodies = [{
294 GRClass::iterator
295 GRClass::allocation_order_end(const MachineFunction &MF) const {
296 const TargetMachine &TM = MF.getTarget();
297 const TargetFrameLowering *TFI = TM.getFrameLowering();
298 return allocation_order_begin(MF)
299 + (TFI->hasFP(MF) ? 31 : 30);
300 }
301 }];
302 }
265 FP, SP]>;
303266
304267 def ALL : RegisterClass<"BF", [i32], 32,
305268 [R0, R1, R2, R3, R4, R5, R6, R7,
309272 FP, SP,
310273 A0X, A0W, A1X, A1W, ASTAT, RETS,
311274 LC0, LT0, LB0, LC1, LT1, LB1, CYCLES, CYCLES2,
312 USP, SEQSTAT, SYSCFG, RETI, RETX, RETN, RETE, EMUDAT]> {
313 let MethodProtos = [{
314 iterator allocation_order_end(const MachineFunction &MF) const;
315 }];
316 let MethodBodies = [{
317 ALLClass::iterator
318 ALLClass::allocation_order_end(const MachineFunction &MF) const {
319 const TargetMachine &TM = MF.getTarget();
320 const TargetFrameLowering *TFI = TM.getFrameLowering();
321 return allocation_order_begin(MF)
322 + (TFI->hasFP(MF) ? 31 : 30);
323 }
324 }];
325 }
275 USP, SEQSTAT, SYSCFG, RETI, RETX, RETN, RETE, EMUDAT]>;
326276
327277 def PI : RegisterClass<"BF", [i32], 32,
328 [P0, P1, P2, P3, P4, P5, I0, I1, I2, I3, FP, SP]> {
329 let MethodProtos = [{
330 iterator allocation_order_end(const MachineFunction &MF) const;
331 }];
332 let MethodBodies = [{
333 PIClass::iterator
334 PIClass::allocation_order_end(const MachineFunction &MF) const {
335 const TargetMachine &TM = MF.getTarget();
336 const TargetFrameLowering *TFI = TM.getFrameLowering();
337 return allocation_order_begin(MF)
338 + (TFI->hasFP(MF) ? 11 : 10);
339 }
340 }];
341 }
278 [P0, P1, P2, P3, P4, P5, I0, I1, I2, I3, FP, SP]>;
342279
343280 // We are going to pretend that CC and !CC are 32-bit registers, even though
344281 // they only can hold 1 bit.
169169 R101, R100, R99, R98, R97, R96, R95, R94, R93, R92, R91, R90, R89, R88, R87,
170170 R86, R85, R84, R83, R82, R81, R80,
171171 /* environment ptr, SP, LR */
172 R2, R1, R0 ]>
173 {
174 let MethodProtos = [{
175 iterator allocation_order_begin(const MachineFunction &MF) const;
176 iterator allocation_order_end(const MachineFunction &MF) const;
177 }];
178 let MethodBodies = [{
179 GPRCClass::iterator
180 GPRCClass::allocation_order_begin(const MachineFunction &MF) const {
181 return begin();
182 }
183 GPRCClass::iterator
184 GPRCClass::allocation_order_end(const MachineFunction &MF) const {
185 return end()-3; // don't allocate R2, R1, or R0 (envp, sp, lr)
186 }
187 }];
188 }
172 R2, R1, R0 ]>;
189173
190174 // The SPU's registers as 64-bit wide (double word integer) "preferred slot":
191175 def R64C : RegisterClass<"SPU", [i64], 128,
203187 R101, R100, R99, R98, R97, R96, R95, R94, R93, R92, R91, R90, R89, R88, R87,
204188 R86, R85, R84, R83, R82, R81, R80,
205189 /* environment ptr, SP, LR */
206 R2, R1, R0 ]>
207 {
208 let MethodProtos = [{
209 iterator allocation_order_begin(const MachineFunction &MF) const;
210 iterator allocation_order_end(const MachineFunction &MF) const;
211 }];
212 let MethodBodies = [{
213 R64CClass::iterator
214 R64CClass::allocation_order_begin(const MachineFunction &MF) const {
215 return begin();
216 }
217 R64CClass::iterator
218 R64CClass::allocation_order_end(const MachineFunction &MF) const {
219 return end()-3; // don't allocate R2, R1, or R0 (envp, sp, lr)
220 }
221 }];
222 }
190 R2, R1, R0 ]>;
223191
224192 // The SPU's registers as 64-bit wide (double word) FP "preferred slot":
225193 def R64FP : RegisterClass<"SPU", [f64], 128,
237205 R101, R100, R99, R98, R97, R96, R95, R94, R93, R92, R91, R90, R89, R88, R87,
238206 R86, R85, R84, R83, R82, R81, R80,
239207 /* environment ptr, SP, LR */
240 R2, R1, R0 ]>
241 {
242 let MethodProtos = [{
243 iterator allocation_order_begin(const MachineFunction &MF) const;
244 iterator allocation_order_end(const MachineFunction &MF) const;
245 }];
246 let MethodBodies = [{
247 R64FPClass::iterator
248 R64FPClass::allocation_order_begin(const MachineFunction &MF) const {
249 return begin();
250 }
251 R64FPClass::iterator
252 R64FPClass::allocation_order_end(const MachineFunction &MF) const {
253 return end()-3; // don't allocate R2, R1, or R0 (envp, sp, lr)
254 }
255 }];
256 }
208 R2, R1, R0 ]>;
257209
258210 // The SPU's registers as 32-bit wide (word) "preferred slot":
259211 def R32C : RegisterClass<"SPU", [i32], 128,
271223 R101, R100, R99, R98, R97, R96, R95, R94, R93, R92, R91, R90, R89, R88, R87,
272224 R86, R85, R84, R83, R82, R81, R80,
273225 /* environment ptr, SP, LR */
274 R2, R1, R0 ]>
275 {
276 let MethodProtos = [{
277 iterator allocation_order_begin(const MachineFunction &MF) const;
278 iterator allocation_order_end(const MachineFunction &MF) const;
279 }];
280 let MethodBodies = [{
281 R32CClass::iterator
282 R32CClass::allocation_order_begin(const MachineFunction &MF) const {
283 return begin();
284 }
285 R32CClass::iterator
286 R32CClass::allocation_order_end(const MachineFunction &MF) const {
287 return end()-3; // don't allocate R2, R1, or R0 (envp, sp, lr)
288 }
289 }];
290 }
226 R2, R1, R0 ]>;
291227
292228 // The SPU's registers as single precision floating point "preferred slot":
293229 def R32FP : RegisterClass<"SPU", [f32], 128,
305241 R101, R100, R99, R98, R97, R96, R95, R94, R93, R92, R91, R90, R89, R88, R87,
306242 R86, R85, R84, R83, R82, R81, R80,
307243 /* environment ptr, SP, LR */
308 R2, R1, R0 ]>
309 {
310 let MethodProtos = [{
311 iterator allocation_order_begin(const MachineFunction &MF) const;
312 iterator allocation_order_end(const MachineFunction &MF) const;
313 }];
314 let MethodBodies = [{
315 R32FPClass::iterator
316 R32FPClass::allocation_order_begin(const MachineFunction &MF) const {
317 return begin();
318 }
319 R32FPClass::iterator
320 R32FPClass::allocation_order_end(const MachineFunction &MF) const {
321 return end()-3; // don't allocate R2, R1, or R0 (envp, sp, lr)
322 }
323 }];
324 }
244 R2, R1, R0 ]>;
325245
326246 // The SPU's registers as 16-bit wide (halfword) "preferred slot":
327247 def R16C : RegisterClass<"SPU", [i16], 128,
339259 R101, R100, R99, R98, R97, R96, R95, R94, R93, R92, R91, R90, R89, R88, R87,
340260 R86, R85, R84, R83, R82, R81, R80,
341261 /* environment ptr, SP, LR */
342 R2, R1, R0 ]>
343 {
344 let MethodProtos = [{
345 iterator allocation_order_begin(const MachineFunction &MF) const;
346 iterator allocation_order_end(const MachineFunction &MF) const;
347 }];
348 let MethodBodies = [{
349 R16CClass::iterator
350 R16CClass::allocation_order_begin(const MachineFunction &MF) const {
351 return begin();
352 }
353 R16CClass::iterator
354 R16CClass::allocation_order_end(const MachineFunction &MF) const {
355 return end()-3; // don't allocate R2, R1, or R0 (envp, sp, lr)
356 }
357 }];
358 }
262 R2, R1, R0 ]>;
359263
360264 // The SPU's registers as 8-bit wide (byte) "preferred slot":
361265 def R8C : RegisterClass<"SPU", [i8], 128,
373277 R101, R100, R99, R98, R97, R96, R95, R94, R93, R92, R91, R90, R89, R88, R87,
374278 R86, R85, R84, R83, R82, R81, R80,
375279 /* environment ptr, SP, LR */
376 R2, R1, R0 ]>
377 {
378 let MethodProtos = [{
379 iterator allocation_order_begin(const MachineFunction &MF) const;
380 iterator allocation_order_end(const MachineFunction &MF) const;
381 }];
382 let MethodBodies = [{
383 R8CClass::iterator
384 R8CClass::allocation_order_begin(const MachineFunction &MF) const {
385 return begin();
386 }
387 R8CClass::iterator
388 R8CClass::allocation_order_end(const MachineFunction &MF) const {
389 return end()-3; // don't allocate R2, R1, or R0 (envp, sp, lr)
390 }
391 }];
392 }
280 R2, R1, R0 ]>;
393281
394282 // The SPU's registers as vector registers:
395283 def VECREG : RegisterClass<"SPU",
409297 R101, R100, R99, R98, R97, R96, R95, R94, R93, R92, R91, R90, R89, R88, R87,
410298 R86, R85, R84, R83, R82, R81, R80,
411299 /* environment ptr, SP, LR */
412 R2, R1, R0 ]>
413 {
414 let MethodProtos = [{
415 iterator allocation_order_begin(const MachineFunction &MF) const;
416 iterator allocation_order_end(const MachineFunction &MF) const;
417 }];
418 let MethodBodies = [{
419 VECREGClass::iterator
420 VECREGClass::allocation_order_begin(const MachineFunction &MF) const {
421 return begin();
422 }
423 VECREGClass::iterator
424 VECREGClass::allocation_order_end(const MachineFunction &MF) const {
425 return end()-3; // don't allocate R2, R1, or R0 (envp, sp, lr)
426 }
427 }];
428 }
300 R2, R1, R0 ]>;
130130 R17, // Return address for exceptions
131131 R18, // Reserved for assembler
132132 R19 // The frame-pointer
133 ]>
134 {
135 let MethodProtos = [{
136 iterator allocation_order_end(const MachineFunction &MF) const;
137 }];
138 let MethodBodies = [{
139 GPRClass::iterator
140 GPRClass::allocation_order_end(const MachineFunction &MF) const {
141 // The last 10 registers on the list above are reserved
142 return end()-10;
143 }
144 }];
145 }
133 ]>;
146134
147135 def SPR : RegisterClass<"MBlaze", [i32], 32,
148136 [
173161 RPVR11
174162 ]>
175163 {
176 let MethodProtos = [{
177 iterator allocation_order_end(const MachineFunction &MF) const;
178 }];
179 let MethodBodies = [{
180 SPRClass::iterator
181 SPRClass::allocation_order_end(const MachineFunction &MF) const {
182 // None of the special purpose registers are allocatable.
183 return end()-24;
184 }
185 }];
164 // None of the special purpose registers are allocatable.
165 let isAllocatable = 0;
186166 }
187167
188168 def CRC : RegisterClass<"MBlaze", [i32], 32, [CARRY]> {
7575 BitVector Reserved(getNumRegs());
7676 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
7777
78 // Mark 4 special registers as reserved.
78 // Mark 4 special registers with subregisters as reserved.
79 Reserved.set(MSP430::PCB);
80 Reserved.set(MSP430::SPB);
81 Reserved.set(MSP430::SRB);
82 Reserved.set(MSP430::CGB);
7983 Reserved.set(MSP430::PCW);
8084 Reserved.set(MSP430::SPW);
8185 Reserved.set(MSP430::SRW);
6969 // Frame pointer, sometimes allocable
7070 FPB,
7171 // Volatile, but not allocable
72 PCB, SPB, SRB, CGB]>
73 {
74 let MethodProtos = [{
75 iterator allocation_order_end(const MachineFunction &MF) const;
76 }];
77 let MethodBodies = [{
78 GR8Class::iterator
79 GR8Class::allocation_order_end(const MachineFunction &MF) const {
80 const TargetMachine &TM = MF.getTarget();
81 const TargetFrameLowering *TFI = TM.getFrameLowering();
82 // Depending on whether the function uses frame pointer or not, last 5 or 4
83 // registers on the list above are reserved
84 if (TFI->hasFP(MF))
85 return end()-5;
86 else
87 return end()-4;
88 }
89 }];
90 }
72 PCB, SPB, SRB, CGB]>;
9173
9274 def GR16 : RegisterClass<"MSP430", [i16], 16,
9375 // Volatile registers
9880 PCW, SPW, SRW, CGW]>
9981 {
10082 let SubRegClasses = [(GR8 subreg_8bit)];
101 let MethodProtos = [{
102 iterator allocation_order_end(const MachineFunction &MF) const;
103 }];
104 let MethodBodies = [{
105 GR16Class::iterator
106 GR16Class::allocation_order_end(const MachineFunction &MF) const {
107 const TargetMachine &TM = MF.getTarget();
108 const TargetFrameLowering *TFI = TM.getFrameLowering();
109 // Depending on whether the function uses frame pointer or not, last 5 or 4
110 // registers on the list above are reserved
111 if (TFI->hasFP(MF))
112 return end()-5;
113 else
114 return end()-4;
115 }
116 }];
11783 }
11884
126126 Reserved.set(Mips::SP);
127127 Reserved.set(Mips::FP);
128128 Reserved.set(Mips::RA);
129 Reserved.set(Mips::F31);
130 Reserved.set(Mips::D15);
129131
130132 // SRV4 requires that odd register can't be used.
131133 if (!Subtarget.isSingleFloat() && !Subtarget.isMips32())
164164 // Callee save
165165 S0, S1, S2, S3, S4, S5, S6, S7,
166166 // Reserved
167 ZERO, AT, K0, K1, GP, SP, FP, RA]>
168 {
169 let MethodProtos = [{
170 iterator allocation_order_end(const MachineFunction &MF) const;
171 }];
172 let MethodBodies = [{
173 CPURegsClass::iterator
174 CPURegsClass::allocation_order_end(const MachineFunction &MF) const {
175 // The last 8 registers on the list above are reserved
176 return end()-8;
177 }
178 }];
179 }
167 ZERO, AT, K0, K1, GP, SP, FP, RA]>;
180168
181169 // 64bit fp:
182170 // * FGR64 - 32 64-bit registers
193181 // Callee save
194182 F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30,
195183 // Reserved
196 F31]>
197 {
198 let MethodProtos = [{
199 iterator allocation_order_begin(const MachineFunction &MF) const;
200 iterator allocation_order_end(const MachineFunction &MF) const;
201 }];
202 let MethodBodies = [{
203
204 static const unsigned MIPS_FGR32[] = {
205 Mips::F0, Mips::F1, Mips::F2, Mips::F3, Mips::F12, Mips::F13,
206 Mips::F14, Mips::F15, Mips::F4, Mips::F5, Mips::F6, Mips::F7,
207 Mips::F8, Mips::F9, Mips::F10, Mips::F11, Mips::F16, Mips::F17,
208 Mips::F18, Mips::F19, Mips::F20, Mips::F21, Mips::F22, Mips::F23,
209 Mips::F24, Mips::F25, Mips::F26, Mips::F27, Mips::F28, Mips::F29,
210 Mips::F30
211 };
212
213 static const unsigned MIPS_SVR4_FGR32[] = {
214 Mips::F0, Mips::F2, Mips::F12, Mips::F14, Mips::F4,
215 Mips::F6, Mips::F8, Mips::F10, Mips::F16, Mips::F18,
216 Mips::F20, Mips::F22, Mips::F24, Mips::F26, Mips::F28, Mips::F30,
217 };
218
219 FGR32Class::iterator
220 FGR32Class::allocation_order_begin(const MachineFunction &MF) const {
221 const TargetMachine &TM = MF.getTarget();
222 const MipsSubtarget &Subtarget = TM.getSubtarget();
223
224 if (Subtarget.isMips32() || Subtarget.isSingleFloat())
225 return MIPS_FGR32;
226 else
227 return MIPS_SVR4_FGR32;
228 }
229
230 FGR32Class::iterator
231 FGR32Class::allocation_order_end(const MachineFunction &MF) const {
232 const TargetMachine &TM = MF.getTarget();
233 const MipsSubtarget &Subtarget = TM.getSubtarget();
234
235 if (Subtarget.isMips32() || Subtarget.isSingleFloat())
236 return MIPS_FGR32 + (sizeof(MIPS_FGR32) / sizeof(unsigned));
237 else
238 return MIPS_SVR4_FGR32 + (sizeof(MIPS_SVR4_FGR32) / sizeof(unsigned));
239 }
240 }];
241 }
184 F31]>;
242185
243186 def AFGR64 : RegisterClass<"Mips", [f64], 64,
244187 // Return Values and Arguments
248191 // Callee save
249192 D10, D11, D12, D13, D14,
250193 // Reserved
251 D15]>
252 {
194 D15]> {
253195 let SubRegClasses = [(FGR32 sub_fpeven, sub_fpodd)];
254 let MethodProtos = [{
255 iterator allocation_order_end(const MachineFunction &MF) const;
256 }];
257 let MethodBodies = [{
258 AFGR64Class::iterator
259 AFGR64Class::allocation_order_end(const MachineFunction &MF) const {
260 // The last register on the list above is reserved
261 return end()-1;
262 }
263 }];
264196 }
265197
266198 // Condition Register for floating point operations
278278 def GPRC : RegisterClass<"PPC", [i32], 32,
279279 [R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12,
280280 R30, R29, R28, R27, R26, R25, R24, R23, R22, R21, R20, R19, R18, R17,
281 R16, R15, R14, R13, R31, R0, R1, LR]>
282 {
283 let MethodProtos = [{
284 iterator allocation_order_begin(const MachineFunction &MF) const;
285 iterator allocation_order_end(const MachineFunction &MF) const;
286 }];
287 let MethodBodies = [{
288 GPRCClass::iterator
289 GPRCClass::allocation_order_begin(const MachineFunction &MF) const {
290 // 32-bit SVR4 ABI: r2 is reserved for the OS.
291 // 64-bit SVR4 ABI: r2 is reserved for the TOC pointer.
292 // Darwin: R2 is reserved for CR save/restore sequence.
293 return begin()+1;
294 }
295 GPRCClass::iterator
296 GPRCClass::allocation_order_end(const MachineFunction &MF) const {
297 // On PPC64, r13 is the thread pointer. Never allocate this register.
298 // Note that this is overconservative, as it also prevents allocation of
299 // R31 when the FP is not needed.
300 // When using the 32-bit SVR4 ABI, r13 is reserved for the Small Data Area
301 // pointer.
302 const PPCSubtarget &Subtarget = MF.getTarget().getSubtarget();
303 const PPCFrameLowering *PPCFI =
304 static_cast(MF.getTarget().getFrameLowering());
305
306 if (Subtarget.isPPC64() || Subtarget.isSVR4ABI())
307 return end()-5; // don't allocate R13, R31, R0, R1, LR
308
309 if (PPCFI->needsFP(MF))
310 return end()-4; // don't allocate R31, R0, R1, LR
311 else
312 return end()-3; // don't allocate R0, R1, LR
313 }
314 }];
315 }
281 R16, R15, R14, R13, R31, R0, R1, LR]>;
282
316283 def G8RC : RegisterClass<"PPC", [i64], 64,
317284 [X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12,
318285 X30, X29, X28, X27, X26, X25, X24, X23, X22, X21, X20, X19, X18, X17,
319 X16, X15, X14, X31, X13, X0, X1, LR8]>
320 {
321 let MethodProtos = [{
322 iterator allocation_order_begin(const MachineFunction &MF) const;
323 iterator allocation_order_end(const MachineFunction &MF) const;
324 }];
325 let MethodBodies = [{
326 G8RCClass::iterator
327 G8RCClass::allocation_order_begin(const MachineFunction &MF) const {
328 // 64-bit SVR4 ABI: r2 is reserved for the TOC pointer.
329 // Darwin: r2 is reserved for CR save/restore sequence.
330 return begin()+1;
331 }
332 G8RCClass::iterator
333 G8RCClass::allocation_order_end(const MachineFunction &MF) const {
334 const PPCFrameLowering *PPCFI =
335 static_cast(MF.getTarget().getFrameLowering());
336 if (PPCFI->needsFP(MF))
337 return end()-5;
338 else
339 return end()-4;
340 }
341 }];
342 }
286 X16, X15, X14, X31, X13, X0, X1, LR8]>;
343287
344288 // Allocate volatiles first, then non-volatiles in reverse order. With the SVR4
345289 // ABI the size of the Floating-point register save area is determined by the
3838
3939 BitVector SparcRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
4040 BitVector Reserved(getNumRegs());
41 // FIXME: G1 reserved for now for large imm generation by frame code.
42 Reserved.set(SP::G1);
4143 Reserved.set(SP::G2);
4244 Reserved.set(SP::G3);
4345 Reserved.set(SP::G4);
141141 def IntRegs : RegisterClass<"SP", [i32], 32, [L0, L1, L2, L3, L4, L5, L6, L7,
142142 I0, I1, I2, I3, I4, I5,
143143 O0, O1, O2, O3, O4, O5, O7,
144
145 // FIXME: G1 reserved for now for large imm generation by frame code.
146144 G1,
147145 // Non-allocatable regs:
148146 G2, G3, G4, // FIXME: OK for use only in
152150 I7, // return address
153151 G0, // constant zero
154152 G5, G6, G7 // reserved for kernel
155 ]> {
156 let MethodProtos = [{
157 iterator allocation_order_end(const MachineFunction &MF) const;
158 }];
159 let MethodBodies = [{
160 IntRegsClass::iterator
161 IntRegsClass::allocation_order_end(const MachineFunction &MF) const {
162 // FIXME: These special regs should be taken out of the regclass!
163 return end()-10 // Don't allocate special registers
164 -1; // FIXME: G1 reserved for large imm generation by frame code.
165 }
166 }];
167 }
153 ]>;
168154
169155 def FPRegs : RegisterClass<"SP", [f32], 32, [F0, F1, F2, F3, F4, F5, F6, F7, F8,
170156 F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21, F22,
513513 Reserved.set(X86::ES);
514514 Reserved.set(X86::FS);
515515 Reserved.set(X86::GS);
516
517 // Reserve the registers that only exist in 64-bit mode.
518 if (!Is64Bit) {
519 for (unsigned n = 0; n != 8; ++n) {
520 const unsigned GPR64[] = {
521 X86::R8, X86::R9, X86::R10, X86::R11,
522 X86::R12, X86::R13, X86::R14, X86::R15
523 };
524 for (const unsigned *AI = getOverlaps(GPR64[n]); unsigned Reg = *AI;
525 ++AI)
526 Reserved.set(Reg);
527
528 // XMM8, XMM9, ...
529 assert(X86::XMM15 == X86::XMM8+7);
530 for (const unsigned *AI = getOverlaps(X86::XMM8 + n); unsigned Reg = *AI;
531 ++AI)
532 Reserved.set(Reg);
533 }
534 }
516535
517536 return Reserved;
518537 }
325325 [AX, CX, DX, SI, DI, BX, BP, SP,
326326 R8W, R9W, R10W, R11W, R14W, R15W, R12W, R13W]> {
327327 let SubRegClasses = [(GR8 sub_8bit, sub_8bit_hi)];
328 let MethodProtos = [{
329 iterator allocation_order_begin(const MachineFunction &MF) const;
330 iterator allocation_order_end(const MachineFunction &MF) const;
331 }];
332 let MethodBodies = [{
333 static const unsigned X86_GR16_AO_64[] = {
334 X86::AX, X86::CX, X86::DX, X86::SI, X86::DI,
335 X86::R8W, X86::R9W, X86::R10W, X86::R11W,
336 X86::BX, X86::R14W, X86::R15W, X86::R12W, X86::R13W, X86::BP
337 };
338
339 GR16Class::iterator
340 GR16Class::allocation_order_begin(const MachineFunction &MF) const {
341 const TargetMachine &TM = MF.getTarget();
342 const X86Subtarget &Subtarget = TM.getSubtarget();
343 if (Subtarget.is64Bit())
344 return X86_GR16_AO_64;
345 else
346 return begin();
347 }
348
349 GR16Class::iterator
350 GR16Class::allocation_order_end(const MachineFunction &MF) const {
351 const TargetMachine &TM = MF.getTarget();
352 const TargetFrameLowering *TFI = TM.getFrameLowering();
353 const X86Subtarget &Subtarget = TM.getSubtarget();
354 const X86MachineFunctionInfo *MFI = MF.getInfo();
355 if (Subtarget.is64Bit()) {
356 // Does the function dedicate RBP to being a frame ptr?
357 if (TFI->hasFP(MF) || MFI->getReserveFP())
358 // If so, don't allocate SP or BP.
359 return array_endof(X86_GR16_AO_64) - 1;
360 else
361 // If not, just don't allocate SP.
362 return array_endof(X86_GR16_AO_64);
363 } else {
364 // Does the function dedicate EBP to being a frame ptr?
365 if (TFI->hasFP(MF) || MFI->getReserveFP())
366 // If so, don't allocate SP or BP.
367 return begin() + 6;
368 else
369 // If not, just don't allocate SP.
370 return begin() + 7;
371 }
372 }
373 }];
374328 }
375329
376330 def GR32 : RegisterClass<"X86", [i32], 32,
377331 [EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP,
378332 R8D, R9D, R10D, R11D, R14D, R15D, R12D, R13D]> {
379333 let SubRegClasses = [(GR8 sub_8bit, sub_8bit_hi), (GR16 sub_16bit)];
380 let MethodProtos = [{
381 iterator allocation_order_begin(const MachineFunction &MF) const;
382 iterator allocation_order_end(const MachineFunction &MF) const;
383 }];
384 let MethodBodies = [{
385 static const unsigned X86_GR32_AO_64[] = {
386 X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI,
387 X86::R8D, X86::R9D, X86::R10D, X86::R11D,
388 X86::EBX, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::EBP
389 };
390
391 GR32Class::iterator
392 GR32Class::allocation_order_begin(const MachineFunction &MF) const {
393 const TargetMachine &TM = MF.getTarget();
394 const X86Subtarget &Subtarget = TM.getSubtarget();
395 if (Subtarget.is64Bit())
396 return X86_GR32_AO_64;
397 else
398 return begin();
399 }
400
401 GR32Class::iterator
402 GR32Class::allocation_order_end(const MachineFunction &MF) const {
403 const TargetMachine &TM = MF.getTarget();
404 const TargetFrameLowering *TFI = TM.getFrameLowering();
405 const X86Subtarget &Subtarget = TM.getSubtarget();
406 const X86MachineFunctionInfo *MFI = MF.getInfo();
407 if (Subtarget.is64Bit()) {
408 // Does the function dedicate RBP to being a frame ptr?
409 if (TFI->hasFP(MF) || MFI->getReserveFP())
410 // If so, don't allocate ESP or EBP.
411 return array_endof(X86_GR32_AO_64) - 1;
412 else
413 // If not, just don't allocate ESP.
414 return array_endof(X86_GR32_AO_64);
415 } else {
416 // Does the function dedicate EBP to being a frame ptr?
417 if (TFI->hasFP(MF) || MFI->getReserveFP())
418 // If so, don't allocate ESP or EBP.
419 return begin() + 6;
420 else
421 // If not, just don't allocate ESP.
422 return begin() + 7;
423 }
424 }
425 }];
426334 }
427335
428336 // GR64 - 64-bit GPRs. This oddly includes RIP, which isn't accurate, since
543451 [EAX, ECX, EDX, ESI, EDI, EBX, EBP,
544452 R8D, R9D, R10D, R11D, R14D, R15D, R12D, R13D]> {
545453 let SubRegClasses = [(GR8 sub_8bit, sub_8bit_hi), (GR16 sub_16bit)];
546 let MethodProtos = [{
547 iterator allocation_order_begin(const MachineFunction &MF) const;
548 iterator allocation_order_end(const MachineFunction &MF) const;
549 }];
550 let MethodBodies = [{
551 static const unsigned X86_GR32_NOSP_AO_64[] = {
552 X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI,
553 X86::R8D, X86::R9D, X86::R10D, X86::R11D,
554 X86::EBX, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::EBP
555 };
556
557 GR32_NOSPClass::iterator
558 GR32_NOSPClass::allocation_order_begin(const MachineFunction &MF) const {
559 const TargetMachine &TM = MF.getTarget();
560 const X86Subtarget &Subtarget = TM.getSubtarget();
561 if (Subtarget.is64Bit())
562 return X86_GR32_NOSP_AO_64;
563 else
564 return begin();
565 }
566
567 GR32_NOSPClass::iterator
568 GR32_NOSPClass::allocation_order_end(const MachineFunction &MF) const {
569 const TargetMachine &TM = MF.getTarget();
570 const TargetFrameLowering *TFI = TM.getFrameLowering();
571 const X86Subtarget &Subtarget = TM.getSubtarget();
572 const X86MachineFunctionInfo *MFI = MF.getInfo();
573 if (Subtarget.is64Bit()) {
574 // Does the function dedicate RBP to being a frame ptr?
575 if (TFI->hasFP(MF) || MFI->getReserveFP())
576 // If so, don't allocate EBP.
577 return array_endof(X86_GR32_NOSP_AO_64) - 1;
578 else
579 // If not, any reg in this class is ok.
580 return array_endof(X86_GR32_NOSP_AO_64);
581 } else {
582 // Does the function dedicate EBP to being a frame ptr?
583 if (TFI->hasFP(MF) || MFI->getReserveFP())
584 // If so, don't allocate EBP.
585 return begin() + 6;
586 else
587 // If not, any reg in this class is ok.
588 return begin() + 7;
589 }
590 }
591 }];
592454 }
593455
594456 // GR64_NOSP - GR64 registers except RSP (and RIP).
627489 def FR32 : RegisterClass<"X86", [f32], 32,
628490 [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
629491 XMM8, XMM9, XMM10, XMM11,
630 XMM12, XMM13, XMM14, XMM15]> {
631 let MethodProtos = [{
632 iterator allocation_order_end(const MachineFunction &MF) const;
633 }];
634 let MethodBodies = [{
635 FR32Class::iterator
636 FR32Class::allocation_order_end(const MachineFunction &MF) const {
637 const TargetMachine &TM = MF.getTarget();
638 const X86Subtarget &Subtarget = TM.getSubtarget();
639 if (!Subtarget.is64Bit())
640 return end()-8; // Only XMM0 to XMM7 are available in 32-bit mode.
641 else
642 return end();
643 }
644 }];
645 }
492 XMM12, XMM13, XMM14, XMM15]>;
646493
647494 def FR64 : RegisterClass<"X86", [f64], 64,
648495 [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
649496 XMM8, XMM9, XMM10, XMM11,
650 XMM12, XMM13, XMM14, XMM15]> {
651 let MethodProtos = [{
652 iterator allocation_order_end(const MachineFunction &MF) const;
653 }];
654 let MethodBodies = [{
655 FR64Class::iterator
656 FR64Class::allocation_order_end(const MachineFunction &MF) const {
657 const TargetMachine &TM = MF.getTarget();
658 const X86Subtarget &Subtarget = TM.getSubtarget();
659 if (!Subtarget.is64Bit())
660 return end()-8; // Only XMM0 to XMM7 are available in 32-bit mode.
661 else
662 return end();
663 }
664 }];
665 }
497 XMM12, XMM13, XMM14, XMM15]>;
666498
667499
668500 // FIXME: This sets up the floating point register files as though they are f64
691523 XMM8, XMM9, XMM10, XMM11,
692524 XMM12, XMM13, XMM14, XMM15]> {
693525 let SubRegClasses = [(FR32 sub_ss), (FR64 sub_sd)];
694
695 let MethodProtos = [{
696 iterator allocation_order_end(const MachineFunction &MF) const;
697 }];
698 let MethodBodies = [{
699 VR128Class::iterator
700 VR128Class::allocation_order_end(const MachineFunction &MF) const {
701 const TargetMachine &TM = MF.getTarget();
702 const X86Subtarget &Subtarget = TM.getSubtarget();
703 if (!Subtarget.is64Bit())
704 return end()-8; // Only XMM0 to XMM7 are available in 32-bit mode.
705 else
706 return end();
707 }
708 }];
709526 }
710527
711528 def VR256 : RegisterClass<"X86", [v32i8, v8i32, v4i64, v8f32, v4f64], 256,
713530 YMM8, YMM9, YMM10, YMM11,
714531 YMM12, YMM13, YMM14, YMM15]> {
715532 let SubRegClasses = [(FR32 sub_ss), (FR64 sub_sd), (VR128 sub_xmm)];
716
717 let MethodProtos = [{
718 iterator allocation_order_end(const MachineFunction &MF) const;
719 }];
720 let MethodBodies = [{
721 VR256Class::iterator
722 VR256Class::allocation_order_end(const MachineFunction &MF) const {
723 const TargetMachine &TM = MF.getTarget();
724 const X86Subtarget &Subtarget = TM.getSubtarget();
725 if (!Subtarget.is64Bit())
726 return end()-8; // Only YMM0 to YMM7 are available in 32-bit mode.
727 else
728 return end();
729 }
730 }];
731533 }
732534
733535 // Status flags registers.
4747 // Not preserved across procedure calls
4848 R11,
4949 // Callee save
50 R4, R5, R6, R7, R8, R9, R10]> {
51 let MethodProtos = [{
52 iterator allocation_order_begin(const MachineFunction &MF) const;
53 iterator allocation_order_end(const MachineFunction &MF) const;
54 }];
55 let MethodBodies = [{
56 GRRegsClass::iterator
57 GRRegsClass::allocation_order_begin(const MachineFunction &MF) const {
58 return begin();
59 }
60 GRRegsClass::iterator
61 GRRegsClass::allocation_order_end(const MachineFunction &MF) const {
62 const TargetMachine &TM = MF.getTarget();
63 const TargetFrameLowering *TFI = TM.getFrameLowering();
64 if (TFI->hasFP(MF))
65 return end()-1; // don't allocate R10
66 else
67 return end();
68 }
69 }];
70 }
50 R4, R5, R6, R7, R8, R9, R10]>;
7151
7252 // Reserved
7353 def RRegs : RegisterClass<"XCore", [i32], 32, [CP, DP, SP, LR]> {