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[ARM] Correct handling of LSL #0 in an IT block The check for LSL #0 in an IT block was checking if operand 4 was zero, but operand 4 is the condition code operand so it was actually checking for LSLEQ. Fix this by checking operand 3, which really is the immediate operand, and add some tests. Differential Revision: https://reviews.llvm.org/D30692 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297142 91177308-0d34-0410-b5e6-96231b3b80d8 John Brawn 3 years ago
2 changed file(s) with 15 addition(s) and 1 deletion(s). Raw diff Collapse all Expand all
89398939 inITBlock())
89408940 return Match_RequiresNotITBlock;
89418941 // LSL with zero immediate is not allowed in an IT block
8942 if (Opc == ARM::tLSLri && Inst.getOperand(4).getImm() == 0 && inITBlock())
8942 if (Opc == ARM::tLSLri && Inst.getOperand(3).getImm() == 0 && inITBlock())
89438943 return Match_RequiresNotITBlock;
89448944 } else if (isThumbOne()) {
89458945 // Some high-register supporting Thumb1 encodings only allow both registers
121121 itt eq
122122 lsleq r0, r1, #0
123123 lslseq r0, r1, #0
124 itt gt
125 lslgt r0, r1, #0
126 lslsgt r0, r1, #0
124127
125128 // CHECK-NONARM: moveq.w r0, r1 @ encoding: [0x4f,0xea,0x01,0x00]
126129 // CHECK-NONARM: movseq.w r0, r1 @ encoding: [0x5f,0xea,0x01,0x00]
130 // CHECK-NONARM: movgt.w r0, r1 @ encoding: [0x4f,0xea,0x01,0x00]
131 // CHECK-NONARM: movsgt.w r0, r1 @ encoding: [0x5f,0xea,0x01,0x00]
127132
128133 // CHECK-ARM: moveq r0, r1 @ encoding: [0x01,0x00,0xa0,0x01]
129134 // CHECK-ARM: movseq r0, r1 @ encoding: [0x01,0x00,0xb0,0x01]
135 // CHECK-ARM: movgt r0, r1 @ encoding: [0x01,0x00,0xa0,0xc1]
136 // CHECK-ARM: movsgt r0, r1 @ encoding: [0x01,0x00,0xb0,0xc1]
130137
131138 itt eq
132139 moveq r0, r1, lsl #0
133140 movseq r0, r1, lsl #0
141 itt gt
142 movgt r0, r1, lsl #0
143 movsgt r0, r1, lsl #0
134144
135145 // CHECK-NONARM: moveq.w r0, r1 @ encoding: [0x4f,0xea,0x01,0x00]
136146 // CHECK-NONARM: movseq.w r0, r1 @ encoding: [0x5f,0xea,0x01,0x00]
147 // CHECK-NONARM: movgt.w r0, r1 @ encoding: [0x4f,0xea,0x01,0x00]
148 // CHECK-NONARM: movsgt.w r0, r1 @ encoding: [0x5f,0xea,0x01,0x00]
137149
138150 // CHECK-ARM: moveq r0, r1 @ encoding: [0x01,0x00,0xa0,0x01]
139151 // CHECK-ARM: movseq r0, r1 @ encoding: [0x01,0x00,0xb0,0x01]
152 // CHECK-ARM: movgt r0, r1 @ encoding: [0x01,0x00,0xa0,0xc1]
153 // CHECK-ARM: movsgt r0, r1 @ encoding: [0x01,0x00,0xb0,0xc1]