llvm.org GIT mirror llvm / 2a7b41b
Refact ARM Thumb1 tMOVr instruction family. Merge the tMOVr, tMOVgpr2tgpr, tMOVtgpr2gpr, and tMOVgpr2gpr instructions into tMOVr. There's no need to keep them separate. Giving the tMOVr instruction the proper GPR register class for its operands is sufficient to give the register allocator enough information to do the right thing directly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134204 91177308-0d34-0410-b5e6-96231b3b80d8 Jim Grosbach 9 years ago
9 changed file(s) with 26 addition(s) and 86 deletion(s). Raw diff Collapse all Expand all
10091009 MI->dump();
10101010 assert(0 && "Unsupported opcode for unwinding information");
10111011 case ARM::MOVr:
1012 case ARM::tMOVgpr2gpr:
1013 case ARM::tMOVgpr2tgpr:
10141012 Offset = 0;
10151013 break;
10161014 case ARM::ADDri:
14551453 case ARM::t2BR_JT: {
14561454 // Lower and emit the instruction itself, then the jump table following it.
14571455 MCInst TmpInst;
1458 TmpInst.setOpcode(ARM::tMOVgpr2gpr);
1456 TmpInst.setOpcode(ARM::tMOVr);
14591457 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
14601458 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
14611459 // Add predicate operands.
15041502 // mov pc, target
15051503 MCInst TmpInst;
15061504 unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
1507 ARM::MOVr : ARM::tMOVgpr2gpr;
1505 ARM::MOVr : ARM::tMOVr;
15081506 TmpInst.setOpcode(Opc);
15091507 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
15101508 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
15171515 OutStreamer.EmitInstruction(TmpInst);
15181516
15191517 // Make sure the Thumb jump table is 4-byte aligned.
1520 if (Opc == ARM::tMOVgpr2gpr)
1518 if (Opc == ARM::tMOVr)
15211519 EmitAlignment(2);
15221520
15231521 // Output the data for the jump table itself
16091607 MCSymbol *Label = GetARMSJLJEHLabel();
16101608 {
16111609 MCInst TmpInst;
1612 TmpInst.setOpcode(ARM::tMOVgpr2tgpr);
1610 TmpInst.setOpcode(ARM::tMOVr);
16131611 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
16141612 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
16151613 // Predicate.
18281826 }
18291827 {
18301828 MCInst TmpInst;
1831 TmpInst.setOpcode(ARM::tMOVtgpr2gpr);
1829 TmpInst.setOpcode(ARM::tMOVr);
18321830 TmpInst.addOperand(MCOperand::CreateReg(ARM::SP));
18331831 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
18341832 // Predicate.
267267 // bic r4, r4, MaxAlign
268268 // mov sp, r4
269269 // FIXME: It will be better just to find spare register here.
270 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2tgpr), ARM::R4)
270 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::R4)
271271 .addReg(ARM::SP, RegState::Kill));
272272 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl,
273273 TII.get(ARM::t2BICri), ARM::R4)
274274 .addReg(ARM::R4, RegState::Kill)
275275 .addImm(MaxAlign-1)));
276 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::SP)
276 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP)
277277 .addReg(ARM::R4, RegState::Kill));
278278 }
279279
292292 .addReg(ARM::SP)
293293 .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
294294 else
295 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr),
295 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
296296 RegInfo->getBaseRegister())
297297 .addReg(ARM::SP));
298298 }
363363 "No scratch register to restore SP from FP!");
364364 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes,
365365 ARMCC::AL, 0, TII);
366 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr),
366 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
367367 ARM::SP)
368368 .addReg(ARM::R4));
369369 }
373373 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP)
374374 .addReg(FramePtr).addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
375375 else
376 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr),
376 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
377377 ARM::SP)
378378 .addReg(FramePtr));
379379 }
10531053 // TODO: A7-73: MOV(2) - mov setting flag.
10541054
10551055 let neverHasSideEffects = 1 in {
1056 def tMOVr : Thumb1pI<(outs tGPR:$Rd), (ins tGPR:$Rm), AddrModeNone,
1056 def tMOVr : Thumb1pI<(outs GPR:$Rd), (ins GPR:$Rm), AddrModeNone,
10571057 Size2Bytes, IIC_iMOVr,
10581058 "mov", "\t$Rd, $Rm", "", []>,
1059 T1Special<0b1000> {
1059 T1Special<{1,0,?,?}> {
10601060 // A8.6.97
10611061 bits<4> Rd;
10621062 bits<4> Rm;
1063 // Bits {7-6} are encoded by the T1Special value.
1064 let Inst{5-3} = Rm{2-0};
1063 let Inst{7} = Rd{3};
1064 let Inst{6-3} = Rm;
10651065 let Inst{2-0} = Rd{2-0};
10661066 }
10671067 let Defs = [CPSR] in
10731073 let Inst{15-6} = 0b0000000000;
10741074 let Inst{5-3} = Rm;
10751075 let Inst{2-0} = Rd;
1076 }
1077
1078 // FIXME: Do we really need separate instructions for GPR<-->tGPR like this?
1079 // They all map to the same instruction (MOV encoding T1).
1080 def tMOVgpr2tgpr : Thumb1pI<(outs tGPR:$Rd), (ins GPR:$Rm), AddrModeNone,
1081 Size2Bytes, IIC_iMOVr, "mov", "\t$Rd, $Rm", "", []>,
1082 T1Special<{1,0,0,?}> {
1083 // A8.6.97
1084 bits<4> Rd;
1085 bits<4> Rm;
1086 // Bit {7} is encoded by the T1Special value.
1087 let Inst{6-3} = Rm;
1088 let Inst{2-0} = Rd{2-0};
1089 }
1090 def tMOVtgpr2gpr : Thumb1pI<(outs GPR:$Rd), (ins tGPR:$Rm), AddrModeNone,
1091 Size2Bytes, IIC_iMOVr, "mov", "\t$Rd, $Rm", "", []>,
1092 T1Special<{1,0,?,0}> {
1093 // A8.6.97
1094 bits<4> Rd;
1095 bits<4> Rm;
1096 // Bit {6} is encoded by the T1Special value.
1097 let Inst{7} = Rd{3};
1098 let Inst{5-3} = Rm{2-0};
1099 let Inst{2-0} = Rd{2-0};
1100 }
1101 def tMOVgpr2gpr : Thumb1pI<(outs GPR:$Rd), (ins GPR:$Rm), AddrModeNone,
1102 Size2Bytes, IIC_iMOVr, "mov", "\t$Rd, $Rm", "", []>,
1103 T1Special<{1,0,?,?}> {
1104 // A8.6.97
1105 bits<4> Rd;
1106 bits<4> Rm;
1107 let Inst{7} = Rd{3};
1108 let Inst{6-3} = Rm;
1109 let Inst{2-0} = Rd{2-0};
11101076 }
11111077 } // neverHasSideEffects
11121078
159159 // will be allocated after this, so we can still use the base pointer
160160 // to reference locals.
161161 if (RegInfo->hasBasePointer(MF))
162 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr), BasePtr)
162 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), BasePtr)
163163 .addReg(ARM::SP));
164164
165165 // If the frame has variable sized objects then the epilogue must restore
239239 "No scratch register to restore SP from FP!");
240240 emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes,
241241 TII, *RegInfo);
242 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVtgpr2gpr),
242 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
243243 ARM::SP)
244244 .addReg(ARM::R4));
245245 } else
246 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVtgpr2gpr),
246 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
247247 ARM::SP)
248248 .addReg(FramePtr));
249249 } else {
3535 MachineBasicBlock::iterator I, DebugLoc DL,
3636 unsigned DestReg, unsigned SrcReg,
3737 bool KillSrc) const {
38 bool tDest = ARM::tGPRRegClass.contains(DestReg);
39 bool tSrc = ARM::tGPRRegClass.contains(SrcReg);
40 unsigned Opc = ARM::tMOVgpr2gpr;
41 if (tDest && tSrc)
42 Opc = ARM::tMOVr;
43 else if (tSrc)
44 Opc = ARM::tMOVtgpr2gpr;
45 else if (tDest)
46 Opc = ARM::tMOVgpr2tgpr;
47
48 AddDefaultPred(BuildMI(MBB, I, DL, get(Opc), DestReg)
38 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)
4939 .addReg(SrcReg, getKillRegState(KillSrc)));
5040 assert(ARM::GPRRegClass.contains(DestReg, SrcReg) &&
5141 "Thumb1 can only copy GPR registers");
416416 unsigned PredReg;
417417 if (Offset == 0 && getInstrPredicate(&MI, PredReg) == ARMCC::AL) {
418418 // Turn it into a move.
419 MI.setDesc(TII.get(ARM::tMOVgpr2tgpr));
419 MI.setDesc(TII.get(ARM::tMOVr));
420420 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
421421 // Remove offset and add predicate operands.
422422 MI.RemoveOperand(FrameRegIdx+1);
563563 // the function, the offset will be negative. Use R12 instead since that's
564564 // a call clobbered register that we know won't be used in Thumb1 mode.
565565 DebugLoc DL;
566 AddDefaultPred(BuildMI(MBB, I, DL, TII.get(ARM::tMOVtgpr2gpr))
566 AddDefaultPred(BuildMI(MBB, I, DL, TII.get(ARM::tMOVr))
567567 .addReg(ARM::R12, RegState::Define)
568568 .addReg(Reg, RegState::Kill));
569569
588588 }
589589 }
590590 // Restore the register from R12
591 AddDefaultPred(BuildMI(MBB, UseMI, DL, TII.get(ARM::tMOVgpr2tgpr)).
591 AddDefaultPred(BuildMI(MBB, UseMI, DL, TII.get(ARM::tMOVr)).
592592 addReg(Reg, RegState::Define).addReg(ARM::R12, RegState::Kill));
593593
594594 return true;
9797 case ARM::MOVr:
9898 case ARM::MOVr_TC:
9999 case ARM::tMOVr:
100 case ARM::tMOVgpr2tgpr:
101 case ARM::tMOVtgpr2gpr:
102 case ARM::tMOVgpr2gpr:
103100 case ARM::t2MOVr:
104101 return true;
105102 }
111111 if (!ARM::GPRRegClass.contains(DestReg, SrcReg))
112112 return ARMBaseInstrInfo::copyPhysReg(MBB, I, DL, DestReg, SrcReg, KillSrc);
113113
114 bool tDest = ARM::tGPRRegClass.contains(DestReg);
115 bool tSrc = ARM::tGPRRegClass.contains(SrcReg);
116 unsigned Opc = ARM::tMOVgpr2gpr;
117 if (tDest && tSrc)
118 Opc = ARM::tMOVr;
119 else if (tSrc)
120 Opc = ARM::tMOVtgpr2gpr;
121 else if (tDest)
122 Opc = ARM::tMOVgpr2tgpr;
123
124 AddDefaultPred(BuildMI(MBB, I, DL, get(Opc), DestReg)
114 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)
125115 .addReg(SrcReg, getKillRegState(KillSrc)));
126116 }
127117
230220 unsigned Opc = 0;
231221 if (DestReg == ARM::SP && BaseReg != ARM::SP) {
232222 // mov sp, rn. Note t2MOVr cannot be used.
233 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr),DestReg)
223 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),DestReg)
234224 .addReg(BaseReg).setMIFlags(MIFlags));
235225 BaseReg = ARM::SP;
236226 continue;
408398 unsigned PredReg;
409399 if (Offset == 0 && getInstrPredicate(&MI, PredReg) == ARMCC::AL) {
410400 // Turn it into a move.
411 MI.setDesc(TII.get(ARM::tMOVgpr2gpr));
401 MI.setDesc(TII.get(ARM::tMOVr));
412402 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
413403 // Remove offset and remaining explicit predicate operands.
414404 do MI.RemoveOperand(FrameRegIdx+1);
574564 Thumb2InstrInfo::scheduleTwoAddrSource(MachineInstr *SrcMI,
575565 MachineInstr *UseMI,
576566 const TargetRegisterInfo &TRI) const {
577 if (SrcMI->getOpcode() != ARM::tMOVgpr2gpr ||
578 SrcMI->getOperand(1).isKill())
567 if (SrcMI->getOpcode() != ARM::tMOVr || SrcMI->getOperand(1).isKill())
579568 return;
580569
581570 unsigned PredReg = 0;
8181 { ARM::t2MOVi, ARM::tMOVi8, 0, 8, 0, 1, 0, 0,0, 0,0 },
8282 { ARM::t2MOVi16,ARM::tMOVi8, 0, 8, 0, 1, 0, 0,0, 0,1 },
8383 // FIXME: Do we need the 16-bit 'S' variant?
84 { ARM::t2MOVr,ARM::tMOVgpr2gpr,0, 0, 0, 0, 0, 1,0, 0,0 },
84 { ARM::t2MOVr,ARM::tMOVr, 0, 0, 0, 0, 0, 1,0, 0,0 },
8585 { ARM::t2MOVCCr,0, ARM::tMOVCCr, 0, 0, 0, 0, 0,1, 0,0 },
8686 { ARM::t2MOVCCi,0, ARM::tMOVCCi, 0, 8, 0, 1, 0,1, 0,0 },
8787 { ARM::t2MUL, 0, ARM::tMUL, 0, 0, 0, 1, 0,0, 1,0 },