llvm.org GIT mirror llvm / 2a613d6
Prevent renaming of CR fields in AADB when a CR restore is present This patch corresponds to review: http://reviews.llvm.org/D15930 Moves to and from CR fields depend on shifts/masks that depend on the target/source CR field. Thus, post-ra anti-dep breaking must not later change that CR register assignment. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@257168 91177308-0d34-0410-b5e6-96231b3b80d8 Nemanja Ivanovic 4 years ago
2 changed file(s) with 30 addition(s) and 4 deletion(s). Raw diff Collapse all Expand all
298298 // 64-bit CR instructions
299299 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
300300 let hasSideEffects = 0 in {
301 // mtocrf's input needs to be prepared by shifting by an amount dependent
302 // on the cr register selected. Thus, post-ra anti-dep breaking must not
303 // later change that register assignment.
304 let hasExtraDefRegAllocReq = 1 in {
301305 def MTOCRF8: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins g8rc:$ST),
302306 "mtocrf $FXM, $ST", IIC_BrMCRX>,
303307 PPC970_DGroup_First, PPC970_Unit_CRU;
304308
309 // Similarly to mtocrf, the mask for mtcrf must be prepared in a way that
310 // is dependent on the cr fields being set.
305311 def MTCRF8 : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, g8rc:$rS),
306312 "mtcrf $FXM, $rS", IIC_BrMCRX>,
307313 PPC970_MicroCode, PPC970_Unit_CRU;
308
309 let hasExtraSrcRegAllocReq = 1 in // to enable post-ra anti-dep breaking.
314 } // hasExtraDefRegAllocReq = 1
315
316 // mfocrf's input needs to be prepared by shifting by an amount dependent
317 // on the cr register selected. Thus, post-ra anti-dep breaking must not
318 // later change that register assignment.
319 let hasExtraSrcRegAllocReq = 1 in {
310320 def MFOCRF8: XFXForm_5a<31, 19, (outs g8rc:$rT), (ins crbitm:$FXM),
311321 "mfocrf $rT, $FXM", IIC_SprMFCRF>,
312322 PPC970_DGroup_First, PPC970_Unit_CRU;
313323
324 // Similarly to mfocrf, the mask for mfcrf must be prepared in a way that
325 // is dependent on the cr fields being copied.
314326 def MFCR8 : XFXForm_3<31, 19, (outs g8rc:$rT), (ins),
315327 "mfcr $rT", IIC_SprMFCR>,
316328 PPC970_MicroCode, PPC970_Unit_CRU;
329 } // hasExtraSrcRegAllocReq = 1
317330 } // hasSideEffects = 0
318331
319332 let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
22982298 "#RESTORE_VRSAVE", []>;
22992299
23002300 let hasSideEffects = 0 in {
2301 // mtocrf's input needs to be prepared by shifting by an amount dependent
2302 // on the cr register selected. Thus, post-ra anti-dep breaking must not
2303 // later change that register assignment.
2304 let hasExtraDefRegAllocReq = 1 in {
23012305 def MTOCRF: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins gprc:$ST),
23022306 "mtocrf $FXM, $ST", IIC_BrMCRX>,
23032307 PPC970_DGroup_First, PPC970_Unit_CRU;
23042308
2309 // Similarly to mtocrf, the mask for mtcrf must be prepared in a way that
2310 // is dependent on the cr fields being set.
23052311 def MTCRF : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, gprc:$rS),
23062312 "mtcrf $FXM, $rS", IIC_BrMCRX>,
23072313 PPC970_MicroCode, PPC970_Unit_CRU;
2308
2309 let hasExtraSrcRegAllocReq = 1 in // to enable post-ra anti-dep breaking.
2314 } // hasExtraDefRegAllocReq = 1
2315
2316 // mfocrf's input needs to be prepared by shifting by an amount dependent
2317 // on the cr register selected. Thus, post-ra anti-dep breaking must not
2318 // later change that register assignment.
2319 let hasExtraSrcRegAllocReq = 1 in {
23102320 def MFOCRF: XFXForm_5a<31, 19, (outs gprc:$rT), (ins crbitm:$FXM),
23112321 "mfocrf $rT, $FXM", IIC_SprMFCRF>,
23122322 PPC970_DGroup_First, PPC970_Unit_CRU;
23132323
2324 // Similarly to mfocrf, the mask for mfcrf must be prepared in a way that
2325 // is dependent on the cr fields being copied.
23142326 def MFCR : XFXForm_3<31, 19, (outs gprc:$rT), (ins),
23152327 "mfcr $rT", IIC_SprMFCR>,
23162328 PPC970_MicroCode, PPC970_Unit_CRU;
2329 } // hasExtraSrcRegAllocReq = 1
23172330 } // hasSideEffects = 0
23182331
23192332 // Pseudo instruction to perform FADD in round-to-zero mode.