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Make ARMAsmPrinter generate the correct alignment specifier syntax in instructions. The Printer will now print instructions with the correct alignment specifier syntax, like vld1.8 {d16}, [r0:64] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175884 91177308-0d34-0410-b5e6-96231b3b80d8 Kristof Beyls 6 years ago
28 changed file(s) with 411 addition(s) and 412 deletion(s). Raw diff Collapse all Expand all
626626 O << markup("
627627 printRegName(O, MO1.getReg());
628628 if (MO2.getImm()) {
629 // FIXME: Both darwin as and GNU as violate ARM docs here.
630 O << ", :" << (MO2.getImm() << 3);
629 O << ":" << (MO2.getImm() << 3);
631630 }
632631 O << "]" << markup(">");
633632 }
77
88 ; CHECK: movw r1, :lower16:{{.*}}
99 ; CHECK: movt r1, :upper16:{{.*}}
10 ; CHECK: vld1.64 {{.*}}, [r1, :128]
10 ; CHECK: vld1.64 {{.*}}, [r1:128]
1111 ; CHECK: vsqrt.f32 {{s[0-9]+}}, {{s[0-9]+}}
1212 ; CHECK: vsqrt.f32 {{s[0-9]+}}, {{s[0-9]+}}
1313 ; CHECK: vsqrt.f32 {{s[0-9]+}}, {{s[0-9]+}}
251251
252252 ; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}}
253253 ; CHECK: movt [[reg0]], :upper16:{{.*}}
254 ; CHECK: vld1.64 {{.*}}, :128
254 ; CHECK: vld1.64 {{.*}}:128
255255 ; CHECK: vmul.f32 {{.*}}
256256
257257 ; CHECK: vst1.64
1717
1818 %i32val = sext <2 x i8> %i8val to <2 x i32>
1919 store <2 x i32> %i32val, <2 x i32>* @var_v2i32
20 ; CHECK: vld1.16 {d[[LOAD:[0-9]+]][0]}, [{{r[0-9]+}}, :16]
20 ; CHECK: vld1.16 {d[[LOAD:[0-9]+]][0]}, [{{r[0-9]+}}:16]
2121 ; CHECK: vmovl.s8 {{q[0-9]+}}, d[[LOAD]]
2222 ; CHECK: vmovl.s16 {{q[0-9]+}}, {{d[0-9]+}}
2323
3131
3232 %i64val = sext <2 x i8> %i8val to <2 x i64>
3333 store <2 x i64> %i64val, <2 x i64>* @var_v2i64
34 ; CHECK: vld1.16 {d{{[0-9]+}}[0]}, [{{r[0-9]+}}, :16]
34 ; CHECK: vld1.16 {d{{[0-9]+}}[0]}, [{{r[0-9]+}}:16]
3535 ; CHECK: vmovl.s8 {{q[0-9]+}}, d[[LOAD]]
3636 ; CHECK: vmovl.s16 {{q[0-9]+}}, {{d[0-9]+}}
3737 ; CHECK: vmovl.s32 {{q[0-9]+}}, {{d[0-9]+}}
4949
5050 %i16val = sext <4 x i8> %i8val to <4 x i16>
5151 store <4 x i16> %i16val, <4 x i16>* @var_v4i16
52 ; CHECK: vld1.32 {d[[LOAD:[0-9]+]][0]}, [{{r[0-9]+}}, :32]
52 ; CHECK: vld1.32 {d[[LOAD:[0-9]+]][0]}, [{{r[0-9]+}}:32]
5353 ; CHECK: vmovl.s8 {{q[0-9]+}}, d[[LOAD]]
5454 ; CHECK-NOT: vmovl.s16
5555
6464
6565 %i16val = sext <4 x i8> %i8val to <4 x i32>
6666 store <4 x i32> %i16val, <4 x i32>* @var_v4i32
67 ; CHECK: vld1.32 {d[[LOAD:[0-9]+]][0]}, [{{r[0-9]+}}, :32]
67 ; CHECK: vld1.32 {d[[LOAD:[0-9]+]][0]}, [{{r[0-9]+}}:32]
6868 ; CHECK: vmovl.s8 {{q[0-9]+}}, d[[LOAD]]
6969 ; CHECK: vmovl.s16 {{q[0-9]+}}, {{d[0-9]+}}
7070
7878
7979 %i32val = sext <2 x i16> %i16val to <2 x i32>
8080 store <2 x i32> %i32val, <2 x i32>* @var_v2i32
81 ; CHECK: vld1.32 {d[[LOAD:[0-9]+]][0]}, [{{r[0-9]+}}, :32]
81 ; CHECK: vld1.32 {d[[LOAD:[0-9]+]][0]}, [{{r[0-9]+}}:32]
8282 ; CHECK: vmovl.s16 {{q[0-9]+}}, d[[LOAD]]
8383 ; CHECK-NOT: vmovl
8484
9393
9494 %i64val = sext <2 x i16> %i16val to <2 x i64>
9595 store <2 x i64> %i64val, <2 x i64>* @var_v2i64
96 ; CHECK: vld1.32 {d[[LOAD:[0-9]+]][0]}, [{{r[0-9]+}}, :32]
96 ; CHECK: vld1.32 {d[[LOAD:[0-9]+]][0]}, [{{r[0-9]+}}:32]
9797 ; CHECK: vmovl.s16 {{q[0-9]+}}, d[[LOAD]]
9898 ; CHECK: vmovl.s32 {{q[0-9]+}}, d[[LOAD]]
9999
66 ; CHECK: vadd.i64 q
77 ; CHECK: vst1.64
88 ; SWIFT: t1
9 ; SWIFT: vld1.64 {{.d[0-9]+, d[0-9]+}, \[r[0-9]+, :128\]}}
10 ; SWIFT: vld1.64 {{.d[0-9]+, d[0-9]+}, \[r[0-9]+, :128\]}}
9 ; SWIFT: vld1.64 {{.d[0-9]+, d[0-9]+}, \[r[0-9]+:128\]}}
10 ; SWIFT: vld1.64 {{.d[0-9]+, d[0-9]+}, \[r[0-9]+:128\]}}
1111 ; SWIFT: vadd.i64 q
12 ; SWIFT: vst1.64 {{.d[0-9]+, d[0-9]+}, \[r[0-9]+, :128\]}}
12 ; SWIFT: vst1.64 {{.d[0-9]+, d[0-9]+}, \[r[0-9]+:128\]}}
1313 define void @t1(<4 x i32>* %r, <2 x i64>* %a, <2 x i64>* %b) nounwind {
1414 entry:
1515 %0 = load <2 x i64>* %a, align 16 ; <<2 x i64>> [#uses=1]
2727 ; CHECK: vmov r0, r1, d
2828 ; CHECK: vmov r2, r3, d
2929 ; SWIFT: t2
30 ; SWIFT: vld1.64 {{.d[0-9]+, d[0-9]+}, \[r[0-9]+, :128\]}}
31 ; SWIFT: vld1.64 {{.d[0-9]+, d[0-9]+}, \[r[0-9]+, :128\]}}
30 ; SWIFT: vld1.64 {{.d[0-9]+, d[0-9]+}, \[r[0-9]+:128\]}}
31 ; SWIFT: vld1.64 {{.d[0-9]+, d[0-9]+}, \[r[0-9]+:128\]}}
3232 ; SWIFT: vsub.i64 q
3333 ; SWIFT: vmov r0, r1, d
3434 ; SWIFT: vmov r2, r3, d
241241 ; CHECK: vldr
242242 ; CHECK-NOT: vmov d{{.*}}, d16
243243 ; CHECK: vmov.i32 d17
244 ; CHECK-NEXT: vst1.64 {d16, d17}, [r0, :128]
245 ; CHECK-NEXT: vst1.64 {d16, d17}, [r0, :128]
244 ; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]
245 ; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]
246246 %3 = bitcast double 0.000000e+00 to <2 x float> ; <<2 x float>> [#uses=2]
247247 %4 = shufflevector <2 x float> %3, <2 x float> undef, <4 x i32> ; <<4 x float>> [#uses=1]
248248 store <4 x float> %4, <4 x float>* undef, align 16
1111 define void @aaa(%quuz* %this, i8* %block) {
1212 ; CHECK: aaa:
1313 ; CHECK: bic {{.*}}, #15
14 ; CHECK: vst1.64 {{.*}}sp, :128
15 ; CHECK: vld1.64 {{.*}}sp, :128
14 ; CHECK: vst1.64 {{.*}}sp:128
15 ; CHECK: vld1.64 {{.*}}sp:128
1616 entry:
1717 %aligned_vec = alloca <4 x float>, align 16
1818 %"alloca point" = bitcast i32 0 to i32
33 define <8 x i8> @vld1i8(i8* %A) nounwind {
44 ;CHECK: vld1i8:
55 ;Check the alignment value. Max for this instruction is 64 bits:
6 ;CHECK: vld1.8 {d16}, [r0, :64]
6 ;CHECK: vld1.8 {d16}, [r0:64]
77 %tmp1 = call <8 x i8> @llvm.arm.neon.vld1.v8i8(i8* %A, i32 16)
88 ret <8 x i8> %tmp1
99 }
6767 define <16 x i8> @vld1Qi8(i8* %A) nounwind {
6868 ;CHECK: vld1Qi8:
6969 ;Check the alignment value. Max for this instruction is 128 bits:
70 ;CHECK: vld1.8 {d16, d17}, [r0, :64]
70 ;CHECK: vld1.8 {d16, d17}, [r0:64]
7171 %tmp1 = call <16 x i8> @llvm.arm.neon.vld1.v16i8(i8* %A, i32 8)
7272 ret <16 x i8> %tmp1
7373 }
7575 ;Check for a post-increment updating load.
7676 define <16 x i8> @vld1Qi8_update(i8** %ptr) nounwind {
7777 ;CHECK: vld1Qi8_update:
78 ;CHECK: vld1.8 {d16, d17}, [{{r[0-9]+}}, :64]!
78 ;CHECK: vld1.8 {d16, d17}, [{{r[0-9]+}}:64]!
7979 %A = load i8** %ptr
8080 %tmp1 = call <16 x i8> @llvm.arm.neon.vld1.v16i8(i8* %A, i32 8)
8181 %tmp2 = getelementptr i8* %A, i32 16
8686 define <8 x i16> @vld1Qi16(i16* %A) nounwind {
8787 ;CHECK: vld1Qi16:
8888 ;Check the alignment value. Max for this instruction is 128 bits:
89 ;CHECK: vld1.16 {d16, d17}, [r0, :128]
89 ;CHECK: vld1.16 {d16, d17}, [r0:128]
9090 %tmp0 = bitcast i16* %A to i8*
9191 %tmp1 = call <8 x i16> @llvm.arm.neon.vld1.v8i16(i8* %tmp0, i32 32)
9292 ret <8 x i16> %tmp1
1313 define <8 x i8> @vld2i8(i8* %A) nounwind {
1414 ;CHECK: vld2i8:
1515 ;Check the alignment value. Max for this instruction is 128 bits:
16 ;CHECK: vld2.8 {d16, d17}, [r0, :64]
16 ;CHECK: vld2.8 {d16, d17}, [r0:64]
1717 %tmp1 = call %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2.v8i8(i8* %A, i32 8)
1818 %tmp2 = extractvalue %struct.__neon_int8x8x2_t %tmp1, 0
1919 %tmp3 = extractvalue %struct.__neon_int8x8x2_t %tmp1, 1
2424 define <4 x i16> @vld2i16(i16* %A) nounwind {
2525 ;CHECK: vld2i16:
2626 ;Check the alignment value. Max for this instruction is 128 bits:
27 ;CHECK: vld2.16 {d16, d17}, [r0, :128]
27 ;CHECK: vld2.16 {d16, d17}, [r0:128]
2828 %tmp0 = bitcast i16* %A to i8*
2929 %tmp1 = call %struct.__neon_int16x4x2_t @llvm.arm.neon.vld2.v4i16(i8* %tmp0, i32 32)
3030 %tmp2 = extractvalue %struct.__neon_int16x4x2_t %tmp1, 0
7373 define <1 x i64> @vld2i64(i64* %A) nounwind {
7474 ;CHECK: vld2i64:
7575 ;Check the alignment value. Max for this instruction is 128 bits:
76 ;CHECK: vld1.64 {d16, d17}, [r0, :128]
76 ;CHECK: vld1.64 {d16, d17}, [r0:128]
7777 %tmp0 = bitcast i64* %A to i8*
7878 %tmp1 = call %struct.__neon_int64x1x2_t @llvm.arm.neon.vld2.v1i64(i8* %tmp0, i32 32)
7979 %tmp2 = extractvalue %struct.__neon_int64x1x2_t %tmp1, 0
8585 define <16 x i8> @vld2Qi8(i8* %A) nounwind {
8686 ;CHECK: vld2Qi8:
8787 ;Check the alignment value. Max for this instruction is 256 bits:
88 ;CHECK: vld2.8 {d16, d17, d18, d19}, [r0, :64]
88 ;CHECK: vld2.8 {d16, d17, d18, d19}, [r0:64]
8989 %tmp1 = call %struct.__neon_int8x16x2_t @llvm.arm.neon.vld2.v16i8(i8* %A, i32 8)
9090 %tmp2 = extractvalue %struct.__neon_int8x16x2_t %tmp1, 0
9191 %tmp3 = extractvalue %struct.__neon_int8x16x2_t %tmp1, 1
9696 ;Check for a post-increment updating load with register increment.
9797 define <16 x i8> @vld2Qi8_update(i8** %ptr, i32 %inc) nounwind {
9898 ;CHECK: vld2Qi8_update:
99 ;CHECK: vld2.8 {d16, d17, d18, d19}, [r2, :128], r1
99 ;CHECK: vld2.8 {d16, d17, d18, d19}, [r2:128], r1
100100 %A = load i8** %ptr
101101 %tmp1 = call %struct.__neon_int8x16x2_t @llvm.arm.neon.vld2.v16i8(i8* %A, i32 16)
102102 %tmp2 = extractvalue %struct.__neon_int8x16x2_t %tmp1, 0
110110 define <8 x i16> @vld2Qi16(i16* %A) nounwind {
111111 ;CHECK: vld2Qi16:
112112 ;Check the alignment value. Max for this instruction is 256 bits:
113 ;CHECK: vld2.16 {d16, d17, d18, d19}, [r0, :128]
113 ;CHECK: vld2.16 {d16, d17, d18, d19}, [r0:128]
114114 %tmp0 = bitcast i16* %A to i8*
115115 %tmp1 = call %struct.__neon_int16x8x2_t @llvm.arm.neon.vld2.v8i16(i8* %tmp0, i32 16)
116116 %tmp2 = extractvalue %struct.__neon_int16x8x2_t %tmp1, 0
122122 define <4 x i32> @vld2Qi32(i32* %A) nounwind {
123123 ;CHECK: vld2Qi32:
124124 ;Check the alignment value. Max for this instruction is 256 bits:
125 ;CHECK: vld2.32 {d16, d17, d18, d19}, [r0, :256]
125 ;CHECK: vld2.32 {d16, d17, d18, d19}, [r0:256]
126126 %tmp0 = bitcast i32* %A to i8*
127127 %tmp1 = call %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2.v4i32(i8* %tmp0, i32 64)
128128 %tmp2 = extractvalue %struct.__neon_int32x4x2_t %tmp1, 0
1414 define <8 x i8> @vld3i8(i8* %A) nounwind {
1515 ;CHECK: vld3i8:
1616 ;Check the alignment value. Max for this instruction is 64 bits:
17 ;CHECK: vld3.8 {d16, d17, d18}, [r0, :64]
17 ;CHECK: vld3.8 {d16, d17, d18}, [r0:64]
1818 %tmp1 = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8(i8* %A, i32 32)
1919 %tmp2 = extractvalue %struct.__neon_int8x8x3_t %tmp1, 0
2020 %tmp3 = extractvalue %struct.__neon_int8x8x3_t %tmp1, 2
7373 define <1 x i64> @vld3i64(i64* %A) nounwind {
7474 ;CHECK: vld3i64:
7575 ;Check the alignment value. Max for this instruction is 64 bits:
76 ;CHECK: vld1.64 {d16, d17, d18}, [r0, :64]
76 ;CHECK: vld1.64 {d16, d17, d18}, [r0:64]
7777 %tmp0 = bitcast i64* %A to i8*
7878 %tmp1 = call %struct.__neon_int64x1x3_t @llvm.arm.neon.vld3.v1i64(i8* %tmp0, i32 16)
7979 %tmp2 = extractvalue %struct.__neon_int64x1x3_t %tmp1, 0
8585 define <16 x i8> @vld3Qi8(i8* %A) nounwind {
8686 ;CHECK: vld3Qi8:
8787 ;Check the alignment value. Max for this instruction is 64 bits:
88 ;CHECK: vld3.8 {d16, d18, d20}, [r0, :64]!
89 ;CHECK: vld3.8 {d17, d19, d21}, [r0, :64]
88 ;CHECK: vld3.8 {d16, d18, d20}, [r0:64]!
89 ;CHECK: vld3.8 {d17, d19, d21}, [r0:64]
9090 %tmp1 = call %struct.__neon_int8x16x3_t @llvm.arm.neon.vld3.v16i8(i8* %A, i32 32)
9191 %tmp2 = extractvalue %struct.__neon_int8x16x3_t %tmp1, 0
9292 %tmp3 = extractvalue %struct.__neon_int8x16x3_t %tmp1, 2
1313 define <8 x i8> @vld4i8(i8* %A) nounwind {
1414 ;CHECK: vld4i8:
1515 ;Check the alignment value. Max for this instruction is 256 bits:
16 ;CHECK: vld4.8 {d16, d17, d18, d19}, [r0, :64]
16 ;CHECK: vld4.8 {d16, d17, d18, d19}, [r0:64]
1717 %tmp1 = call %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4.v8i8(i8* %A, i32 8)
1818 %tmp2 = extractvalue %struct.__neon_int8x8x4_t %tmp1, 0
1919 %tmp3 = extractvalue %struct.__neon_int8x8x4_t %tmp1, 2
2424 ;Check for a post-increment updating load with register increment.
2525 define <8 x i8> @vld4i8_update(i8** %ptr, i32 %inc) nounwind {
2626 ;CHECK: vld4i8_update:
27 ;CHECK: vld4.8 {d16, d17, d18, d19}, [r2, :128], r1
27 ;CHECK: vld4.8 {d16, d17, d18, d19}, [r2:128], r1
2828 %A = load i8** %ptr
2929 %tmp1 = call %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4.v8i8(i8* %A, i32 16)
3030 %tmp2 = extractvalue %struct.__neon_int8x8x4_t %tmp1, 0
3838 define <4 x i16> @vld4i16(i16* %A) nounwind {
3939 ;CHECK: vld4i16:
4040 ;Check the alignment value. Max for this instruction is 256 bits:
41 ;CHECK: vld4.16 {d16, d17, d18, d19}, [r0, :128]
41 ;CHECK: vld4.16 {d16, d17, d18, d19}, [r0:128]
4242 %tmp0 = bitcast i16* %A to i8*
4343 %tmp1 = call %struct.__neon_int16x4x4_t @llvm.arm.neon.vld4.v4i16(i8* %tmp0, i32 16)
4444 %tmp2 = extractvalue %struct.__neon_int16x4x4_t %tmp1, 0
5050 define <2 x i32> @vld4i32(i32* %A) nounwind {
5151 ;CHECK: vld4i32:
5252 ;Check the alignment value. Max for this instruction is 256 bits:
53 ;CHECK: vld4.32 {d16, d17, d18, d19}, [r0, :256]
53 ;CHECK: vld4.32 {d16, d17, d18, d19}, [r0:256]
5454 %tmp0 = bitcast i32* %A to i8*
5555 %tmp1 = call %struct.__neon_int32x2x4_t @llvm.arm.neon.vld4.v2i32(i8* %tmp0, i32 32)
5656 %tmp2 = extractvalue %struct.__neon_int32x2x4_t %tmp1, 0
7373 define <1 x i64> @vld4i64(i64* %A) nounwind {
7474 ;CHECK: vld4i64:
7575 ;Check the alignment value. Max for this instruction is 256 bits:
76 ;CHECK: vld1.64 {d16, d17, d18, d19}, [r0, :256]
76 ;CHECK: vld1.64 {d16, d17, d18, d19}, [r0:256]
7777 %tmp0 = bitcast i64* %A to i8*
7878 %tmp1 = call %struct.__neon_int64x1x4_t @llvm.arm.neon.vld4.v1i64(i8* %tmp0, i32 64)
7979 %tmp2 = extractvalue %struct.__neon_int64x1x4_t %tmp1, 0
8585 define <16 x i8> @vld4Qi8(i8* %A) nounwind {
8686 ;CHECK: vld4Qi8:
8787 ;Check the alignment value. Max for this instruction is 256 bits:
88 ;CHECK: vld4.8 {d16, d18, d20, d22}, [r0, :256]!
89 ;CHECK: vld4.8 {d17, d19, d21, d23}, [r0, :256]
88 ;CHECK: vld4.8 {d16, d18, d20, d22}, [r0:256]!
89 ;CHECK: vld4.8 {d17, d19, d21, d23}, [r0:256]
9090 %tmp1 = call %struct.__neon_int8x16x4_t @llvm.arm.neon.vld4.v16i8(i8* %A, i32 64)
9191 %tmp2 = extractvalue %struct.__neon_int8x16x4_t %tmp1, 0
9292 %tmp3 = extractvalue %struct.__neon_int8x16x4_t %tmp1, 2
110110 ;Check for a post-increment updating load.
111111 define <8 x i16> @vld4Qi16_update(i16** %ptr) nounwind {
112112 ;CHECK: vld4Qi16_update:
113 ;CHECK: vld4.16 {d16, d18, d20, d22}, [r1, :64]!
114 ;CHECK: vld4.16 {d17, d19, d21, d23}, [r1, :64]!
113 ;CHECK: vld4.16 {d16, d18, d20, d22}, [r1:64]!
114 ;CHECK: vld4.16 {d17, d19, d21, d23}, [r1:64]!
115115 %A = load i16** %ptr
116116 %tmp0 = bitcast i16* %A to i8*
117117 %tmp1 = call %struct.__neon_int16x8x4_t @llvm.arm.neon.vld4.v8i16(i8* %tmp0, i32 8)
1212 define <4 x i16> @vld1dupi16(i16* %A) nounwind {
1313 ;CHECK: vld1dupi16:
1414 ;Check the alignment value. Max for this instruction is 16 bits:
15 ;CHECK: vld1.16 {d16[]}, [r0, :16]
15 ;CHECK: vld1.16 {d16[]}, [r0:16]
1616 %tmp1 = load i16* %A, align 8
1717 %tmp2 = insertelement <4 x i16> undef, i16 %tmp1, i32 0
1818 %tmp3 = shufflevector <4 x i16> %tmp2, <4 x i16> undef, <4 x i32> zeroinitializer
2222 define <2 x i32> @vld1dupi32(i32* %A) nounwind {
2323 ;CHECK: vld1dupi32:
2424 ;Check the alignment value. Max for this instruction is 32 bits:
25 ;CHECK: vld1.32 {d16[]}, [r0, :32]
25 ;CHECK: vld1.32 {d16[]}, [r0:32]
2626 %tmp1 = load i32* %A, align 8
2727 %tmp2 = insertelement <2 x i32> undef, i32 %tmp1, i32 0
2828 %tmp3 = shufflevector <2 x i32> %tmp2, <2 x i32> undef, <2 x i32> zeroinitializer
3131
3232 define <2 x float> @vld1dupf(float* %A) nounwind {
3333 ;CHECK: vld1dupf:
34 ;CHECK: vld1.32 {d16[]}, [r0, :32]
34 ;CHECK: vld1.32 {d16[]}, [r0:32]
3535 %tmp0 = load float* %A
3636 %tmp1 = insertelement <2 x float> undef, float %tmp0, i32 0
3737 %tmp2 = shufflevector <2 x float> %tmp1, <2 x float> undef, <2 x i32> zeroinitializer
5050
5151 define <4 x float> @vld1dupQf(float* %A) nounwind {
5252 ;CHECK: vld1dupQf:
53 ;CHECK: vld1.32 {d16[], d17[]}, [r0, :32]
53 ;CHECK: vld1.32 {d16[], d17[]}, [r0:32]
5454 %tmp0 = load float* %A
5555 %tmp1 = insertelement <4 x float> undef, float %tmp0, i32 0
5656 %tmp2 = shufflevector <4 x float> %tmp1, <4 x float> undef, <4 x i32> zeroinitializer
108108 define <2 x i32> @vld2dupi32(i8* %A) nounwind {
109109 ;CHECK: vld2dupi32:
110110 ;Check the alignment value. Max for this instruction is 64 bits:
111 ;CHECK: vld2.32 {d16[], d17[]}, [r0, :64]
111 ;CHECK: vld2.32 {d16[], d17[]}, [r0:64]
112112 %tmp0 = tail call %struct.__neon_int2x32x2_t @llvm.arm.neon.vld2lane.v2i32(i8* %A, <2 x i32> undef, <2 x i32> undef, i32 0, i32 16)
113113 %tmp1 = extractvalue %struct.__neon_int2x32x2_t %tmp0, 0
114114 %tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <2 x i32> zeroinitializer
193193 ;CHECK: vld4dupi32:
194194 ;Check the alignment value. An 8-byte alignment is allowed here even though
195195 ;it is smaller than the total size of the memory being loaded.
196 ;CHECK: vld4.32 {d16[], d17[], d18[], d19[]}, [r0, :64]
196 ;CHECK: vld4.32 {d16[], d17[], d18[], d19[]}, [r0:64]
197197 %tmp0 = tail call %struct.__neon_int32x2x4_t @llvm.arm.neon.vld4lane.v2i32(i8* %A, <2 x i32> undef, <2 x i32> undef, <2 x i32> undef, <2 x i32> undef, i32 0, i32 8)
198198 %tmp1 = extractvalue %struct.__neon_int32x2x4_t %tmp0, 0
199199 %tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <2 x i32> zeroinitializer
1313 define <4 x i16> @vld1lanei16(i16* %A, <4 x i16>* %B) nounwind {
1414 ;CHECK: vld1lanei16:
1515 ;Check the alignment value. Max for this instruction is 16 bits:
16 ;CHECK: vld1.16 {d16[2]}, [r0, :16]
16 ;CHECK: vld1.16 {d16[2]}, [r0:16]
1717 %tmp1 = load <4 x i16>* %B
1818 %tmp2 = load i16* %A, align 8
1919 %tmp3 = insertelement <4 x i16> %tmp1, i16 %tmp2, i32 2
2323 define <2 x i32> @vld1lanei32(i32* %A, <2 x i32>* %B) nounwind {
2424 ;CHECK: vld1lanei32:
2525 ;Check the alignment value. Max for this instruction is 32 bits:
26 ;CHECK: vld1.32 {d16[1]}, [r0, :32]
26 ;CHECK: vld1.32 {d16[1]}, [r0:32]
2727 %tmp1 = load <2 x i32>* %B
2828 %tmp2 = load i32* %A, align 8
2929 %tmp3 = insertelement <2 x i32> %tmp1, i32 %tmp2, i32 1
3333 define <2 x i32> @vld1lanei32a32(i32* %A, <2 x i32>* %B) nounwind {
3434 ;CHECK: vld1lanei32a32:
3535 ;Check the alignment value. Legal values are none or :32.
36 ;CHECK: vld1.32 {d16[1]}, [r0, :32]
36 ;CHECK: vld1.32 {d16[1]}, [r0:32]
3737 %tmp1 = load <2 x i32>* %B
3838 %tmp2 = load i32* %A, align 4
3939 %tmp3 = insertelement <2 x i32> %tmp1, i32 %tmp2, i32 1
4242
4343 define <2 x float> @vld1lanef(float* %A, <2 x float>* %B) nounwind {
4444 ;CHECK: vld1lanef:
45 ;CHECK: vld1.32 {d16[1]}, [r0, :32]
45 ;CHECK: vld1.32 {d16[1]}, [r0:32]
4646 %tmp1 = load <2 x float>* %B
4747 %tmp2 = load float* %A, align 4
4848 %tmp3 = insertelement <2 x float> %tmp1, float %tmp2, i32 1
6060
6161 define <8 x i16> @vld1laneQi16(i16* %A, <8 x i16>* %B) nounwind {
6262 ;CHECK: vld1laneQi16:
63 ;CHECK: vld1.16 {d17[1]}, [r0, :16]
63 ;CHECK: vld1.16 {d17[1]}, [r0:16]
6464 %tmp1 = load <8 x i16>* %B
6565 %tmp2 = load i16* %A, align 8
6666 %tmp3 = insertelement <8 x i16> %tmp1, i16 %tmp2, i32 5
6969
7070 define <4 x i32> @vld1laneQi32(i32* %A, <4 x i32>* %B) nounwind {
7171 ;CHECK: vld1laneQi32:
72 ;CHECK: vld1.32 {d17[1]}, [r0, :32]
72 ;CHECK: vld1.32 {d17[1]}, [r0:32]
7373 %tmp1 = load <4 x i32>* %B
7474 %tmp2 = load i32* %A, align 8
7575 %tmp3 = insertelement <4 x i32> %tmp1, i32 %tmp2, i32 3
7878
7979 define <4 x float> @vld1laneQf(float* %A, <4 x float>* %B) nounwind {
8080 ;CHECK: vld1laneQf:
81 ;CHECK: vld1.32 {d16[0]}, [r0, :32]
81 ;CHECK: vld1.32 {d16[0]}, [r0:32]
8282 %tmp1 = load <4 x float>* %B
8383 %tmp2 = load float* %A
8484 %tmp3 = insertelement <4 x float> %tmp1, float %tmp2, i32 0
9797 define <8 x i8> @vld2lanei8(i8* %A, <8 x i8>* %B) nounwind {
9898 ;CHECK: vld2lanei8:
9999 ;Check the alignment value. Max for this instruction is 16 bits:
100 ;CHECK: vld2.8 {d16[1], d17[1]}, [r0, :16]
100 ;CHECK: vld2.8 {d16[1], d17[1]}, [r0:16]
101101 %tmp1 = load <8 x i8>* %B
102102 %tmp2 = call %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 4)
103103 %tmp3 = extractvalue %struct.__neon_int8x8x2_t %tmp2, 0
109109 define <4 x i16> @vld2lanei16(i16* %A, <4 x i16>* %B) nounwind {
110110 ;CHECK: vld2lanei16:
111111 ;Check the alignment value. Max for this instruction is 32 bits:
112 ;CHECK: vld2.16 {d16[1], d17[1]}, [r0, :32]
112 ;CHECK: vld2.16 {d16[1], d17[1]}, [r0:32]
113113 %tmp0 = bitcast i16* %A to i8*
114114 %tmp1 = load <4 x i16>* %B
115115 %tmp2 = call %struct.__neon_int16x4x2_t @llvm.arm.neon.vld2lane.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1, i32 8)
175175 define <4 x i32> @vld2laneQi32(i32* %A, <4 x i32>* %B) nounwind {
176176 ;CHECK: vld2laneQi32:
177177 ;Check the alignment value. Max for this instruction is 64 bits:
178 ;CHECK: vld2.32 {d17[0], d19[0]}, [{{r[0-9]+}}, :64]
178 ;CHECK: vld2.32 {d17[0], d19[0]}, [{{r[0-9]+}}:64]
179179 %tmp0 = bitcast i32* %A to i8*
180180 %tmp1 = load <4 x i32>* %B
181181 %tmp2 = call %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2lane.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 2, i32 16)
353353 define <8 x i8> @vld4lanei8(i8* %A, <8 x i8>* %B) nounwind {
354354 ;CHECK: vld4lanei8:
355355 ;Check the alignment value. Max for this instruction is 32 bits:
356 ;CHECK: vld4.8 {d{{.*}}[1], d{{.*}}[1], d{{.*}}[1], d{{.*}}[1]}, [{{r[0-9]+}}, :32]
356 ;CHECK: vld4.8 {d{{.*}}[1], d{{.*}}[1], d{{.*}}[1], d{{.*}}[1]}, [{{r[0-9]+}}:32]
357357 %tmp1 = load <8 x i8>* %B
358358 %tmp2 = call %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 8)
359359 %tmp3 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 0
369369 ;Check for a post-increment updating load.
370370 define <8 x i8> @vld4lanei8_update(i8** %ptr, <8 x i8>* %B) nounwind {
371371 ;CHECK: vld4lanei8_update:
372 ;CHECK: vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [{{r[0-9]+}}, :32]!
372 ;CHECK: vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [{{r[0-9]+}}:32]!
373373 %A = load i8** %ptr
374374 %tmp1 = load <8 x i8>* %B
375375 %tmp2 = call %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 8)
407407 ;CHECK: vld4lanei32:
408408 ;Check the alignment value. An 8-byte alignment is allowed here even though
409409 ;it is smaller than the total size of the memory being loaded.
410 ;CHECK: vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [{{r[0-9]+}}, :64]
410 ;CHECK: vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [{{r[0-9]+}}:64]
411411 %tmp0 = bitcast i32* %A to i8*
412412 %tmp1 = load <2 x i32>* %B
413413 %tmp2 = call %struct.__neon_int32x2x4_t @llvm.arm.neon.vld4lane.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1, i32 8)
440440 define <8 x i16> @vld4laneQi16(i16* %A, <8 x i16>* %B) nounwind {
441441 ;CHECK: vld4laneQi16:
442442 ;Check the alignment value. Max for this instruction is 64 bits:
443 ;CHECK: vld4.16 {d16[1], d18[1], d20[1], d22[1]}, [{{r[0-9]+}}, :64]
443 ;CHECK: vld4.16 {d16[1], d18[1], d20[1], d22[1]}, [{{r[0-9]+}}:64]
444444 %tmp0 = bitcast i16* %A to i8*
445445 %tmp1 = load <8 x i16>* %B
446446 %tmp2 = call %struct.__neon_int16x8x4_t @llvm.arm.neon.vld4lane.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1, i32 16)
22 define void @vst1i8(i8* %A, <8 x i8>* %B) nounwind {
33 ;CHECK: vst1i8:
44 ;Check the alignment value. Max for this instruction is 64 bits:
5 ;CHECK: vst1.8 {d16}, [r0, :64]
5 ;CHECK: vst1.8 {d16}, [r0:64]
66 %tmp1 = load <8 x i8>* %B
77 call void @llvm.arm.neon.vst1.v8i8(i8* %A, <8 x i8> %tmp1, i32 16)
88 ret void
6060 define void @vst1Qi8(i8* %A, <16 x i8>* %B) nounwind {
6161 ;CHECK: vst1Qi8:
6262 ;Check the alignment value. Max for this instruction is 128 bits:
63 ;CHECK: vst1.8 {d16, d17}, [r0, :64]
63 ;CHECK: vst1.8 {d16, d17}, [r0:64]
6464 %tmp1 = load <16 x i8>* %B
6565 call void @llvm.arm.neon.vst1.v16i8(i8* %A, <16 x i8> %tmp1, i32 8)
6666 ret void
6969 define void @vst1Qi16(i16* %A, <8 x i16>* %B) nounwind {
7070 ;CHECK: vst1Qi16:
7171 ;Check the alignment value. Max for this instruction is 128 bits:
72 ;CHECK: vst1.16 {d16, d17}, [r0, :128]
72 ;CHECK: vst1.16 {d16, d17}, [r0:128]
7373 %tmp0 = bitcast i16* %A to i8*
7474 %tmp1 = load <8 x i16>* %B
7575 call void @llvm.arm.neon.vst1.v8i16(i8* %tmp0, <8 x i16> %tmp1, i32 32)
7979 ;Check for a post-increment updating store with register increment.
8080 define void @vst1Qi16_update(i16** %ptr, <8 x i16>* %B, i32 %inc) nounwind {
8181 ;CHECK: vst1Qi16_update:
82 ;CHECK: vst1.16 {d16, d17}, [r1, :64], r2
82 ;CHECK: vst1.16 {d16, d17}, [r1:64], r2
8383 %A = load i16** %ptr
8484 %tmp0 = bitcast i16* %A to i8*
8585 %tmp1 = load <8 x i16>* %B
22 define void @vst2i8(i8* %A, <8 x i8>* %B) nounwind {
33 ;CHECK: vst2i8:
44 ;Check the alignment value. Max for this instruction is 128 bits:
5 ;CHECK: vst2.8 {d16, d17}, [r0, :64]
5 ;CHECK: vst2.8 {d16, d17}, [r0:64]
66 %tmp1 = load <8 x i8>* %B
77 call void @llvm.arm.neon.vst2.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 8)
88 ret void
2323 define void @vst2i16(i16* %A, <4 x i16>* %B) nounwind {
2424 ;CHECK: vst2i16:
2525 ;Check the alignment value. Max for this instruction is 128 bits:
26 ;CHECK: vst2.16 {d16, d17}, [r0, :128]
26 ;CHECK: vst2.16 {d16, d17}, [r0:128]
2727 %tmp0 = bitcast i16* %A to i8*
2828 %tmp1 = load <4 x i16>* %B
2929 call void @llvm.arm.neon.vst2.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 32)
5151 define void @vst2i64(i64* %A, <1 x i64>* %B) nounwind {
5252 ;CHECK: vst2i64:
5353 ;Check the alignment value. Max for this instruction is 128 bits:
54 ;CHECK: vst1.64 {d16, d17}, [r0, :128]
54 ;CHECK: vst1.64 {d16, d17}, [r0:128]
5555 %tmp0 = bitcast i64* %A to i8*
5656 %tmp1 = load <1 x i64>* %B
5757 call void @llvm.arm.neon.vst2.v1i64(i8* %tmp0, <1 x i64> %tmp1, <1 x i64> %tmp1, i32 32)
6161 ;Check for a post-increment updating store.
6262 define void @vst2i64_update(i64** %ptr, <1 x i64>* %B) nounwind {
6363 ;CHECK: vst2i64_update:
64 ;CHECK: vst1.64 {d16, d17}, [r1, :64]!
64 ;CHECK: vst1.64 {d16, d17}, [r1:64]!
6565 %A = load i64** %ptr
6666 %tmp0 = bitcast i64* %A to i8*
6767 %tmp1 = load <1 x i64>* %B
7474 define void @vst2Qi8(i8* %A, <16 x i8>* %B) nounwind {
7575 ;CHECK: vst2Qi8:
7676 ;Check the alignment value. Max for this instruction is 256 bits:
77 ;CHECK: vst2.8 {d16, d17, d18, d19}, [r0, :64]
77 ;CHECK: vst2.8 {d16, d17, d18, d19}, [r0:64]
7878 %tmp1 = load <16 x i8>* %B
7979 call void @llvm.arm.neon.vst2.v16i8(i8* %A, <16 x i8> %tmp1, <16 x i8> %tmp1, i32 8)
8080 ret void
8383 define void @vst2Qi16(i16* %A, <8 x i16>* %B) nounwind {
8484 ;CHECK: vst2Qi16:
8585 ;Check the alignment value. Max for this instruction is 256 bits:
86 ;CHECK: vst2.16 {d16, d17, d18, d19}, [r0, :128]
86 ;CHECK: vst2.16 {d16, d17, d18, d19}, [r0:128]
8787 %tmp0 = bitcast i16* %A to i8*
8888 %tmp1 = load <8 x i16>* %B
8989 call void @llvm.arm.neon.vst2.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 16)
9393 define void @vst2Qi32(i32* %A, <4 x i32>* %B) nounwind {
9494 ;CHECK: vst2Qi32:
9595 ;Check the alignment value. Max for this instruction is 256 bits:
96 ;CHECK: vst2.32 {d16, d17, d18, d19}, [r0, :256]
96 ;CHECK: vst2.32 {d16, d17, d18, d19}, [r0:256]
9797 %tmp0 = bitcast i32* %A to i8*
9898 %tmp1 = load <4 x i32>* %B
9999 call void @llvm.arm.neon.vst2.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 64)
33 ;CHECK: vst3i8:
44 ;Check the alignment value. Max for this instruction is 64 bits:
55 ;This test runs at -O0 so do not check for specific register numbers.
6 ;CHECK: vst3.8 {d{{.*}}, d{{.*}}, d{{.*}}}, [r{{.*}}, :64]
6 ;CHECK: vst3.8 {d{{.*}}, d{{.*}}, d{{.*}}}, [r{{.*}}:64]
77 %tmp1 = load <8 x i8>* %B
88 call void @llvm.arm.neon.vst3.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 32)
99 ret void
5353 ;CHECK: vst3i64:
5454 ;Check the alignment value. Max for this instruction is 64 bits:
5555 ;This test runs at -O0 so do not check for specific register numbers.
56 ;CHECK: vst1.64 {d{{.*}}, d{{.*}}, d{{.*}}}, [r{{.*}}, :64]
56 ;CHECK: vst1.64 {d{{.*}}, d{{.*}}, d{{.*}}}, [r{{.*}}:64]
5757 %tmp0 = bitcast i64* %A to i8*
5858 %tmp1 = load <1 x i64>* %B
5959 call void @llvm.arm.neon.vst3.v1i64(i8* %tmp0, <1 x i64> %tmp1, <1 x i64> %tmp1, <1 x i64> %tmp1, i32 16)
6464 ;CHECK: vst3Qi8:
6565 ;Check the alignment value. Max for this instruction is 64 bits:
6666 ;This test runs at -O0 so do not check for specific register numbers.
67 ;CHECK: vst3.8 {d{{.*}}, d{{.*}}, d{{.*}}}, [r{{.*}}, :64]!
68 ;CHECK: vst3.8 {d{{.*}}, d{{.*}}, d{{.*}}}, [r{{.*}}, :64]
67 ;CHECK: vst3.8 {d{{.*}}, d{{.*}}, d{{.*}}}, [r{{.*}}:64]!
68 ;CHECK: vst3.8 {d{{.*}}, d{{.*}}, d{{.*}}}, [r{{.*}}:64]
6969 %tmp1 = load <16 x i8>* %B
7070 call void @llvm.arm.neon.vst3.v16i8(i8* %A, <16 x i8> %tmp1, <16 x i8> %tmp1, <16 x i8> %tmp1, i32 32)
7171 ret void
22 define void @vst4i8(i8* %A, <8 x i8>* %B) nounwind {
33 ;CHECK: vst4i8:
44 ;Check the alignment value. Max for this instruction is 256 bits:
5 ;CHECK: vst4.8 {d16, d17, d18, d19}, [r0, :64]
5 ;CHECK: vst4.8 {d16, d17, d18, d19}, [r0:64]
66 %tmp1 = load <8 x i8>* %B
77 call void @llvm.arm.neon.vst4.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 8)
88 ret void
1111 ;Check for a post-increment updating store with register increment.
1212 define void @vst4i8_update(i8** %ptr, <8 x i8>* %B, i32 %inc) nounwind {
1313 ;CHECK: vst4i8_update:
14 ;CHECK: vst4.8 {d16, d17, d18, d19}, [r1, :128], r2
14 ;CHECK: vst4.8 {d16, d17, d18, d19}, [r1:128], r2
1515 %A = load i8** %ptr
1616 %tmp1 = load <8 x i8>* %B
1717 call void @llvm.arm.neon.vst4.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 16)
2323 define void @vst4i16(i16* %A, <4 x i16>* %B) nounwind {
2424 ;CHECK: vst4i16:
2525 ;Check the alignment value. Max for this instruction is 256 bits:
26 ;CHECK: vst4.16 {d16, d17, d18, d19}, [r0, :128]
26 ;CHECK: vst4.16 {d16, d17, d18, d19}, [r0:128]
2727 %tmp0 = bitcast i16* %A to i8*
2828 %tmp1 = load <4 x i16>* %B
2929 call void @llvm.arm.neon.vst4.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 16)
3333 define void @vst4i32(i32* %A, <2 x i32>* %B) nounwind {
3434 ;CHECK: vst4i32:
3535 ;Check the alignment value. Max for this instruction is 256 bits:
36 ;CHECK: vst4.32 {d16, d17, d18, d19}, [r0, :256]
36 ;CHECK: vst4.32 {d16, d17, d18, d19}, [r0:256]
3737 %tmp0 = bitcast i32* %A to i8*
3838 %tmp1 = load <2 x i32>* %B
3939 call void @llvm.arm.neon.vst4.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 32)
5252 define void @vst4i64(i64* %A, <1 x i64>* %B) nounwind {
5353 ;CHECK: vst4i64:
5454 ;Check the alignment value. Max for this instruction is 256 bits:
55 ;CHECK: vst1.64 {d16, d17, d18, d19}, [r0, :256]
55 ;CHECK: vst1.64 {d16, d17, d18, d19}, [r0:256]
5656 %tmp0 = bitcast i64* %A to i8*
5757 %tmp1 = load <1 x i64>* %B
5858 call void @llvm.arm.neon.vst4.v1i64(i8* %tmp0, <1 x i64> %tmp1, <1 x i64> %tmp1, <1 x i64> %tmp1, <1 x i64> %tmp1, i32 64)
6262 define void @vst4Qi8(i8* %A, <16 x i8>* %B) nounwind {
6363 ;CHECK: vst4Qi8:
6464 ;Check the alignment value. Max for this instruction is 256 bits:
65 ;CHECK: vst4.8 {d16, d18, d20, d22}, [r0, :256]!
66 ;CHECK: vst4.8 {d17, d19, d21, d23}, [r0, :256]
65 ;CHECK: vst4.8 {d16, d18, d20, d22}, [r0:256]!
66 ;CHECK: vst4.8 {d17, d19, d21, d23}, [r0:256]
6767 %tmp1 = load <16 x i8>* %B
6868 call void @llvm.arm.neon.vst4.v16i8(i8* %A, <16 x i8> %tmp1, <16 x i8> %tmp1, <16 x i8> %tmp1, <16 x i8> %tmp1, i32 64)
6969 ret void
2525 define void @vst1lanei16(i16* %A, <4 x i16>* %B) nounwind {
2626 ;CHECK: vst1lanei16:
2727 ;Check the alignment value. Max for this instruction is 16 bits:
28 ;CHECK: vst1.16 {d16[2]}, [r0, :16]
28 ;CHECK: vst1.16 {d16[2]}, [r0:16]
2929 %tmp1 = load <4 x i16>* %B
3030 %tmp2 = extractelement <4 x i16> %tmp1, i32 2
3131 store i16 %tmp2, i16* %A, align 8
3535 define void @vst1lanei32(i32* %A, <2 x i32>* %B) nounwind {
3636 ;CHECK: vst1lanei32:
3737 ;Check the alignment value. Max for this instruction is 32 bits:
38 ;CHECK: vst1.32 {d16[1]}, [r0, :32]
38 ;CHECK: vst1.32 {d16[1]}, [r0:32]
3939 %tmp1 = load <2 x i32>* %B
4040 %tmp2 = extractelement <2 x i32> %tmp1, i32 1
4141 store i32 %tmp2, i32* %A, align 8
4444
4545 define void @vst1lanef(float* %A, <2 x float>* %B) nounwind {
4646 ;CHECK: vst1lanef:
47 ;CHECK: vst1.32 {d16[1]}, [r0, :32]
47 ;CHECK: vst1.32 {d16[1]}, [r0:32]
4848 %tmp1 = load <2 x float>* %B
4949 %tmp2 = extractelement <2 x float> %tmp1, i32 1
5050 store float %tmp2, float* %A
6363
6464 define void @vst1laneQi16(i16* %A, <8 x i16>* %B) nounwind {
6565 ;CHECK: vst1laneQi16:
66 ;CHECK: vst1.16 {d17[1]}, [r0, :16]
66 ;CHECK: vst1.16 {d17[1]}, [r0:16]
6767 %tmp1 = load <8 x i16>* %B
6868 %tmp2 = extractelement <8 x i16> %tmp1, i32 5
6969 store i16 %tmp2, i16* %A, align 8
7373 define void @vst1laneQi32(i32* %A, <4 x i32>* %B) nounwind {
7474 ;CHECK: vst1laneQi32:
7575 ; // Can use scalar load. No need to use vectors.
76 ; // CHE-CK: vst1.32 {d17[1]}, [r0, :32]
76 ; // CHE-CK: vst1.32 {d17[1]}, [r0:32]
7777 %tmp1 = load <4 x i32>* %B
7878 %tmp2 = extractelement <4 x i32> %tmp1, i32 3
7979 store i32 %tmp2, i32* %A, align 8
8484 define void @vst1laneQi32_update(i32** %ptr, <4 x i32>* %B) nounwind {
8585 ;CHECK: vst1laneQi32_update:
8686 ; // Can use scalar load. No need to use vectors.
87 ; // CHE-CK: vst1.32 {d17[1]}, [r1, :32]!
87 ; // CHE-CK: vst1.32 {d17[1]}, [r1:32]!
8888 %A = load i32** %ptr
8989 %tmp1 = load <4 x i32>* %B
9090 %tmp2 = extractelement <4 x i32> %tmp1, i32 3
107107 define void @vst2lanei8(i8* %A, <8 x i8>* %B) nounwind {
108108 ;CHECK: vst2lanei8:
109109 ;Check the alignment value. Max for this instruction is 16 bits:
110 ;CHECK: vst2.8 {d16[1], d17[1]}, [r0, :16]
110 ;CHECK: vst2.8 {d16[1], d17[1]}, [r0:16]
111111 %tmp1 = load <8 x i8>* %B
112112 call void @llvm.arm.neon.vst2lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 4)
113113 ret void
116116 define void @vst2lanei16(i16* %A, <4 x i16>* %B) nounwind {
117117 ;CHECK: vst2lanei16:
118118 ;Check the alignment value. Max for this instruction is 32 bits:
119 ;CHECK: vst2.16 {d16[1], d17[1]}, [r0, :32]
119 ;CHECK: vst2.16 {d16[1], d17[1]}, [r0:32]
120120 %tmp0 = bitcast i16* %A to i8*
121121 %tmp1 = load <4 x i16>* %B
122122 call void @llvm.arm.neon.vst2lane.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1, i32 8)
167167 define void @vst2laneQi32(i32* %A, <4 x i32>* %B) nounwind {
168168 ;CHECK: vst2laneQi32:
169169 ;Check the alignment value. Max for this instruction is 64 bits:
170 ;CHECK: vst2.32 {d17[0], d19[0]}, [r0, :64]
170 ;CHECK: vst2.32 {d17[0], d19[0]}, [r0:64]
171171 %tmp0 = bitcast i32* %A to i8*
172172 %tmp1 = load <4 x i32>* %B
173173 call void @llvm.arm.neon.vst2lane.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 2, i32 16)
282282 define void @vst4lanei8(i8* %A, <8 x i8>* %B) nounwind {
283283 ;CHECK: vst4lanei8:
284284 ;Check the alignment value. Max for this instruction is 32 bits:
285 ;CHECK: vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0, :32]
285 ;CHECK: vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0:32]
286286 %tmp1 = load <8 x i8>* %B
287287 call void @llvm.arm.neon.vst4lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 8)
288288 ret void
291291 ;Check for a post-increment updating store.
292292 define void @vst4lanei8_update(i8** %ptr, <8 x i8>* %B) nounwind {
293293 ;CHECK: vst4lanei8_update:
294 ;CHECK: vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r1, :32]!
294 ;CHECK: vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r1:32]!
295295 %A = load i8** %ptr
296296 %tmp1 = load <8 x i8>* %B
297297 call void @llvm.arm.neon.vst4lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 8)
312312 define void @vst4lanei32(i32* %A, <2 x i32>* %B) nounwind {
313313 ;CHECK: vst4lanei32:
314314 ;Check the alignment value. Max for this instruction is 128 bits:
315 ;CHECK: vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0, :128]
315 ;CHECK: vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0:128]
316316 %tmp0 = bitcast i32* %A to i8*
317317 %tmp1 = load <2 x i32>* %B
318318 call void @llvm.arm.neon.vst4lane.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1, i32 16)
331331 define void @vst4laneQi16(i16* %A, <8 x i16>* %B) nounwind {
332332 ;CHECK: vst4laneQi16:
333333 ;Check the alignment value. Max for this instruction is 64 bits:
334 ;CHECK: vst4.16 {d17[3], d19[3], d21[3], d23[3]}, [r0, :64]
334 ;CHECK: vst4.16 {d17[3], d19[3], d21[3], d23[3]}, [r0:64]
335335 %tmp0 = bitcast i16* %A to i8*
336336 %tmp1 = load <8 x i16>* %B
337337 call void @llvm.arm.neon.vst4lane.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 7, i32 16)
2525 ; NEON: bic r4, r4, #15
2626 ; Stack pointer must be updated before the spills.
2727 ; NEON: mov sp, r4
28 ; NEON: vst1.64 {d8, d9, d10, d11}, [r4, :128]!
29 ; NEON: vst1.64 {d12, d13, d14, d15}, [r4, :128]
28 ; NEON: vst1.64 {d8, d9, d10, d11}, [r4:128]!
29 ; NEON: vst1.64 {d12, d13, d14, d15}, [r4:128]
3030 ; Stack pointer adjustment for the stack frame contents.
3131 ; This could legally happen before the spills.
3232 ; Since the spill slot is only 8 bytes, technically it would be fine to only
3535 ; NEON: sub sp, #16
3636 ; The epilog is free to use another scratch register than r4.
3737 ; NEON: add r[[R4:[0-9]+]], sp, #16
38 ; NEON: vld1.64 {d8, d9, d10, d11}, [r[[R4]], :128]!
39 ; NEON: vld1.64 {d12, d13, d14, d15}, [r[[R4]], :128]
38 ; NEON: vld1.64 {d8, d9, d10, d11}, [r[[R4]]:128]!
39 ; NEON: vld1.64 {d12, d13, d14, d15}, [r[[R4]]:128]
4040 ; The stack pointer restore must happen after the reloads.
4141 ; NEON: mov sp,
4242 ; NEON: pop
5656 ; NEON: bic r4, r4, #15
5757 ; Stack pointer must be updated before the spills.
5858 ; NEON: mov sp, r4
59 ; NEON: vst1.64 {d8, d9, d10, d11}, [r4, :128]!
60 ; NEON: vst1.64 {d12, d13}, [r4, :128]
59 ; NEON: vst1.64 {d8, d9, d10, d11}, [r4:128]!
60 ; NEON: vst1.64 {d12, d13}, [r4:128]
6161 ; NEON: vstr d14, [r4, #16]
6262 ; Epilog
6363 ; NEON: vld1.64 {d8, d9, d10, d11},
8383 ; NEON: bic r4, r4, #15
8484 ; Stack pointer must be updated before the spills.
8585 ; NEON: mov sp, r4
86 ; NEON: vst1.64 {d8, d9}, [r4, :128]
86 ; NEON: vst1.64 {d8, d9}, [r4:128]
8787 ; NEON: vstr d10, [r4, #16]
8888 ; Epilog
8989 ; NEON: vld1.64 {d8, d9},
1111 define void @aaa(%quuz* %this, i8* %block) {
1212 ; CHECK: aaa:
1313 ; CHECK: bic r4, r4, #15
14 ; CHECK: vst1.64 {{.*}}[{{.*}}, :128]
15 ; CHECK: vld1.64 {{.*}}[{{.*}}, :128]
14 ; CHECK: vst1.64 {{.*}}[{{.*}}:128]
15 ; CHECK: vld1.64 {{.*}}[{{.*}}:128]
1616 entry:
1717 %aligned_vec = alloca <4 x float>, align 16
1818 %"alloca point" = bitcast i32 0 to i32
5454 vld1.32 {d5, d6, d7, d8}, [r3], r8
5555 vld1.64 {d6, d7, d8, d9}, [r3:64], r8
5656
57 @ CHECK: vld1.8 {d16}, [r0, :64] @ encoding: [0x1f,0x07,0x60,0xf4]
57 @ CHECK: vld1.8 {d16}, [r0:64] @ encoding: [0x1f,0x07,0x60,0xf4]
5858 @ CHECK: vld1.16 {d16}, [r0] @ encoding: [0x4f,0x07,0x60,0xf4]
5959 @ CHECK: vld1.32 {d16}, [r0] @ encoding: [0x8f,0x07,0x60,0xf4]
6060 @ CHECK: vld1.64 {d16}, [r0] @ encoding: [0xcf,0x07,0x60,0xf4]
61 @ CHECK: vld1.8 {d16, d17}, [r0, :64] @ encoding: [0x1f,0x0a,0x60,0xf4]
62 @ CHECK: vld1.16 {d16, d17}, [r0, :128] @ encoding: [0x6f,0x0a,0x60,0xf4]
61 @ CHECK: vld1.8 {d16, d17}, [r0:64] @ encoding: [0x1f,0x0a,0x60,0xf4]
62 @ CHECK: vld1.16 {d16, d17}, [r0:128] @ encoding: [0x6f,0x0a,0x60,0xf4]
6363 @ CHECK: vld1.32 {d16, d17}, [r0] @ encoding: [0x8f,0x0a,0x60,0xf4]
6464 @ CHECK: vld1.64 {d16, d17}, [r0] @ encoding: [0xcf,0x0a,0x60,0xf4]
6565 @ CHECK: vld1.8 {d1, d2, d3}, [r3] @ encoding: [0x0f,0x16,0x23,0xf4]
66 @ CHECK: vld1.16 {d4, d5, d6}, [r3, :64] @ encoding: [0x5f,0x46,0x23,0xf4]
66 @ CHECK: vld1.16 {d4, d5, d6}, [r3:64] @ encoding: [0x5f,0x46,0x23,0xf4]
6767 @ CHECK: vld1.32 {d5, d6, d7}, [r3] @ encoding: [0x8f,0x56,0x23,0xf4]
68 @ CHECK: vld1.64 {d6, d7, d8}, [r3, :64] @ encoding: [0xdf,0x66,0x23,0xf4]
68 @ CHECK: vld1.64 {d6, d7, d8}, [r3:64] @ encoding: [0xdf,0x66,0x23,0xf4]
6969 @ CHECK: vld1.8 {d1, d2, d3, d4}, [r3] @ encoding: [0x0f,0x12,0x23,0xf4]
70 @ CHECK: vld1.16 {d4, d5, d6, d7}, [r3, :64] @ encoding: [0x5f,0x42,0x23,0xf4]
70 @ CHECK: vld1.16 {d4, d5, d6, d7}, [r3:64] @ encoding: [0x5f,0x42,0x23,0xf4]
7171 @ CHECK: vld1.32 {d5, d6, d7, d8}, [r3] @ encoding: [0x8f,0x52,0x23,0xf4]
72 @ CHECK: vld1.64 {d6, d7, d8, d9}, [r3, :64] @ encoding: [0xdf,0x62,0x23,0xf4]
73 @ CHECK: vld1.8 {d16}, [r0, :64]! @ encoding: [0x1d,0x07,0x60,0xf4]
72 @ CHECK: vld1.64 {d6, d7, d8, d9}, [r3:64] @ encoding: [0xdf,0x62,0x23,0xf4]
73 @ CHECK: vld1.8 {d16}, [r0:64]! @ encoding: [0x1d,0x07,0x60,0xf4]
7474
7575 @ CHECK: vld1.16 {d16}, [r0]! @ encoding: [0x4d,0x07,0x60,0xf4]
7676 @ CHECK: vld1.32 {d16}, [r0]! @ encoding: [0x8d,0x07,0x60,0xf4]
7777 @ CHECK: vld1.64 {d16}, [r0]! @ encoding: [0xcd,0x07,0x60,0xf4]
78 @ CHECK: vld1.8 {d16, d17}, [r0, :64]! @ encoding: [0x1d,0x0a,0x60,0xf4]
79 @ CHECK: vld1.16 {d16, d17}, [r0, :128]! @ encoding: [0x6d,0x0a,0x60,0xf4]
78 @ CHECK: vld1.8 {d16, d17}, [r0:64]! @ encoding: [0x1d,0x0a,0x60,0xf4]
79 @ CHECK: vld1.16 {d16, d17}, [r0:128]! @ encoding: [0x6d,0x0a,0x60,0xf4]
8080 @ CHECK: vld1.32 {d16, d17}, [r0]! @ encoding: [0x8d,0x0a,0x60,0xf4]
8181 @ CHECK: vld1.64 {d16, d17}, [r0]! @ encoding: [0xcd,0x0a,0x60,0xf4]
8282
83 @ CHECK: vld1.8 {d16}, [r0, :64], r5 @ encoding: [0x15,0x07,0x60,0xf4]
83 @ CHECK: vld1.8 {d16}, [r0:64], r5 @ encoding: [0x15,0x07,0x60,0xf4]
8484 @ CHECK: vld1.16 {d16}, [r0], r5 @ encoding: [0x45,0x07,0x60,0xf4]
8585 @ CHECK: vld1.32 {d16}, [r0], r5 @ encoding: [0x85,0x07,0x60,0xf4]
8686 @ CHECK: vld1.64 {d16}, [r0], r5 @ encoding: [0xc5,0x07,0x60,0xf4]
87 @ CHECK: vld1.8 {d16, d17}, [r0, :64], r5 @ encoding: [0x15,0x0a,0x60,0xf4]
88 @ CHECK: vld1.16 {d16, d17}, [r0, :128], r5 @ encoding: [0x65,0x0a,0x60,0xf4]
87 @ CHECK: vld1.8 {d16, d17}, [r0:64], r5 @ encoding: [0x15,0x0a,0x60,0xf4]
88 @ CHECK: vld1.16 {d16, d17}, [r0:128], r5 @ encoding: [0x65,0x0a,0x60,0xf4]
8989 @ CHECK: vld1.32 {d16, d17}, [r0], r5 @ encoding: [0x85,0x0a,0x60,0xf4]
9090 @ CHECK: vld1.64 {d16, d17}, [r0], r5 @ encoding: [0xc5,0x0a,0x60,0xf4]
9191
9292 @ CHECK: vld1.8 {d1, d2, d3}, [r3]! @ encoding: [0x0d,0x16,0x23,0xf4]
93 @ CHECK: vld1.16 {d4, d5, d6}, [r3, :64]! @ encoding: [0x5d,0x46,0x23,0xf4]
93 @ CHECK: vld1.16 {d4, d5, d6}, [r3:64]! @ encoding: [0x5d,0x46,0x23,0xf4]
9494 @ CHECK: vld1.32 {d5, d6, d7}, [r3]! @ encoding: [0x8d,0x56,0x23,0xf4]
95 @ CHECK: vld1.64 {d6, d7, d8}, [r3, :64]! @ encoding: [0xdd,0x66,0x23,0xf4]
95 @ CHECK: vld1.64 {d6, d7, d8}, [r3:64]! @ encoding: [0xdd,0x66,0x23,0xf4]
9696
9797 @ CHECK: vld1.8 {d1, d2, d3}, [r3], r6 @ encoding: [0x06,0x16,0x23,0xf4]
98 @ CHECK: vld1.16 {d4, d5, d6}, [r3, :64], r6 @ encoding: [0x56,0x46,0x23,0xf4]
98 @ CHECK: vld1.16 {d4, d5, d6}, [r3:64], r6 @ encoding: [0x56,0x46,0x23,0xf4]
9999 @ CHECK: vld1.32 {d5, d6, d7}, [r3], r6 @ encoding: [0x86,0x56,0x23,0xf4]
100 @ CHECK: vld1.64 {d6, d7, d8}, [r3, :64], r6 @ encoding: [0xd6,0x66,0x23,0xf4]
100 @ CHECK: vld1.64 {d6, d7, d8}, [r3:64], r6 @ encoding: [0xd6,0x66,0x23,0xf4]
101101
102102 @ CHECK: vld1.8 {d1, d2, d3, d4}, [r3]! @ encoding: [0x0d,0x12,0x23,0xf4]
103 @ CHECK: vld1.16 {d4, d5, d6, d7}, [r3, :64]! @ encoding: [0x5d,0x42,0x23,0xf4]
103 @ CHECK: vld1.16 {d4, d5, d6, d7}, [r3:64]! @ encoding: [0x5d,0x42,0x23,0xf4]
104104 @ CHECK: vld1.32 {d5, d6, d7, d8}, [r3]! @ encoding: [0x8d,0x52,0x23,0xf4]
105 @ CHECK: vld1.64 {d6, d7, d8, d9}, [r3, :64]! @ encoding: [0xdd,0x62,0x23,0xf4]
105 @ CHECK: vld1.64 {d6, d7, d8, d9}, [r3:64]! @ encoding: [0xdd,0x62,0x23,0xf4]
106106
107107 @ CHECK: vld1.8 {d1, d2, d3, d4}, [r3], r8 @ encoding: [0x08,0x12,0x23,0xf4]
108 @ CHECK: vld1.16 {d4, d5, d6, d7}, [r3, :64], r8 @ encoding: [0x58,0x42,0x23,0xf4]
108 @ CHECK: vld1.16 {d4, d5, d6, d7}, [r3:64], r8 @ encoding: [0x58,0x42,0x23,0xf4]
109109 @ CHECK: vld1.32 {d5, d6, d7, d8}, [r3], r8 @ encoding: [0x88,0x52,0x23,0xf4]
110 @ CHECK: vld1.64 {d6, d7, d8, d9}, [r3, :64], r8 @ encoding: [0xd8,0x62,0x23,0xf4]
110 @ CHECK: vld1.64 {d6, d7, d8, d9}, [r3:64], r8 @ encoding: [0xd8,0x62,0x23,0xf4]
111111
112112
113113 vld2.8 {d16, d17}, [r0:64]
131131 vld2.16 {d1, d2, d3, d4}, [r0:128], r6
132132 vld2.32 {q7, q8}, [r0:256], r6
133133
134 @ CHECK: vld2.8 {d16, d17}, [r0, :64] @ encoding: [0x1f,0x08,0x60,0xf4]
135 @ CHECK: vld2.16 {d16, d17}, [r0, :128] @ encoding: [0x6f,0x08,0x60,0xf4]
134 @ CHECK: vld2.8 {d16, d17}, [r0:64] @ encoding: [0x1f,0x08,0x60,0xf4]
135 @ CHECK: vld2.16 {d16, d17}, [r0:128] @ encoding: [0x6f,0x08,0x60,0xf4]
136136 @ CHECK: vld2.32 {d16, d17}, [r0] @ encoding: [0x8f,0x08,0x60,0xf4]
137 @ CHECK: vld2.8 {d16, d17, d18, d19}, [r0, :64] @ encoding: [0x1f,0x03,0x60,0xf4]
138 @ CHECK: vld2.16 {d16, d17, d18, d19}, [r0, :128] @ encoding: [0x6f,0x03,0x60,0xf4]
139 @ CHECK: vld2.32 {d16, d17, d18, d19}, [r0, :256] @ encoding: [0xbf,0x03,0x60,0xf4]
140
141 @ CHECK: vld2.8 {d19, d20}, [r0, :64]! @ encoding: [0x1d,0x38,0x60,0xf4]
142 @ CHECK: vld2.16 {d16, d17}, [r0, :128]! @ encoding: [0x6d,0x08,0x60,0xf4]
137 @ CHECK: vld2.8 {d16, d17, d18, d19}, [r0:64] @ encoding: [0x1f,0x03,0x60,0xf4]
138 @ CHECK: vld2.16 {d16, d17, d18, d19}, [r0:128] @ encoding: [0x6f,0x03,0x60,0xf4]
139 @ CHECK: vld2.32 {d16, d17, d18, d19}, [r0:256] @ encoding: [0xbf,0x03,0x60,0xf4]
140
141 @ CHECK: vld2.8 {d19, d20}, [r0:64]! @ encoding: [0x1d,0x38,0x60,0xf4]
142 @ CHECK: vld2.16 {d16, d17}, [r0:128]! @ encoding: [0x6d,0x08,0x60,0xf4]
143143 @ CHECK: vld2.32 {d20, d21}, [r0]! @ encoding: [0x8d,0x48,0x60,0xf4]
144 @ CHECK: vld2.8 {d4, d5, d6, d7}, [r0, :64]! @ encoding: [0x1d,0x43,0x20,0xf4]
145 @ CHECK: vld2.16 {d1, d2, d3, d4}, [r0, :128]! @ encoding: [0x6d,0x13,0x20,0xf4]
146 @ CHECK: vld2.32 {d14, d15, d16, d17}, [r0, :256]! @ encoding: [0xbd,0xe3,0x20,0xf4]
147
148 @ CHECK: vld2.8 {d19, d20}, [r0, :64], r6 @ encoding: [0x16,0x38,0x60,0xf4]
149 @ CHECK: vld2.16 {d16, d17}, [r0, :128], r6 @ encoding: [0x66,0x08,0x60,0xf4]
144 @ CHECK: vld2.8 {d4, d5, d6, d7}, [r0:64]! @ encoding: [0x1d,0x43,0x20,0xf4]
145 @ CHECK: vld2.16 {d1, d2, d3, d4}, [r0:128]! @ encoding: [0x6d,0x13,0x20,0xf4]
146 @ CHECK: vld2.32 {d14, d15, d16, d17}, [r0:256]! @ encoding: [0xbd,0xe3,0x20,0xf4]
147
148 @ CHECK: vld2.8 {d19, d20}, [r0:64], r6 @ encoding: [0x16,0x38,0x60,0xf4]
149 @ CHECK: vld2.16 {d16, d17}, [r0:128], r6 @ encoding: [0x66,0x08,0x60,0xf4]
150150 @ CHECK: vld2.32 {d20, d21}, [r0], r6 @ encoding: [0x86,0x48,0x60,0xf4]
151 @ CHECK: vld2.8 {d4, d5, d6, d7}, [r0, :64], r6 @ encoding: [0x16,0x43,0x20,0xf4]
152 @ CHECK: vld2.16 {d1, d2, d3, d4}, [r0, :128], r6 @ encoding: [0x66,0x13,0x20,0xf4]
153 @ CHECK: vld2.32 {d14, d15, d16, d17}, [r0, :256], r6 @ encoding: [0xb6,0xe3,0x20,0xf4]
151 @ CHECK: vld2.8 {d4, d5, d6, d7}, [r0:64], r6 @ encoding: [0x16,0x43,0x20,0xf4]
152 @ CHECK: vld2.16 {d1, d2, d3, d4}, [r0:128], r6 @ encoding: [0x66,0x13,0x20,0xf4]
153 @ CHECK: vld2.32 {d14, d15, d16, d17}, [r0:256], r6 @ encoding: [0xb6,0xe3,0x20,0xf4]
154154
155155
156156 vld3.8 {d16, d17, d18}, [r1]
178178 @ CHECK: vld3.8 {d16, d17, d18}, [r1] @ encoding: [0x0f,0x04,0x61,0xf4]
179179 @ CHECK: vld3.16 {d6, d7, d8}, [r2] @ encoding: [0x4f,0x64,0x22,0xf4]
180180 @ CHECK: vld3.32 {d1, d2, d3}, [r3] @ encoding: [0x8f,0x14,0x23,0xf4]
181 @ CHECK: vld3.8 {d16, d18, d20}, [r0, :64] @ encoding: [0x1f,0x05,0x60,0xf4]
181 @ CHECK: vld3.8 {d16, d18, d20}, [r0:64] @ encoding: [0x1f,0x05,0x60,0xf4]
182182 @ CHECK: vld3.16 {d27, d29, d31}, [r4] @ encoding: [0x4f,0xb5,0x64,0xf4]
183183 @ CHECK: vld3.32 {d6, d8, d10}, [r5] @ encoding: [0x8f,0x65,0x25,0xf4]
184184 @ CHECK: vld3.8 {d12, d13, d14}, [r6], r1 @ encoding: [0x01,0xc4,0x26,0xf4]
190190 @ CHECK: vld3.8 {d6, d7, d8}, [r8]! @ encoding: [0x0d,0x64,0x28,0xf4]
191191 @ CHECK: vld3.16 {d9, d10, d11}, [r7]! @ encoding: [0x4d,0x94,0x27,0xf4]
192192 @ CHECK: vld3.32 {d1, d2, d3}, [r6]! @ encoding: [0x8d,0x14,0x26,0xf4]
193 @ CHECK: vld3.8 {d16, d18, d20}, [r0, :64]! @ encoding: [0x1d,0x05,0x60,0xf4]
193 @ CHECK: vld3.8 {d16, d18, d20}, [r0:64]! @ encoding: [0x1d,0x05,0x60,0xf4]
194194 @ CHECK: vld3.16 {d20, d22, d24}, [r5]! @ encoding: [0x4d,0x45,0x65,0xf4]
195195 @ CHECK: vld3.32 {d5, d7, d9}, [r4]! @ encoding: [0x8d,0x55,0x24,0xf4]
196196
216216 vld4.i16 {d16, d18, d20, d22}, [r6], r3
217217 vld4.i32 {d17, d19, d21, d23}, [r9], r4
218218
219 @ CHECK: vld4.8 {d16, d17, d18, d19}, [r1, :64] @ encoding: [0x1f,0x00,0x61,0xf4]
220 @ CHECK: vld4.16 {d16, d17, d18, d19}, [r2, :128] @ encoding: [0x6f,0x00,0x62,0xf4]
221 @ CHECK: vld4.32 {d16, d17, d18, d19}, [r3, :256] @ encoding: [0xbf,0x00,0x63,0xf4]
222 @ CHECK: vld4.8 {d17, d19, d21, d23}, [r5, :256] @ encoding: [0x3f,0x11,0x65,0xf4]
219 @ CHECK: vld4.8 {d16, d17, d18, d19}, [r1:64] @ encoding: [0x1f,0x00,0x61,0xf4]
220 @ CHECK: vld4.16 {d16, d17, d18, d19}, [r2:128] @ encoding: [0x6f,0x00,0x62,0xf4]
221 @ CHECK: vld4.32 {d16, d17, d18, d19}, [r3:256] @ encoding: [0xbf,0x00,0x63,0xf4]
222 @ CHECK: vld4.8 {d17, d19, d21, d23}, [r5:256] @ encoding: [0x3f,0x11,0x65,0xf4]
223223 @ CHECK: vld4.16 {d17, d19, d21, d23}, [r7] @ encoding: [0x4f,0x11,0x67,0xf4]
224224 @ CHECK: vld4.32 {d16, d18, d20, d22}, [r8] @ encoding: [0x8f,0x01,0x68,0xf4]
225 @ CHECK: vld4.8 {d16, d17, d18, d19}, [r1, :64]! @ encoding: [0x1d,0x00,0x61,0xf4]
226 @ CHECK: vld4.16 {d16, d17, d18, d19}, [r2, :128]! @ encoding: [0x6d,0x00,0x62,0xf4]
227 @ CHECK: vld4.32 {d16, d17, d18, d19}, [r3, :256]! @ encoding: [0xbd,0x00,0x63,0xf4]
228 @ CHECK: vld4.8 {d17, d19, d21, d23}, [r5, :256]! @ encoding: [0x3d,0x11,0x65,0xf4]
225 @ CHECK: vld4.8 {d16, d17, d18, d19}, [r1:64]! @ encoding: [0x1d,0x00,0x61,0xf4]
226 @ CHECK: vld4.16 {d16, d17, d18, d19}, [r2:128]! @ encoding: [0x6d,0x00,0x62,0xf4]
227 @ CHECK: vld4.32 {d16, d17, d18, d19}, [r3:256]! @ encoding: [0xbd,0x00,0x63,0xf4]
228 @ CHECK: vld4.8 {d17, d19, d21, d23}, [r5:256]! @ encoding: [0x3d,0x11,0x65,0xf4]
229229 @ CHECK: vld4.16 {d17, d19, d21, d23}, [r7]! @ encoding: [0x4d,0x11,0x67,0xf4]
230230 @ CHECK: vld4.32 {d16, d18, d20, d22}, [r8]! @ encoding: [0x8d,0x01,0x68,0xf4]
231 @ CHECK: vld4.8 {d16, d17, d18, d19}, [r1, :64], r8 @ encoding: [0x18,0x00,0x61,0xf4]
231 @ CHECK: vld4.8 {d16, d17, d18, d19}, [r1:64], r8 @ encoding: [0x18,0x00,0x61,0xf4]
232232 @ CHECK: vld4.16 {d16, d17, d18, d19}, [r2], r7 @ encoding: [0x47,0x00,0x62,0xf4]
233 @ CHECK: vld4.32 {d16, d17, d18, d19}, [r3, :64], r5 @ encoding: [0x95,0x00,0x63,0xf4]
234 @ CHECK: vld4.8 {d16, d18, d20, d22}, [r4, :256], r2 @ encoding: [0x32,0x01,0x64,0xf4]
233 @ CHECK: vld4.32 {d16, d17, d18, d19}, [r3:64], r5 @ encoding: [0x95,0x00,0x63,0xf4]
234 @ CHECK: vld4.8 {d16, d18, d20, d22}, [r4:256], r2 @ encoding: [0x32,0x01,0x64,0xf4]
235235 @ CHECK: vld4.16 {d16, d18, d20, d22}, [r6], r3 @ encoding: [0x43,0x01,0x66,0xf4]
236236 @ CHECK: vld4.32 {d17, d19, d21, d23}, [r9], r4 @ encoding: [0x84,0x11,0x69,0xf4]
237237
259259 vld1.16 d12[2], [r2], r2
260260
261261 @ CHECK: vld1.8 {d16[3]}, [r0] @ encoding: [0x6f,0x00,0xe0,0xf4]
262 @ CHECK: vld1.16 {d16[2]}, [r0, :16] @ encoding: [0x9f,0x04,0xe0,0xf4]
263 @ CHECK: vld1.32 {d16[1]}, [r0, :32] @ encoding: [0xbf,0x08,0xe0,0xf4]
262 @ CHECK: vld1.16 {d16[2]}, [r0:16] @ encoding: [0x9f,0x04,0xe0,0xf4]
263 @ CHECK: vld1.32 {d16[1]}, [r0:32] @ encoding: [0xbf,0x08,0xe0,0xf4]
264264 @ CHECK: vld1.8 {d12[6]}, [r2]! @ encoding: [0xcd,0xc0,0xa2,0xf4]
265265 @ CHECK: vld1.8 {d12[6]}, [r2], r2 @ encoding: [0xc2,0xc0,0xa2,0xf4]
266266 @ CHECK: vld1.16 {d12[3]}, [r2]! @ encoding: [0xcd,0xc4,0xa2,0xf4]
283283 vld2.32 {d22[ ],d23[ ]}, [r5], r4
284284 vld2.32 {d22[ ],d24[ ]}, [r6], r4
285285
286 @ CHECK: vld2.8 {d16[1], d17[1]}, [r0, :16] @ encoding: [0x3f,0x01,0xe0,0xf4]
287 @ CHECK: vld2.16 {d16[1], d17[1]}, [r0, :32] @ encoding: [0x5f,0x05,0xe0,0xf4]
286 @ CHECK: vld2.8 {d16[1], d17[1]}, [r0:16] @ encoding: [0x3f,0x01,0xe0,0xf4]
287 @ CHECK: vld2.16 {d16[1], d17[1]}, [r0:32] @ encoding: [0x5f,0x05,0xe0,0xf4]
288288 @ CHECK: vld2.32 {d16[1], d17[1]}, [r0] @ encoding: [0x8f,0x09,0xe0,0xf4]
289289 @ CHECK: vld2.16 {d17[1], d19[1]}, [r0] @ encoding: [0x6f,0x15,0xe0,0xf4]
290 @ CHECK: vld2.32 {d17[0], d19[0]}, [r0, :64] @ encoding: [0x5f,0x19,0xe0,0xf4]
291 @ CHECK: vld2.32 {d17[0], d19[0]}, [r0, :64]! @ encoding: [0x5d,0x19,0xe0,0xf4]
290 @ CHECK: vld2.32 {d17[0], d19[0]}, [r0:64] @ encoding: [0x5f,0x19,0xe0,0xf4]
291 @ CHECK: vld2.32 {d17[0], d19[0]}, [r0:64]! @ encoding: [0x5d,0x19,0xe0,0xf4]
292292 @ CHECK: vld2.8 {d2[4], d3[4]}, [r2], r3 @ encoding: [0x83,0x21,0xa2,0xf4]
293293 @ CHECK: vld2.8 {d2[4], d3[4]}, [r2]! @ encoding: [0x8d,0x21,0xa2,0xf4]
294294 @ CHECK: vld2.8 {d2[4], d3[4]}, [r2] @ encoding: [0x8f,0x21,0xa2,0xf4]
399399 @ CHECK: vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [r3] @ encoding: [0x8f,0x0b,0xe3,0xf4]
400400 @ CHECK: vld4.16 {d17[1], d19[1], d21[1], d23[1]}, [r7] @ encoding: [0x6f,0x17,0xe7,0xf4]
401401 @ CHECK: vld4.32 {d16[1], d18[1], d20[1], d22[1]}, [r8] @ encoding: [0xcf,0x0b,0xe8,0xf4]
402 @ CHECK: vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [r1, :32]! @ encoding: [0x3d,0x03,0xe1,0xf4]
403 @ CHECK: vld4.16 {d16[1], d17[1], d18[1], d19[1]}, [r2, :64]! @ encoding: [0x5d,0x07,0xe2,0xf4]
404 @ CHECK: vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [r3, :128]! @ encoding: [0xad,0x0b,0xe3,0xf4]
402 @ CHECK: vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [r1:32]! @ encoding: [0x3d,0x03,0xe1,0xf4]
403 @ CHECK: vld4.16 {d16[1], d17[1], d18[1], d19[1]}, [r2:64]! @ encoding: [0x5d,0x07,0xe2,0xf4]
404 @ CHECK: vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [r3:128]! @ encoding: [0xad,0x0b,0xe3,0xf4]
405405 @ CHECK: vld4.16 {d17[1], d18[1], d19[1], d20[1]}, [r7]! @ encoding: [0x6d,0x17,0xe7,0xf4]
406406 @ CHECK: vld4.32 {d16[1], d18[1], d20[1], d22[1]}, [r8]! @ encoding: [0xcd,0x0b,0xe8,0xf4]
407 @ CHECK: vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [r1, :32], r8 @ encoding: [0x38,0x03,0xe1,0xf4]
407 @ CHECK: vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [r1:32], r8 @ encoding: [0x38,0x03,0xe1,0xf4]
408408 @ CHECK: vld4.16 {d16[1], d17[1], d18[1], d19[1]}, [r2], r7 @ encoding: [0x47,0x07,0xe2,0xf4]
409 @ CHECK: vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [r3, :64], r5 @ encoding: [0x95,0x0b,0xe3,0xf4]
409 @ CHECK: vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [r3:64], r5 @ encoding: [0x95,0x0b,0xe3,0xf4]
410410 @ CHECK: vld4.16 {d16[1], d18[1], d20[1], d22[1]}, [r6], r3 @ encoding: [0x63,0x07,0xe6,0xf4]
411411 @ CHECK: vld4.32 {d17[1], d19[1], d21[1], d23[1]}, [r9], r4 @ encoding: [0xc4,0x1b,0xe9,0xf4]
412412
492492 vld1.f64 {d2-d5}, [r2:128]!
493493 vld1.f64 {d2,d3,d4,d5}, [r2:128]!
494494
495 @ CHECK: vld1.64 {d2, d3, d4, d5}, [r2, :128]! @ encoding: [0xed,0x22,0x22,0xf4]
496 @ CHECK: vld1.64 {d2, d3, d4, d5}, [r2, :128]! @ encoding: [0xed,0x22,0x22,0xf4]
495 @ CHECK: vld1.64 {d2, d3, d4, d5}, [r2:128]! @ encoding: [0xed,0x22,0x22,0xf4]
496 @ CHECK: vld1.64 {d2, d3, d4, d5}, [r2:128]! @ encoding: [0xed,0x22,0x22,0xf4]
497497
498498
499499 @ verify that the old incorrect alignment specifier syntax (", :")
501501 vld2.8 {d16, d17}, [r0, :64]
502502 vld2.16 {d16, d17}, [r0, :128]
503503
504 @ CHECK: vld2.8 {d16, d17}, [r0, :64] @ encoding: [0x1f,0x08,0x60,0xf4]
505 @ CHECK: vld2.16 {d16, d17}, [r0, :128] @ encoding: [0x6f,0x08,0x60,0xf4]
504 @ CHECK: vld2.8 {d16, d17}, [r0:64] @ encoding: [0x1f,0x08,0x60,0xf4]
505 @ CHECK: vld2.16 {d16, d17}, [r0:128] @ encoding: [0x6f,0x08,0x60,0xf4]
1414 vst1.16 {d16, d17, d18, d19}, [r1:64]!
1515 vst1.64 {d16, d17, d18, d19}, [r3], r2
1616
17 @ CHECK: vst1.8 {d16}, [r0, :64] @ encoding: [0x1f,0x07,0x40,0xf4]
17 @ CHECK: vst1.8 {d16}, [r0:64] @ encoding: [0x1f,0x07,0x40,0xf4]
1818 @ CHECK: vst1.16 {d16}, [r0] @ encoding: [0x4f,0x07,0x40,0xf4]
1919 @ CHECK: vst1.32 {d16}, [r0] @ encoding: [0x8f,0x07,0x40,0xf4]
2020 @ CHECK: vst1.64 {d16}, [r0] @ encoding: [0xcf,0x07,0x40,0xf4]
21 @ CHECK: vst1.8 {d16, d17}, [r0, :64] @ encoding: [0x1f,0x0a,0x40,0xf4]
22 @ CHECK: vst1.16 {d16, d17}, [r0, :128] @ encoding: [0x6f,0x0a,0x40,0xf4]
21 @ CHECK: vst1.8 {d16, d17}, [r0:64] @ encoding: [0x1f,0x0a,0x40,0xf4]
22 @ CHECK: vst1.16 {d16, d17}, [r0:128] @ encoding: [0x6f,0x0a,0x40,0xf4]
2323 @ CHECK: vst1.32 {d16, d17}, [r0] @ encoding: [0x8f,0x0a,0x40,0xf4]
2424 @ CHECK: vst1.64 {d16, d17}, [r0] @ encoding: [0xcf,0x0a,0x40,0xf4]
25 @ CHECK: vst1.8 {d16, d17, d18}, [r0, :64] @ encoding: [0x1f,0x06,0x40,0xf4]
26 @ CHECK: vst1.8 {d16, d17, d18}, [r0, :64]! @ encoding: [0x1d,0x06,0x40,0xf4]
25 @ CHECK: vst1.8 {d16, d17, d18}, [r0:64] @ encoding: [0x1f,0x06,0x40,0xf4]
26 @ CHECK: vst1.8 {d16, d17, d18}, [r0:64]! @ encoding: [0x1d,0x06,0x40,0xf4]
2727 @ CHECK: vst1.8 {d16, d17, d18}, [r0], r3 @ encoding: [0x03,0x06,0x40,0xf4]
28 @ CHECK: vst1.8 {d16, d17, d18, d19}, [r0, :64] @ encoding: [0x1f,0x02,0x40,0xf4]
29 @ CHECK: vst1.16 {d16, d17, d18, d19}, [r1, :64]! @ encoding: [0x5d,0x02,0x41,0xf4]
28 @ CHECK: vst1.8 {d16, d17, d18, d19}, [r0:64] @ encoding: [0x1f,0x02,0x40,0xf4]
29 @ CHECK: vst1.16 {d16, d17, d18, d19}, [r1:64]! @ encoding: [0x5d,0x02,0x41,0xf4]
3030 @ CHECK: vst1.64 {d16, d17, d18, d19}, [r3], r2 @ encoding: [0xc2,0x02,0x43,0xf4]
3131
3232
4343 vst2.16 {d18-d21}, [r0:128]!
4444 vst2.32 {q4, q5}, [r0:256]!
4545
46 @ CHECK: vst2.8 {d16, d17}, [r0, :64] @ encoding: [0x1f,0x08,0x40,0xf4]
47 @ CHECK: vst2.16 {d16, d17}, [r0, :128] @ encoding: [0x6f,0x08,0x40,0xf4]
46 @ CHECK: vst2.8 {d16, d17}, [r0:64] @ encoding: [0x1f,0x08,0x40,0xf4]
47 @ CHECK: vst2.16 {d16, d17}, [r0:128] @ encoding: [0x6f,0x08,0x40,0xf4]
4848 @ CHECK: vst2.32 {d16, d17}, [r0] @ encoding: [0x8f,0x08,0x40,0xf4]
49 @ CHECK: vst2.8 {d16, d17, d18, d19}, [r0, :64] @ encoding: [0x1f,0x03,0x40,0xf4]
50 @ CHECK: vst2.16 {d16, d17, d18, d19}, [r0, :128] @ encoding: [0x6f,0x03,0x40,0xf4]
51 @ CHECK: vst2.32 {d16, d17, d18, d19}, [r0, :256] @ encoding: [0xbf,0x03,0x40,0xf4]
52 @ CHECK: vst2.8 {d16, d17}, [r0, :64]! @ encoding: [0x1d,0x08,0x40,0xf4]
53 @ CHECK: vst2.16 {d30, d31}, [r0, :128]! @ encoding: [0x6d,0xe8,0x40,0xf4]
49 @ CHECK: vst2.8 {d16, d17, d18, d19}, [r0:64] @ encoding: [0x1f,0x03,0x40,0xf4]
50 @ CHECK: vst2.16 {d16, d17, d18, d19}, [r0:128] @ encoding: [0x6f,0x03,0x40,0xf4]
51 @ CHECK: vst2.32 {d16, d17, d18, d19}, [r0:256] @ encoding: [0xbf,0x03,0x40,0xf4]
52 @ CHECK: vst2.8 {d16, d17}, [r0:64]! @ encoding: [0x1d,0x08,0x40,0xf4]
53 @ CHECK: vst2.16 {d30, d31}, [r0:128]! @ encoding: [0x6d,0xe8,0x40,0xf4]
5454 @ CHECK: vst2.32 {d14, d15}, [r0]! @ encoding: [0x8d,0xe8,0x00,0xf4]
55 @ CHECK: vst2.8 {d16, d17, d18, d19}, [r0, :64]! @ encoding: [0x1d,0x03,0x40,0xf4]
56 @ CHECK: vst2.16 {d18, d19, d20, d21}, [r0, :128]! @ encoding: [0x6d,0x23,0x40,0xf4]
57 @ CHECK: vst2.32 {d8, d9, d10, d11}, [r0, :256]! @ encoding: [0xbd,0x83,0x00,0xf4]
55 @ CHECK: vst2.8 {d16, d17, d18, d19}, [r0:64]! @ encoding: [0x1d,0x03,0x40,0xf4]
56 @ CHECK: vst2.16 {d18, d19, d20, d21}, [r0:128]! @ encoding: [0x6d,0x23,0x40,0xf4]
57 @ CHECK: vst2.32 {d8, d9, d10, d11}, [r0:256]! @ encoding: [0xbd,0x83,0x00,0xf4]
5858
5959
6060 vst3.8 {d16, d17, d18}, [r1]
8181 @ CHECK: vst3.8 {d16, d17, d18}, [r1] @ encoding: [0x0f,0x04,0x41,0xf4]
8282 @ CHECK: vst3.16 {d6, d7, d8}, [r2] @ encoding: [0x4f,0x64,0x02,0xf4]
8383 @ CHECK: vst3.32 {d1, d2, d3}, [r3] @ encoding: [0x8f,0x14,0x03,0xf4]
84 @ CHECK: vst3.8 {d16, d18, d20}, [r0, :64] @ encoding: [0x1f,0x05,0x40,0xf4]
84 @ CHECK: vst3.8 {d16, d18, d20}, [r0:64] @ encoding: [0x1f,0x05,0x40,0xf4]
8585 @ CHECK: vst3.16 {d27, d29, d31}, [r4] @ encoding: [0x4f,0xb5,0x44,0xf4]
8686 @ CHECK: vst3.32 {d6, d8, d10}, [r5] @ encoding: [0x8f,0x65,0x05,0xf4]
8787 @ CHECK: vst3.8 {d12, d13, d14}, [r6], r1 @ encoding: [0x01,0xc4,0x06,0xf4]
9393 @ CHECK: vst3.8 {d6, d7, d8}, [r8]! @ encoding: [0x0d,0x64,0x08,0xf4]
9494 @ CHECK: vst3.16 {d9, d10, d11}, [r7]! @ encoding: [0x4d,0x94,0x07,0xf4]
9595 @ CHECK: vst3.32 {d1, d2, d3}, [r6]! @ encoding: [0x8d,0x14,0x06,0xf4]
96 @ CHECK: vst3.8 {d16, d18, d20}, [r0, :64]! @ encoding: [0x1d,0x05,0x40,0xf4]
96 @ CHECK: vst3.8 {d16, d18, d20}, [r0:64]! @ encoding: [0x1d,0x05,0x40,0xf4]
9797 @ CHECK: vst3.16 {d20, d22, d24}, [r5]! @ encoding: [0x4d,0x45,0x45,0xf4]
9898 @ CHECK: vst3.32 {d5, d7, d9}, [r4]! @ encoding: [0x8d,0x55,0x04,0xf4]
9999
119119 vst4.i16 {d16, d18, d20, d22}, [r6], r3
120120 vst4.i32 {d17, d19, d21, d23}, [r9], r4
121121
122 @ CHECK: vst4.8 {d16, d17, d18, d19}, [r1, :64] @ encoding: [0x1f,0x00,0x41,0xf4]
123 @ CHECK: vst4.16 {d16, d17, d18, d19}, [r2, :128] @ encoding: [0x6f,0x00,0x42,0xf4]
124 @ CHECK: vst4.32 {d16, d17, d18, d19}, [r3, :256] @ encoding: [0xbf,0x00,0x43,0xf4]
125 @ CHECK: vst4.8 {d17, d19, d21, d23}, [r5, :256] @ encoding: [0x3f,0x11,0x45,0xf4]
122 @ CHECK: vst4.8 {d16, d17, d18, d19}, [r1:64] @ encoding: [0x1f,0x00,0x41,0xf4]
123 @ CHECK: vst4.16 {d16, d17, d18, d19}, [r2:128] @ encoding: [0x6f,0x00,0x42,0xf4]
124 @ CHECK: vst4.32 {d16, d17, d18, d19}, [r3:256] @ encoding: [0xbf,0x00,0x43,0xf4]
125 @ CHECK: vst4.8 {d17, d19, d21, d23}, [r5:256] @ encoding: [0x3f,0x11,0x45,0xf4]
126126 @ CHECK: vst4.16 {d17, d19, d21, d23}, [r7] @ encoding: [0x4f,0x11,0x47,0xf4]
127127 @ CHECK: vst4.32 {d16, d18, d20, d22}, [r8] @ encoding: [0x8f,0x01,0x48,0xf4]
128 @ CHECK: vst4.8 {d16, d17, d18, d19}, [r1, :64]! @ encoding: [0x1d,0x00,0x41,0xf4]
129 @ CHECK: vst4.16 {d16, d17, d18, d19}, [r2, :128]! @ encoding: [0x6d,0x00,0x42,0xf4]
130 @ CHECK: vst4.32 {d16, d17, d18, d19}, [r3, :256]! @ encoding: [0xbd,0x00,0x43,0xf4]
131 @ CHECK: vst4.8 {d17, d19, d21, d23}, [r5, :256]! @ encoding: [0x3d,0x11,0x45,0xf4]
128 @ CHECK: vst4.8 {d16, d17, d18, d19}, [r1:64]! @ encoding: [0x1d,0x00,0x41,0xf4]
129 @ CHECK: vst4.16 {d16, d17, d18, d19}, [r2:128]! @ encoding: [0x6d,0x00,0x42,0xf4]
130 @ CHECK: vst4.32 {d16, d17, d18, d19}, [r3:256]! @ encoding: [0xbd,0x00,0x43,0xf4]
131 @ CHECK: vst4.8 {d17, d19, d21, d23}, [r5:256]! @ encoding: [0x3d,0x11,0x45,0xf4]
132132 @ CHECK: vst4.16 {d17, d19, d21, d23}, [r7]! @ encoding: [0x4d,0x11,0x47,0xf4]
133133 @ CHECK: vst4.32 {d16, d18, d20, d22}, [r8]! @ encoding: [0x8d,0x01,0x48,0xf4]
134 @ CHECK: vst4.8 {d16, d17, d18, d19}, [r1, :64], r8 @ encoding: [0x18,0x00,0x41,0xf4]
134 @ CHECK: vst4.8 {d16, d17, d18, d19}, [r1:64], r8 @ encoding: [0x18,0x00,0x41,0xf4]
135135 @ CHECK: vst4.16 {d16, d17, d18, d19}, [r2], r7 @ encoding: [0x47,0x00,0x42,0xf4]
136 @ CHECK: vst4.32 {d16, d17, d18, d19}, [r3, :64], r5 @ encoding: [0x95,0x00,0x43,0xf4]
137 @ CHECK: vst4.8 {d16, d18, d20, d22}, [r4, :256], r2 @ encoding: [0x32,0x01,0x44,0xf4]
136 @ CHECK: vst4.32 {d16, d17, d18, d19}, [r3:64], r5 @ encoding: [0x95,0x00,0x43,0xf4]
137 @ CHECK: vst4.8 {d16, d18, d20, d22}, [r4:256], r2 @ encoding: [0x32,0x01,0x44,0xf4]
138138 @ CHECK: vst4.16 {d16, d18, d20, d22}, [r6], r3 @ encoding: [0x43,0x01,0x46,0xf4]
139139 @ CHECK: vst4.32 {d17, d19, d21, d23}, [r9], r4 @ encoding: [0x84,0x11,0x49,0xf4]
140140
156156 vst2.16 {d2[1], d4[1]}, [r3], r5
157157 vst2.u32 {d5[0], d7[0]}, [r4:64], r7
158158
159 @ CHECK: vst2.8 {d16[1], d17[1]}, [r0, :16] @ encoding: [0x3f,0x01,0xc0,0xf4]
160 @ CHECK: vst2.16 {d16[1], d17[1]}, [r0, :32] @ encoding: [0x5f,0x05,0xc0,0xf4]
159 @ CHECK: vst2.8 {d16[1], d17[1]}, [r0:16] @ encoding: [0x3f,0x01,0xc0,0xf4]
160 @ CHECK: vst2.16 {d16[1], d17[1]}, [r0:32] @ encoding: [0x5f,0x05,0xc0,0xf4]
161161 @ CHECK: vst2.32 {d16[1], d17[1]}, [r0] @ encoding: [0x8f,0x09,0xc0,0xf4]
162162 @ CHECK: vst2.16 {d17[1], d19[1]}, [r0] @ encoding: [0x6f,0x15,0xc0,0xf4]
163 @ CHECK: vst2.32 {d17[0], d19[0]}, [r0, :64] @ encoding: [0x5f,0x19,0xc0,0xf4]
163 @ CHECK: vst2.32 {d17[0], d19[0]}, [r0:64] @ encoding: [0x5f,0x19,0xc0,0xf4]
164164
165165 @ CHECK: vst2.8 {d2[4], d3[4]}, [r2], r3 @ encoding: [0x83,0x21,0x82,0xf4]
166166 @ CHECK: vst2.8 {d2[4], d3[4]}, [r2]! @ encoding: [0x8d,0x21,0x82,0xf4]
167167 @ CHECK: vst2.8 {d2[4], d3[4]}, [r2] @ encoding: [0x8f,0x21,0x82,0xf4]
168168
169169 @ CHECK: vst2.16 {d17[1], d19[1]}, [r0] @ encoding: [0x6f,0x15,0xc0,0xf4]
170 @ CHECK: vst2.32 {d17[0], d19[0]}, [r0, :64] @ encoding: [0x5f,0x19,0xc0,0xf4]
170 @ CHECK: vst2.32 {d17[0], d19[0]}, [r0:64] @ encoding: [0x5f,0x19,0xc0,0xf4]
171171 @ CHECK: vst2.16 {d7[1], d9[1]}, [r1]! @ encoding: [0x6d,0x75,0x81,0xf4]
172 @ CHECK: vst2.32 {d6[0], d8[0]}, [r2, :64]! @ encoding: [0x5d,0x69,0x82,0xf4]
172 @ CHECK: vst2.32 {d6[0], d8[0]}, [r2:64]! @ encoding: [0x5d,0x69,0x82,0xf4]
173173 @ CHECK: vst2.16 {d2[1], d4[1]}, [r3], r5 @ encoding: [0x65,0x25,0x83,0xf4]
174 @ CHECK: vst2.32 {d5[0], d7[0]}, [r4, :64], r7 @ encoding: [0x57,0x59,0x84,0xf4]
174 @ CHECK: vst2.32 {d5[0], d7[0]}, [r4:64], r7 @ encoding: [0x57,0x59,0x84,0xf4]
175175
176176
177177 vst3.8 {d16[1], d17[1], d18[1]}, [r1]
232232 @ CHECK: vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r3] @ encoding: [0x8f,0x0b,0xc3,0xf4]
233233 @ CHECK: vst4.16 {d17[1], d19[1], d21[1], d23[1]}, [r7] @ encoding: [0x6f,0x17,0xc7,0xf4]
234234 @ CHECK: vst4.32 {d16[1], d18[1], d20[1], d22[1]}, [r8] @ encoding: [0xcf,0x0b,0xc8,0xf4]
235 @ CHECK: vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r1, :32]! @ encoding: [0x3d,0x03,0xc1,0xf4]
236 @ CHECK: vst4.16 {d16[1], d17[1], d18[1], d19[1]}, [r2, :64]! @ encoding: [0x5d,0x07,0xc2,0xf4]
237 @ CHECK: vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r3, :128]! @ encoding: [0xad,0x0b,0xc3,0xf4]
235 @ CHECK: vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r1:32]! @ encoding: [0x3d,0x03,0xc1,0xf4]
236 @ CHECK: vst4.16 {d16[1], d17[1], d18[1], d19[1]}, [r2:64]! @ encoding: [0x5d,0x07,0xc2,0xf4]
237 @ CHECK: vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r3:128]! @ encoding: [0xad,0x0b,0xc3,0xf4]
238238 @ CHECK: vst4.16 {d17[1], d18[1], d19[1], d20[1]}, [r7]! @ encoding: [0x6d,0x17,0xc7,0xf4]
239239 @ CHECK: vst4.32 {d16[1], d18[1], d20[1], d22[1]}, [r8]! @ encoding: [0xcd,0x0b,0xc8,0xf4]
240 @ CHECK: vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r1, :32], r8 @ encoding: [0x38,0x03,0xc1,0xf4]
240 @ CHECK: vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r1:32], r8 @ encoding: [0x38,0x03,0xc1,0xf4]
241241 @ CHECK: vst4.16 {d16[1], d17[1], d18[1], d19[1]}, [r2], r7 @ encoding: [0x47,0x07,0xc2,0xf4]
242 @ CHECK: vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r3, :64], r5 @ encoding: [0x95,0x0b,0xc3,0xf4]
242 @ CHECK: vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r3:64], r5 @ encoding: [0x95,0x0b,0xc3,0xf4]
243243 @ CHECK: vst4.16 {d16[1], d18[1], d20[1], d22[1]}, [r6], r3 @ encoding: [0x63,0x07,0xc6,0xf4]
244244 @ CHECK: vst4.32 {d17[1], d19[1], d21[1], d23[1]}, [r9], r4 @ encoding: [0xc4,0x1b,0xc9,0xf4]
245245
271271 vst1.32 {d9[1]}, [r3:32]
272272 vst1.32 {d27[1]}, [r9:32]!
273273 vst1.32 {d27[1]}, [r3:32], r5
274 @ CHECK: vst1.32 {d9[1]}, [r3, :32] @ encoding: [0xbf,0x98,0x83,0xf4]
275 @ CHECK: vst1.32 {d27[1]}, [r9, :32]! @ encoding: [0xbd,0xb8,0xc9,0xf4]
276 @ CHECK: vst1.32 {d27[1]}, [r3, :32], r5 @ encoding: [0xb5,0xb8,0xc3,0xf4]
274 @ CHECK: vst1.32 {d9[1]}, [r3:32] @ encoding: [0xbf,0x98,0x83,0xf4]
275 @ CHECK: vst1.32 {d27[1]}, [r9:32]! @ encoding: [0xbd,0xb8,0xc9,0xf4]
276 @ CHECK: vst1.32 {d27[1]}, [r3:32], r5 @ encoding: [0xb5,0xb8,0xc3,0xf4]
277277
278278 @ verify that the old incorrect alignment specifier syntax (", :")
279279 @ still gets accepted.
280280 vst2.8 {d16, d17}, [r0, :64]
281281 vst2.16 {d16, d17}, [r0, :128]
282282
283 @ CHECK: vst2.8 {d16, d17}, [r0, :64] @ encoding: [0x1f,0x08,0x40,0xf4]
284 @ CHECK: vst2.16 {d16, d17}, [r0, :128] @ encoding: [0x6f,0x08,0x40,0xf4]
283 @ CHECK: vst2.8 {d16, d17}, [r0:64] @ encoding: [0x1f,0x08,0x40,0xf4]
284 @ CHECK: vst2.16 {d16, d17}, [r0:128] @ encoding: [0x6f,0x08,0x40,0xf4]
22
33 .code 16
44
5 @ CHECK: vld1.8 {d16}, [r0, :64] @ encoding: [0x1f,0x07,0x60,0xf9]
5 @ CHECK: vld1.8 {d16}, [r0:64] @ encoding: [0x1f,0x07,0x60,0xf9]
66 vld1.8 {d16}, [r0:64]
77 @ CHECK: vld1.16 {d16}, [r0] @ encoding: [0x4f,0x07,0x60,0xf9]
88 vld1.16 {d16}, [r0]
1010 vld1.32 {d16}, [r0]
1111 @ CHECK: vld1.64 {d16}, [r0] @ encoding: [0xcf,0x07,0x60,0xf9]
1212 vld1.64 {d16}, [r0]
13 @ CHECK: vld1.8 {d16, d17}, [r0, :64] @ encoding: [0x1f,0x0a,0x60,0xf9]
13 @ CHECK: vld1.8 {d16, d17}, [r0:64] @ encoding: [0x1f,0x0a,0x60,0xf9]
1414 vld1.8 {d16, d17}, [r0:64]
15 @ CHECK: vld1.16 {d16, d17}, [r0, :128] @ encoding: [0x6f,0x0a,0x60,0xf9]
15 @ CHECK: vld1.16 {d16, d17}, [r0:128] @ encoding: [0x6f,0x0a,0x60,0xf9]
1616 vld1.16 {d16, d17}, [r0:128]
1717 @ CHECK: vld1.32 {d16, d17}, [r0] @ encoding: [0x8f,0x0a,0x60,0xf9]
1818 vld1.32 {d16, d17}, [r0]
1919 @ CHECK: vld1.64 {d16, d17}, [r0] @ encoding: [0xcf,0x0a,0x60,0xf9]
2020 vld1.64 {d16, d17}, [r0]
2121
22 @ CHECK: vld2.8 {d16, d17}, [r0, :64] @ encoding: [0x1f,0x08,0x60,0xf9]
22 @ CHECK: vld2.8 {d16, d17}, [r0:64] @ encoding: [0x1f,0x08,0x60,0xf9]
2323 vld2.8 {d16, d17}, [r0:64]
24 @ CHECK: vld2.16 {d16, d17}, [r0, :128] @ encoding: [0x6f,0x08,0x60,0xf9]
24 @ CHECK: vld2.16 {d16, d17}, [r0:128] @ encoding: [0x6f,0x08,0x60,0xf9]
2525 vld2.16 {d16, d17}, [r0:128]
2626 @ CHECK: vld2.32 {d16, d17}, [r0] @ encoding: [0x8f,0x08,0x60,0xf9]
2727 vld2.32 {d16, d17}, [r0]
28 @ CHECK: vld2.8 {d16, d17, d18, d19}, [r0, :64] @ encoding: [0x1f,0x03,0x60,0xf9]
28 @ CHECK: vld2.8 {d16, d17, d18, d19}, [r0:64] @ encoding: [0x1f,0x03,0x60,0xf9]
2929 vld2.8 {d16, d17, d18, d19}, [r0:64]
30 @ CHECK: vld2.16 {d16, d17, d18, d19}, [r0, :128] @ encoding: [0x6f,0x03,0x60,0xf9]
30 @ CHECK: vld2.16 {d16, d17, d18, d19}, [r0:128] @ encoding: [0x6f,0x03,0x60,0xf9]
3131 vld2.16 {d16, d17, d18, d19}, [r0:128]
32 @ CHECK: vld2.32 {d16, d17, d18, d19}, [r0, :256] @ encoding: [0xbf,0x03,0x60,0xf9]
32 @ CHECK: vld2.32 {d16, d17, d18, d19}, [r0:256] @ encoding: [0xbf,0x03,0x60,0xf9]
3333 vld2.32 {d16, d17, d18, d19}, [r0:256]
3434
35 @ CHECK: vld3.8 {d16, d17, d18}, [r0, :64] @ encoding: [0x1f,0x04,0x60,0xf9]
35 @ CHECK: vld3.8 {d16, d17, d18}, [r0:64] @ encoding: [0x1f,0x04,0x60,0xf9]
3636 vld3.8 {d16, d17, d18}, [r0:64]
3737 @ CHECK: vld3.16 {d16, d17, d18}, [r0] @ encoding: [0x4f,0x04,0x60,0xf9]
3838 vld3.16 {d16, d17, d18}, [r0]
3939 @ CHECK: vld3.32 {d16, d17, d18}, [r0] @ encoding: [0x8f,0x04,0x60,0xf9]
4040 vld3.32 {d16, d17, d18}, [r0]
41 @ CHECK: vld3.8 {d16, d18, d20}, [r0, :64]! @ encoding: [0x1d,0x05,0x60,0xf9]
41 @ CHECK: vld3.8 {d16, d18, d20}, [r0:64]! @ encoding: [0x1d,0x05,0x60,0xf9]
4242 vld3.8 {d16, d18, d20}, [r0:64]!
43 @ CHECK: vld3.8 {d17, d19, d21}, [r0, :64]! @ encoding: [0x1d,0x15,0x60,0xf9]
43 @ CHECK: vld3.8 {d17, d19, d21}, [r0:64]! @ encoding: [0x1d,0x15,0x60,0xf9]
4444 vld3.8 {d17, d19, d21}, [r0:64]!
4545 @ CHECK: vld3.16 {d16, d18, d20}, [r0]! @ encoding: [0x4d,0x05,0x60,0xf9]
4646 vld3.16 {d16, d18, d20}, [r0]!
5151 @ CHECK: vld3.32 {d17, d19, d21}, [r0]! @ encoding: [0x8d,0x15,0x60,0xf9]
5252 vld3.32 {d17, d19, d21}, [r0]!
5353
54 @ CHECK: vld4.8 {d16, d17, d18, d19}, [r0, :64] @ encoding: [0x1f,0x00,0x60,0xf9]
54 @ CHECK: vld4.8 {d16, d17, d18, d19}, [r0:64] @ encoding: [0x1f,0x00,0x60,0xf9]
5555 vld4.8 {d16, d17, d18, d19}, [r0:64]
56 @ CHECK: vld4.16 {d16, d17, d18, d19}, [r0, :128] @ encoding: [0x6f,0x00,0x60,0xf9]
56 @ CHECK: vld4.16 {d16, d17, d18, d19}, [r0:128] @ encoding: [0x6f,0x00,0x60,0xf9]
5757 vld4.16 {d16, d17, d18, d19}, [r0:128]
58 @ CHECK: vld4.32 {d16, d17, d18, d19}, [r0, :256] @ encoding: [0xbf,0x00,0x60,0xf9]
58 @ CHECK: vld4.32 {d16, d17, d18, d19}, [r0:256] @ encoding: [0xbf,0x00,0x60,0xf9]
5959 vld4.32 {d16, d17, d18, d19}, [r0:256]
60 @ CHECK: vld4.8 {d16, d18, d20, d22}, [r0, :256]! @ encoding: [0x3d,0x01,0x60,0xf9]
60 @ CHECK: vld4.8 {d16, d18, d20, d22}, [r0:256]! @ encoding: [0x3d,0x01,0x60,0xf9]
6161 vld4.8 {d16, d18, d20, d22}, [r0:256]!
62 @ CHECK: vld4.8 {d17, d19, d21, d23}, [r0, :256]! @ encoding: [0x3d,0x11,0x60,0xf9]
62 @ CHECK: vld4.8 {d17, d19, d21, d23}, [r0:256]! @ encoding: [0x3d,0x11,0x60,0xf9]
6363 vld4.8 {d17, d19, d21, d23}, [r0:256]!
6464 @ CHECK: vld4.16 {d16, d18, d20, d22}, [r0]! @ encoding: [0x4d,0x01,0x60,0xf9]
6565 vld4.16 {d16, d18, d20, d22}, [r0]!
7272
7373 @ CHECK: vld1.8 {d16[3]}, [r0] @ encoding: [0x6f,0x00,0xe0,0xf9]
7474 vld1.8 {d16[3]}, [r0]
75 @ CHECK: vld1.16 {d16[2]}, [r0, :16] @ encoding: [0x9f,0x04,0xe0,0xf9]
75 @ CHECK: vld1.16 {d16[2]}, [r0:16] @ encoding: [0x9f,0x04,0xe0,0xf9]
7676 vld1.16 {d16[2]}, [r0:16]
77 @ CHECK: vld1.32 {d16[1]}, [r0, :32] @ encoding: [0xbf,0x08,0xe0,0xf9]
77 @ CHECK: vld1.32 {d16[1]}, [r0:32] @ encoding: [0xbf,0x08,0xe0,0xf9]
7878 vld1.32 {d16[1]}, [r0:32]
7979
80 @ CHECK: vld2.8 {d16[1], d17[1]}, [r0, :16] @ encoding: [0x3f,0x01,0xe0,0xf9]
80 @ CHECK: vld2.8 {d16[1], d17[1]}, [r0:16] @ encoding: [0x3f,0x01,0xe0,0xf9]
8181 vld2.8 {d16[1], d17[1]}, [r0:16]
82 @ CHECK: vld2.16 {d16[1], d17[1]}, [r0, :32] @ encoding: [0x5f,0x05,0xe0,0xf9]
82 @ CHECK: vld2.16 {d16[1], d17[1]}, [r0:32] @ encoding: [0x5f,0x05,0xe0,0xf9]
8383 vld2.16 {d16[1], d17[1]}, [r0:32]
8484 @ CHECK: vld2.32 {d16[1], d17[1]}, [r0] @ encoding: [0x8f,0x09,0xe0,0xf9]
8585 vld2.32 {d16[1], d17[1]}, [r0]
8686 @ CHECK: vld2.16 {d17[1], d19[1]}, [r0] @ encoding: [0x6f,0x15,0xe0,0xf9]
8787 vld2.16 {d17[1], d19[1]}, [r0]
88 @ CHECK: vld2.32 {d17[0], d19[0]}, [r0, :64] @ encoding: [0x5f,0x19,0xe0,0xf9]
88 @ CHECK: vld2.32 {d17[0], d19[0]}, [r0:64] @ encoding: [0x5f,0x19,0xe0,0xf9]
8989 vld2.32 {d17[0], d19[0]}, [r0:64]
9090
9191 @ CHECK: vld3.8 {d16[1], d17[1], d18[1]}, [r0] @ encoding: [0x2f,0x02,0xe0,0xf9]
9999 @ CHECK: vld3.32 {d17[1], d19[1], d21[1]}, [r0] @ encoding: [0xcf,0x1a,0xe0,0xf9]
100100 vld3.32 {d17[1], d19[1], d21[1]}, [r0]
101101
102 @ CHECK: vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0, :32] @ encoding: [0x3f,0x03,0xe0,0xf9]
102 @ CHECK: vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0:32] @ encoding: [0x3f,0x03,0xe0,0xf9]
103103 vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0:32]
104104 @ CHECK: vld4.16 {d16[1], d17[1], d18[1], d19[1]}, [r0] @ encoding: [0x4f,0x07,0xe0,0xf9]
105105 vld4.16 {d16[1], d17[1], d18[1], d19[1]}, [r0]
106 @ CHECK: vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0, :128] @ encoding: [0xaf,0x0b,0xe0,0xf9]
106 @ CHECK: vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0:128] @ encoding: [0xaf,0x0b,0xe0,0xf9]
107107 vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0:128]
108 @ CHECK: vld4.16 {d16[1], d18[1], d20[1], d22[1]}, [r0, :64] @ encoding: [0x7f,0x07,0xe0,0xf9]
108 @ CHECK: vld4.16 {d16[1], d18[1], d20[1], d22[1]}, [r0:64] @ encoding: [0x7f,0x07,0xe0,0xf9]
109109 vld4.16 {d16[1], d18[1], d20[1], d22[1]}, [r0:64]
110110 @ CHECK: vld4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0] @ encoding: [0x4f,0x1b,0xe0,0xf9]
111111 vld4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0]
22
33 .code 16
44
5 @ CHECK: vst1.8 {d16}, [r0, :64] @ encoding: [0x1f,0x07,0x40,0xf9]
5 @ CHECK: vst1.8 {d16}, [r0:64] @ encoding: [0x1f,0x07,0x40,0xf9]
66 vst1.8 {d16}, [r0:64]
77 @ CHECK: vst1.16 {d16}, [r0] @ encoding: [0x4f,0x07,0x40,0xf9]
88 vst1.16 {d16}, [r0]
1010 vst1.32 {d16}, [r0]
1111 @ CHECK: vst1.64 {d16}, [r0] @ encoding: [0xcf,0x07,0x40,0xf9]
1212 vst1.64 {d16}, [r0]
13 @ CHECK: vst1.8 {d16, d17}, [r0, :64] @ encoding: [0x1f,0x0a,0x40,0xf9]
13 @ CHECK: vst1.8 {d16, d17}, [r0:64] @ encoding: [0x1f,0x0a,0x40,0xf9]
1414 vst1.8 {d16, d17}, [r0:64]
15 @ CHECK: vst1.16 {d16, d17}, [r0, :128] @ encoding: [0x6f,0x0a,0x40,0xf9]
15 @ CHECK: vst1.16 {d16, d17}, [r0:128] @ encoding: [0x6f,0x0a,0x40,0xf9]
1616 vst1.16 {d16, d17}, [r0:128]
1717 @ CHECK: vst1.32 {d16, d17}, [r0] @ encoding: [0x8f,0x0a,0x40,0xf9]
1818 vst1.32 {d16, d17}, [r0]
1919 @ CHECK: vst1.64 {d16, d17}, [r0] @ encoding: [0xcf,0x0a,0x40,0xf9]
2020 vst1.64 {d16, d17}, [r0]
2121
22 @ CHECK: vst2.8 {d16, d17}, [r0, :64] @ encoding: [0x1f,0x08,0x40,0xf9]
22 @ CHECK: vst2.8 {d16, d17}, [r0:64] @ encoding: [0x1f,0x08,0x40,0xf9]
2323 vst2.8 {d16, d17}, [r0:64]
24 @ CHECK: vst2.16 {d16, d17}, [r0, :128] @ encoding: [0x6f,0x08,0x40,0xf9]
24 @ CHECK: vst2.16 {d16, d17}, [r0:128] @ encoding: [0x6f,0x08,0x40,0xf9]
2525 vst2.16 {d16, d17}, [r0:128]
2626 @ CHECK: vst2.32 {d16, d17}, [r0] @ encoding: [0x8f,0x08,0x40,0xf9]
2727 vst2.32 {d16, d17}, [r0]
28 @ CHECK: vst2.8 {d16, d17, d18, d19}, [r0, :64] @ encoding: [0x1f,0x03,0x40,0xf9]
28 @ CHECK: vst2.8 {d16, d17, d18, d19}, [r0:64] @ encoding: [0x1f,0x03,0x40,0xf9]
2929 vst2.8 {d16, d17, d18, d19}, [r0:64]
30 @ CHECK: vst2.16 {d16, d17, d18, d19}, [r0, :128] @ encoding: [0x6f,0x03,0x40,0xf9]
30 @ CHECK: vst2.16 {d16, d17, d18, d19}, [r0:128] @ encoding: [0x6f,0x03,0x40,0xf9]
3131 vst2.16 {d16, d17, d18, d19}, [r0:128]
32 @ CHECK: vst2.32 {d16, d17, d18, d19}, [r0, :256] @ encoding: [0xbf,0x03,0x40,0xf9]
32 @ CHECK: vst2.32 {d16, d17, d18, d19}, [r0:256] @ encoding: [0xbf,0x03,0x40,0xf9]
3333 vst2.32 {d16, d17, d18, d19}, [r0:256]
3434
35 @ CHECK: vst3.8 {d16, d17, d18}, [r0, :64] @ encoding: [0x1f,0x04,0x40,0xf9]
35 @ CHECK: vst3.8 {d16, d17, d18}, [r0:64] @ encoding: [0x1f,0x04,0x40,0xf9]
3636 vst3.8 {d16, d17, d18}, [r0:64]
3737 @ CHECK: vst3.16 {d16, d17, d18}, [r0] @ encoding: [0x4f,0x04,0x40,0xf9]
3838 vst3.16 {d16, d17, d18}, [r0]
3939 @ CHECK: vst3.32 {d16, d17, d18}, [r0] @ encoding: [0x8f,0x04,0x40,0xf9]
4040 vst3.32 {d16, d17, d18}, [r0]
41 @ CHECK: vst3.8 {d16, d18, d20}, [r0, :64]! @ encoding: [0x1d,0x05,0x40,0xf9]
41 @ CHECK: vst3.8 {d16, d18, d20}, [r0:64]! @ encoding: [0x1d,0x05,0x40,0xf9]
4242 vst3.8 {d16, d18, d20}, [r0:64]!
43 @ CHECK: vst3.8 {d17, d19, d21}, [r0, :64]! @ encoding: [0x1d,0x15,0x40,0xf9]
43 @ CHECK: vst3.8 {d17, d19, d21}, [r0:64]! @ encoding: [0x1d,0x15,0x40,0xf9]
4444 vst3.8 {d17, d19, d21}, [r0:64]!
4545 @ CHECK: vst3.16 {d16, d18, d20}, [r0]! @ encoding: [0x4d,0x05,0x40,0xf9]
4646 vst3.16 {d16, d18, d20}, [r0]!
5151 @ CHECK: vst3.32 {d17, d19, d21}, [r0]! @ encoding: [0x8d,0x15,0x40,0xf9]
5252 vst3.32 {d17, d19, d21}, [r0]!
5353
54 @ CHECK: vst4.8 {d16, d17, d18, d19}, [r0, :64] @ encoding: [0x1f,0x00,0x40,0xf9]
54 @ CHECK: vst4.8 {d16, d17, d18, d19}, [r0:64] @ encoding: [0x1f,0x00,0x40,0xf9]
5555 vst4.8 {d16, d17, d18, d19}, [r0:64]
56 @ CHECK: vst4.16 {d16, d17, d18, d19}, [r0, :128] @ encoding: [0x6f,0x00,0x40,0xf9]
56 @ CHECK: vst4.16 {d16, d17, d18, d19}, [r0:128] @ encoding: [0x6f,0x00,0x40,0xf9]
5757 vst4.16 {d16, d17, d18, d19}, [r0:128]
58 @ CHECK: vst4.8 {d16, d18, d20, d22}, [r0, :256]! @ encoding: [0x3d,0x01,0x40,0xf9]
58 @ CHECK: vst4.8 {d16, d18, d20, d22}, [r0:256]! @ encoding: [0x3d,0x01,0x40,0xf9]
5959 vst4.8 {d16, d18, d20, d22}, [r0:256]!
60 @ CHECK: vst4.8 {d17, d19, d21, d23}, [r0, :256]! @ encoding: [0x3d,0x11,0x40,0xf9]
60 @ CHECK: vst4.8 {d17, d19, d21, d23}, [r0:256]! @ encoding: [0x3d,0x11,0x40,0xf9]
6161 vst4.8 {d17, d19, d21, d23}, [r0:256]!
6262 @ CHECK: vst4.16 {d16, d18, d20, d22}, [r0]! @ encoding: [0x4d,0x01,0x40,0xf9]
6363 vst4.16 {d16, d18, d20, d22}, [r0]!
6868 @ CHECK: vst4.32 {d17, d19, d21, d23}, [r0]! @ encoding: [0x8d,0x11,0x40,0xf9]
6969 vst4.32 {d17, d19, d21, d23}, [r0]!
7070
71 @ CHECK: vst2.8 {d16[1], d17[1]}, [r0, :16] @ encoding: [0x3f,0x01,0xc0,0xf9]
71 @ CHECK: vst2.8 {d16[1], d17[1]}, [r0:16] @ encoding: [0x3f,0x01,0xc0,0xf9]
7272 vst2.8 {d16[1], d17[1]}, [r0:16]
73 @ CHECK: vst2.16 {d16[1], d17[1]}, [r0, :32] @ encoding: [0x5f,0x05,0xc0,0xf9]
73 @ CHECK: vst2.16 {d16[1], d17[1]}, [r0:32] @ encoding: [0x5f,0x05,0xc0,0xf9]
7474 vst2.16 {d16[1], d17[1]}, [r0:32]
7575 @ CHECK: vst2.32 {d16[1], d17[1]}, [r0] @ encoding: [0x8f,0x09,0xc0,0xf9]
7676 vst2.32 {d16[1], d17[1]}, [r0]
7777 @ CHECK: vst2.16 {d17[1], d19[1]}, [r0] @ encoding: [0x6f,0x15,0xc0,0xf9]
7878 vst2.16 {d17[1], d19[1]}, [r0]
79 @ CHECK: vst2.32 {d17[0], d19[0]}, [r0, :64] @ encoding: [0x5f,0x19,0xc0,0xf9]
79 @ CHECK: vst2.32 {d17[0], d19[0]}, [r0:64] @ encoding: [0x5f,0x19,0xc0,0xf9]
8080 vst2.32 {d17[0], d19[0]}, [r0:64]
8181
8282 @ CHECK: vst3.8 {d16[1], d17[1], d18[1]}, [r0] @ encoding: [0x2f,0x02,0xc0,0xf9]
9090 @ CHECK: vst3.32 {d16[0], d18[0], d20[0]}, [r0] @ encoding: [0x4f,0x0a,0xc0,0xf9]
9191 vst3.32 {d16[0], d18[0], d20[0]}, [r0]
9292
93 @ CHECK: vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0, :32] @ encoding: [0x3f,0x03,0xc0,0xf9]
93 @ CHECK: vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0:32] @ encoding: [0x3f,0x03,0xc0,0xf9]
9494 vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0:32]
9595 @ CHECK: vst4.16 {d16[1], d17[1], d18[1], d19[1]}, [r0] @ encoding: [0x4f,0x07,0xc0,0xf9]
9696 vst4.16 {d16[1], d17[1], d18[1], d19[1]}, [r0]
97 @ CHECK: vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0, :128] @ encoding: [0xaf,0x0b,0xc0,0xf9]
97 @ CHECK: vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0:128] @ encoding: [0xaf,0x0b,0xc0,0xf9]
9898 vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0:128]
99 @ CHECK: vst4.16 {d17[3], d19[3], d21[3], d23[3]}, [r0, :64] @ encoding: [0xff,0x17,0xc0,0xf9]
99 @ CHECK: vst4.16 {d17[3], d19[3], d21[3], d23[3]}, [r0:64] @ encoding: [0xff,0x17,0xc0,0xf9]
100100 vst4.16 {d17[3], d19[3], d21[3], d23[3]}, [r0:64]
101101 @ CHECK: vst4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0] @ encoding: [0x4f,0x1b,0xc0,0xf9]
102102 vst4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0]
2020 # CHECK: vld4.8 {d4, d6, d8, d10}, [r2]
2121 0x0f 0x41 0x22 0xf4
2222
23 # CHECK: vld1.32 {d3[], d4[]}, [r0, :32]!
23 # CHECK: vld1.32 {d3[], d4[]}, [r0:32]!
2424 0xbd 0x3c 0xa0 0xf4
2525
26 # CHECK: vld4.16 {d3[], d5[], d7[], d9[]}, [r0, :64]!
26 # CHECK: vld4.16 {d3[], d5[], d7[], d9[]}, [r0:64]!
2727 0x7d 0x3f 0xa0 0xf4
2828
2929 # CHECK: vorr d0, d15, d15
7474 # CHECK: vbic.i32 q2, #0xa900
7575 0x79 0x43 0x82 0xf3
7676
77 # CHECK: vst2.32 {d16, d18}, [r2, :64], r2
77 # CHECK: vst2.32 {d16, d18}, [r2:64], r2
7878 0x92 0x9 0x42 0xf4
7979
8080 # CHECK: vmov.s8 r0, d8[1]
16371637
16381638
16391639 0x1f 0x07 0x60 0xf4
1640 # CHECK: vld1.8 {d16}, [r0, :64]
1640 # CHECK: vld1.8 {d16}, [r0:64]
16411641 0x4f 0x07 0x60 0xf4
16421642 # CHECK: vld1.16 {d16}, [r0]
16431643 0x8f 0x07 0x60 0xf4
16451645 0xcf 0x07 0x60 0xf4
16461646 # CHECK: vld1.64 {d16}, [r0]
16471647 0x1f 0x0a 0x60 0xf4
1648 # CHECK: vld1.8 {d16, d17}, [r0, :64]
1648 # CHECK: vld1.8 {d16, d17}, [r0:64]
16491649 0x6f 0x0a 0x60 0xf4
1650 # CHECK: vld1.16 {d16, d17}, [r0, :128]
1650 # CHECK: vld1.16 {d16, d17}, [r0:128]
16511651 0x8f 0x0a 0x60 0xf4
16521652 # CHECK: vld1.32 {d16, d17}, [r0]
16531653 0xcf 0x0a 0x60 0xf4
16541654 # CHECK: vld1.64 {d16, d17}, [r0]
16551655
16561656 0x1f 0x08 0x60 0xf4
1657 # CHECK: vld2.8 {d16, d17}, [r0, :64]
1657 # CHECK: vld2.8 {d16, d17}, [r0:64]
16581658 0x6f 0x08 0x60 0xf4
1659 # CHECK: vld2.16 {d16, d17}, [r0, :128]
1659 # CHECK: vld2.16 {d16, d17}, [r0:128]
16601660 0x8f 0x08 0x60 0xf4
16611661 # CHECK: vld2.32 {d16, d17}, [r0]
16621662 0x1f 0x03 0x60 0xf4
1663 # CHECK: vld2.8 {d16, d17, d18, d19}, [r0, :64]
1663 # CHECK: vld2.8 {d16, d17, d18, d19}, [r0:64]
16641664 0x6f 0x03 0x60 0xf4
1665 # CHECK: vld2.16 {d16, d17, d18, d19}, [r0, :128]
1665 # CHECK: vld2.16 {d16, d17, d18, d19}, [r0:128]
16661666 0xbf 0x03 0x60 0xf4
1667 # CHECK: vld2.32 {d16, d17, d18, d19}, [r0, :256]
1667 # CHECK: vld2.32 {d16, d17, d18, d19}, [r0:256]
16681668
16691669 0x1f 0x04 0x60 0xf4
1670 # CHECK: vld3.8 {d16, d17, d18}, [r0, :64]
1670 # CHECK: vld3.8 {d16, d17, d18}, [r0:64]
16711671 0x4f 0x04 0x60 0xf4
16721672 # CHECK: vld3.16 {d16, d17, d18}, [r0]
16731673 0x8f 0x04 0x60 0xf4
16741674 # CHECK: vld3.32 {d16, d17, d18}, [r0]
16751675 0x1d 0x05 0x60 0xf4
1676 # CHECK: vld3.8 {d16, d18, d20}, [r0, :64]!
1676 # CHECK: vld3.8 {d16, d18, d20}, [r0:64]!
16771677 0x1d 0x15 0x60 0xf4
1678 # CHECK: vld3.8 {d17, d19, d21}, [r0, :64]!
1678 # CHECK: vld3.8 {d17, d19, d21}, [r0:64]!
16791679 0x4d 0x05 0x60 0xf4
16801680 # CHECK: vld3.16 {d16, d18, d20}, [r0]!
16811681 0x4d 0x15 0x60 0xf4
16861686 # CHECK: vld3.32 {d17, d19, d21}, [r0]!
16871687
16881688 0x1f 0x00 0x60 0xf4
1689 # CHECK: vld4.8 {d16, d17, d18, d19}, [r0, :64]
1689 # CHECK: vld4.8 {d16, d17, d18, d19}, [r0:64]
16901690 0x6f 0x00 0x60 0xf4
1691 # CHECK: vld4.16 {d16, d17, d18, d19}, [r0, :128]
1691 # CHECK: vld4.16 {d16, d17, d18, d19}, [r0:128]
16921692 0xbf 0x00 0x60 0xf4
1693 # CHECK: vld4.32 {d16, d17, d18, d19}, [r0, :256]
1693 # CHECK: vld4.32 {d16, d17, d18, d19}, [r0:256]
16941694 0x3d 0x01 0x60 0xf4
1695 # CHECK: vld4.8 {d16, d18, d20, d22}, [r0, :256]!
1695 # CHECK: vld4.8 {d16, d18, d20, d22}, [r0:256]!
16961696 0x3d 0x11 0x60 0xf4
1697 # CHECK: vld4.8 {d17, d19, d21, d23}, [r0, :256]!
1697 # CHECK: vld4.8 {d17, d19, d21, d23}, [r0:256]!
16981698 0x4d 0x01 0x60 0xf4
16991699 # CHECK: vld4.16 {d16, d18, d20, d22}, [r0]!
17001700 0x4d 0x11 0x60 0xf4
17071707 0x6f 0x00 0xe0 0xf4
17081708 # CHECK: vld1.8 {d16[3]}, [r0]
17091709 0x9f 0x04 0xe0 0xf4
1710 # CHECK: vld1.16 {d16[2]}, [r0, :16]
1710 # CHECK: vld1.16 {d16[2]}, [r0:16]
17111711 0xbf 0x08 0xe0 0xf4
1712 # CHECK: vld1.32 {d16[1]}, [r0, :32]
1712 # CHECK: vld1.32 {d16[1]}, [r0:32]
17131713
17141714 0x3f 0x01 0xe0 0xf4
1715 # CHECK: vld2.8 {d16[1], d17[1]}, [r0, :16]
1715 # CHECK: vld2.8 {d16[1], d17[1]}, [r0:16]
17161716 0x5f 0x05 0xe0 0xf4
1717 # CHECK: vld2.16 {d16[1], d17[1]}, [r0, :32]
1717 # CHECK: vld2.16 {d16[1], d17[1]}, [r0:32]
17181718 0x8f 0x09 0xe0 0xf4
17191719 # CHECK: vld2.32 {d16[1], d17[1]}, [r0]
17201720 0x6f 0x15 0xe0 0xf4
17211721 # CHECK: vld2.16 {d17[1], d19[1]}, [r0]
17221722 0x5f 0x19 0xe0 0xf4
1723 # CHECK: vld2.32 {d17[0], d19[0]}, [r0, :64]
1723 # CHECK: vld2.32 {d17[0], d19[0]}, [r0:64]
17241724
17251725 0x2f 0x02 0xe0 0xf4
17261726 # CHECK: vld3.8 {d16[1], d17[1], d18[1]}, [r0]
17531753 0xa5 0x0e 0xa4 0xf4
17541754
17551755 0x3f 0x03 0xe0 0xf4
1756 # CHECK: vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0, :32]
1756 # CHECK: vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0:32]
17571757 0x4f 0x07 0xe0 0xf4
17581758 # CHECK: vld4.16 {d16[1], d17[1], d18[1], d19[1]}, [r0]
17591759 0xaf 0x0b 0xe0 0xf4
1760 # CHECK: vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0, :128]
1760 # CHECK: vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0:128]
17611761 0x7f 0x07 0xe0 0xf4
1762 # CHECK: vld4.16 {d16[1], d18[1], d20[1], d22[1]}, [r0, :64]
1762 # CHECK: vld4.16 {d16[1], d18[1], d20[1], d22[1]}, [r0:64]
17631763 0x4f 0x1b 0xe0 0xf4
17641764 # CHECK: vld4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0]
17651765
17661766 0x0f 0x0f 0xa4 0xf4
17671767 # CHECK: vld4.8 {d0[], d1[], d2[], d3[]}, [r4]
17681768 0x3f 0x0f 0xa4 0xf4
1769 # CHECK: vld4.8 {d0[], d2[], d4[], d6[]}, [r4, :32]
1769 # CHECK: vld4.8 {d0[], d2[], d4[], d6[]}, [r4:32]
17701770 0x1d 0x0f 0xa4 0xf4
1771 # CHECK: vld4.8 {d0[], d1[], d2[], d3[]}, [r4, :32]!
1771 # CHECK: vld4.8 {d0[], d1[], d2[], d3[]}, [r4:32]!
17721772 0x35 0x0f 0xa4 0xf4
1773 # CHECK: vld4.8 {d0[], d2[], d4[], d6[]}, [r4, :32], r5
1773 # CHECK: vld4.8 {d0[], d2[], d4[], d6[]}, [r4:32], r5
17741774 0x4f 0x0f 0xa4 0xf4
17751775 # CHECK: vld4.16 {d0[], d1[], d2[], d3[]}, [r4]
17761776 0x7f 0x0f 0xa4 0xf4
1777 # CHECK: vld4.16 {d0[], d2[], d4[], d6[]}, [r4, :64]
1777 # CHECK: vld4.16 {d0[], d2[], d4[], d6[]}, [r4:64]
17781778 0x5d 0x0f 0xa4 0xf4
1779 # CHECK: vld4.16 {d0[], d1[], d2[], d3[]}, [r4, :64]!
1779 # CHECK: vld4.16 {d0[], d1[], d2[], d3[]}, [r4:64]!
17801780 0x75 0x0f 0xa4 0xf4
1781 # CHECK: vld4.16 {d0[], d2[], d4[], d6[]}, [r4, :64], r5
1781 # CHECK: vld4.16 {d0[], d2[], d4[], d6[]}, [r4:64], r5
17821782 0x8f 0x0f 0xa4 0xf4
17831783 # CHECK: vld4.32 {d0[], d1[], d2[], d3[]}, [r4]
17841784 0xbf 0x0f 0xa4 0xf4
1785 # CHECK: vld4.32 {d0[], d2[], d4[], d6[]}, [r4, :64]
1785 # CHECK: vld4.32 {d0[], d2[], d4[], d6[]}, [r4:64]
17861786 0xdd 0x0f 0xa4 0xf4
1787 # CHECK: vld4.32 {d0[], d1[], d2[], d3[]}, [r4, :128]!
1787 # CHECK: vld4.32 {d0[], d1[], d2[], d3[]}, [r4:128]!
17881788 0xf5 0x0f 0xa4 0xf4
1789 # CHECK: vld4.32 {d0[], d2[], d4[], d6[]}, [r4, :128], r5
1789 # CHECK: vld4.32 {d0[], d2[], d4[], d6[]}, [r4:128], r5
17901790
17911791
17921792 0x1f 0x07 0x40 0xf4
1793 # CHECK: vst1.8 {d16}, [r0, :64]
1793 # CHECK: vst1.8 {d16}, [r0:64]
17941794 0x4f 0x07 0x40 0xf4
17951795 # CHECK: vst1.16 {d16}, [r0]
17961796 0x8f 0x07 0x40 0xf4
17981798 0xcf 0x07 0x40 0xf4
17991799 # CHECK: vst1.64 {d16}, [r0]
18001800 0x1f 0x0a 0x40 0xf4
1801 # CHECK: vst1.8 {d16, d17}, [r0, :64]
1801 # CHECK: vst1.8 {d16, d17}, [r0:64]
18021802 0x6f 0x0a 0x40 0xf4
1803 # CHECK: vst1.16 {d16, d17}, [r0, :128]
1803 # CHECK: vst1.16 {d16, d17}, [r0:128]
18041804 0x8f 0x0a 0x40 0xf4
18051805 # CHECK: vst1.32 {d16, d17}, [r0]
18061806 0xcf 0x0a 0x40 0xf4
18071807 # CHECK: vst1.64 {d16, d17}, [r0]
18081808
18091809 0x1f 0x08 0x40 0xf4
1810 # CHECK: vst2.8 {d16, d17}, [r0, :64]
1810 # CHECK: vst2.8 {d16, d17}, [r0:64]
18111811 0x6f 0x08 0x40 0xf4
1812 # CHECK: vst2.16 {d16, d17}, [r0, :128]
1812 # CHECK: vst2.16 {d16, d17}, [r0:128]
18131813 0x8f 0x08 0x40 0xf4
18141814 # CHECK: vst2.32 {d16, d17}, [r0]
18151815 0x1f 0x03 0x40 0xf4
1816 # CHECK: vst2.8 {d16, d17, d18, d19}, [r0, :64]
1816 # CHECK: vst2.8 {d16, d17, d18, d19}, [r0:64]
18171817 0x6f 0x03 0x40 0xf4
1818 # CHECK: vst2.16 {d16, d17, d18, d19}, [r0, :128]
1818 # CHECK: vst2.16 {d16, d17, d18, d19}, [r0:128]
18191819 0xbf 0x03 0x40 0xf4
1820 # CHECK: vst2.32 {d16, d17, d18, d19}, [r0, :256]
1820 # CHECK: vst2.32 {d16, d17, d18, d19}, [r0:256]
18211821
18221822 0x1f 0x04 0x40 0xf4
1823 # CHECK: vst3.8 {d16, d17, d18}, [r0, :64]
1823 # CHECK: vst3.8 {d16, d17, d18}, [r0:64]
18241824 0x4f 0x04 0x40 0xf4
18251825 # CHECK: vst3.16 {d16, d17, d18}, [r0]
18261826 0x8f 0x04 0x40 0xf4
18271827 # CHECK: vst3.32 {d16, d17, d18}, [r0]
18281828 0x1d 0x05 0x40 0xf4
1829 # CHECK: vst3.8 {d16, d18, d20}, [r0, :64]!
1829 # CHECK: vst3.8 {d16, d18, d20}, [r0:64]!
18301830 0x1d 0x15 0x40 0xf4
1831 # CHECK: vst3.8 {d17, d19, d21}, [r0, :64]!
1831 # CHECK: vst3.8 {d17, d19, d21}, [r0:64]!
18321832 0x4d 0x05 0x40 0xf4
18331833 # CHECK: vst3.16 {d16, d18, d20}, [r0]!
18341834 0x4d 0x15 0x40 0xf4
18391839 # CHECK: vst3.32 {d17, d19, d21}, [r0]!
18401840
18411841 0x1f 0x00 0x40 0xf4
1842 # CHECK: vst4.8 {d16, d17, d18, d19}, [r0, :64]
1842 # CHECK: vst4.8 {d16, d17, d18, d19}, [r0:64]
18431843 0x6f 0x00 0x40 0xf4
1844 # CHECK: vst4.16 {d16, d17, d18, d19}, [r0, :128]
1844 # CHECK: vst4.16 {d16, d17, d18, d19}, [r0:128]
18451845 0x3d 0x01 0x40 0xf4
1846 # CHECK: vst4.8 {d16, d18, d20, d22}, [r0, :256]!
1846 # CHECK: vst4.8 {d16, d18, d20, d22}, [r0:256]!
18471847 0x3d 0x11 0x40 0xf4
1848 # CHECK: vst4.8 {d17, d19, d21, d23}, [r0, :256]!
1848 # CHECK: vst4.8 {d17, d19, d21, d23}, [r0:256]!
18491849 0x4d 0x01 0x40 0xf4
18501850 # CHECK: vst4.16 {d16, d18, d20, d22}, [r0]!
18511851 0x4d 0x11 0x40 0xf4
18561856 # CHECK: vst4.32 {d17, d19, d21, d23}, [r0]!
18571857
18581858 0x3f 0x01 0xc0 0xf4
1859 # CHECK: vst2.8 {d16[1], d17[1]}, [r0, :16]
1859 # CHECK: vst2.8 {d16[1], d17[1]}, [r0:16]
18601860 0x5f 0x05 0xc0 0xf4
1861 # CHECK: vst2.16 {d16[1], d17[1]}, [r0, :32]
1861 # CHECK: vst2.16 {d16[1], d17[1]}, [r0:32]
18621862 0x8f 0x09 0xc0 0xf4
18631863 # CHECK: vst2.32 {d16[1], d17[1]}, [r0]
18641864 0x6f 0x15 0xc0 0xf4
18651865 # CHECK: vst2.16 {d17[1], d19[1]}, [r0]
18661866 0x5f 0x19 0xc0 0xf4
1867 # CHECK: vst2.32 {d17[0], d19[0]}, [r0, :64]
1867 # CHECK: vst2.32 {d17[0], d19[0]}, [r0:64]
18681868
18691869 0x2f 0x02 0xc0 0xf4
18701870 # CHECK: vst3.8 {d16[1], d17[1], d18[1]}, [r0]
18781878 # CHECK: vst3.32 {d16[0], d18[0], d20[0]}, [r0]
18791879
18801880 0x3f 0x03 0xc0 0xf4
1881 # CHECK: vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0, :32]
1881 # CHECK: vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0:32]
18821882 0x4f 0x07 0xc0 0xf4
18831883 # CHECK: vst4.16 {d16[1], d17[1], d18[1], d19[1]}, [r0]
18841884 0xaf 0x0b 0xc0 0xf4
1885 # CHECK: vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0, :128]
1885 # CHECK: vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0:128]
18861886 0xff 0x17 0xc0 0xf4
1887 # CHECK: vst4.16 {d17[3], d19[3], d21[3], d23[3]}, [r0, :64]
1887 # CHECK: vst4.16 {d17[3], d19[3], d21[3], d23[3]}, [r0:64]
18881888 0x4f 0x1b 0xc0 0xf4
18891889 # CHECK: vst4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0]
18901890
19191919 # CHECK: vcvttmi.f32.f16 s2, s19
19201920
19211921 0x1d 0x76 0x66 0xf4
1922 # CHECK: vld1.8 {d23, d24, d25}, [r6, :64]!
1922 # CHECK: vld1.8 {d23, d24, d25}, [r6:64]!
19231923 0x9d 0x62 0x6f 0xf4
1924 # CHECK: vld1.32 {d22, d23, d24, d25}, [pc, :64]!
1924 # CHECK: vld1.32 {d22, d23, d24, d25}, [pc:64]!
19251925 0x9d 0xaa 0x41 0xf4
1926 # CHECK: vst1.32 {d26, d27}, [r1, :64]!
1926 # CHECK: vst1.32 {d26, d27}, [r1:64]!
19271927
19281928 0x10 0x0f 0x83 0xf2
19291929 0x50 0x0f 0x83 0xf2
2727 0xa0 0xf9 0xd0 0x04
2828
2929 # CHECK: vld1.16 {d0[0]}, [r0], r0 @ encoding: [0xa0,0xf9,0x00,0x04]
30 # CHECK: vld1.16 {d0[0]}, [r0, :16], r0 @ encoding: [0xa0,0xf9,0x10,0x04]
30 # CHECK: vld1.16 {d0[0]}, [r0:16], r0 @ encoding: [0xa0,0xf9,0x10,0x04]
3131 # CHECK: vld1.16 {d0[1]}, [r0], r0 @ encoding: [0xa0,0xf9,0x40,0x04]
32 # CHECK: vld1.16 {d0[1]}, [r0, :16], r0 @ encoding: [0xa0,0xf9,0x50,0x04]
32 # CHECK: vld1.16 {d0[1]}, [r0:16], r0 @ encoding: [0xa0,0xf9,0x50,0x04]
3333 # CHECK: vld1.16 {d0[2]}, [r0], r0 @ encoding: [0xa0,0xf9,0x80,0x04]
34 # CHECK: vld1.16 {d0[2]}, [r0, :16], r0 @ encoding: [0xa0,0xf9,0x90,0x04]
34 # CHECK: vld1.16 {d0[2]}, [r0:16], r0 @ encoding: [0xa0,0xf9,0x90,0x04]
3535 # CHECK: vld1.16 {d0[3]}, [r0], r0 @ encoding: [0xa0,0xf9,0xc0,0x04]
36 # CHECK: vld1.16 {d0[3]}, [r0, :16], r0 @ encoding: [0xa0,0xf9,0xd0,0x04]
36 # CHECK: vld1.16 {d0[3]}, [r0:16], r0 @ encoding: [0xa0,0xf9,0xd0,0x04]
3737
3838 0xa0 0xf9 0x00 0x08
3939 0xa0 0xf9 0x30 0x08
4141 0xa0 0xf9 0xb0 0x08
4242
4343 # CHECK: vld1.32 {d0[0]}, [r0], r0 @ encoding: [0xa0,0xf9,0x00,0x08]
44 # CHECK: vld1.32 {d0[0]}, [r0, :32], r0 @ encoding: [0xa0,0xf9,0x30,0x08]
44 # CHECK: vld1.32 {d0[0]}, [r0:32], r0 @ encoding: [0xa0,0xf9,0x30,0x08]
4545 # CHECK: vld1.32 {d0[1]}, [r0], r0 @ encoding: [0xa0,0xf9,0x80,0x08]
46 # CHECK: vld1.32 {d0[1]}, [r0, :32], r0 @ encoding: [0xa0,0xf9,0xb0,0x08]
46 # CHECK: vld1.32 {d0[1]}, [r0:32], r0 @ encoding: [0xa0,0xf9,0xb0,0x08]
4747
4848 0xa0 0xf9 0x1f 0x04
4949 0xa0 0xf9 0x8f 0x00
5050
51 # CHECK: vld1.16 {d0[0]}, [r0, :16] @ encoding: [0xa0,0xf9,0x1f,0x04]
51 # CHECK: vld1.16 {d0[0]}, [r0:16] @ encoding: [0xa0,0xf9,0x1f,0x04]
5252 # CHECK: vld1.8 {d0[4]}, [r0] @ encoding: [0xa0,0xf9,0x8f,0x00]
5353
5454 0xa0 0xf9 0x1d 0x04
5555 0xa0 0xf9 0x8d 0x00
5656
57 # CHECK: vld1.16 {d0[0]}, [r0, :16]! @ encoding: [0xa0,0xf9,0x1d,0x04]
57 # CHECK: vld1.16 {d0[0]}, [r0:16]! @ encoding: [0xa0,0xf9,0x1d,0x04]
5858 # CHECK: vld1.8 {d0[4]}, [r0]! @ encoding: [0xa0,0xf9,0x8d,0x00]
5959
6060 0xa5 0xf9 0x10 0x04
6262 0xae 0xf9 0x1a 0x04
6363 0xa5 0xf9 0x1a 0x94
6464
65 # CHECK: vld1.16 {d0[0]}, [r5, :16], r0 @ encoding: [0xa5,0xf9,0x10,0x04]
66 # CHECK: vld1.16 {d0[0]}, [r5, :16], r10 @ encoding: [0xa5,0xf9,0x1a,0x04]
67 # CHECK: vld1.16 {d0[0]}, [lr, :16], r10 @ encoding: [0xae,0xf9,0x1a,0x04]
68 # CHECK: vld1.16 {d9[0]}, [r5, :16], r10 @ encoding: [0xa5,0xf9,0x1a,0x94]
65 # CHECK: vld1.16 {d0[0]}, [r5:16], r0 @ encoding: [0xa5,0xf9,0x10,0x04]
66 # CHECK: vld1.16 {d0[0]}, [r5:16], r10 @ encoding: [0xa5,0xf9,0x1a,0x04]
67 # CHECK: vld1.16 {d0[0]}, [lr:16], r10 @ encoding: [0xae,0xf9,0x1a,0x04]
68 # CHECK: vld1.16 {d9[0]}, [r5:16], r10 @ encoding: [0xa5,0xf9,0x1a,0x94]
6969
7070 0xa0 0xf9 0x20 0x0b
7171 0xa0 0xf9 0x20 0x07
7272 0xa0 0xf9 0x20 0x03
7373
74 # CHECK: vld4.32 {d0[0], d1[0], d2[0], d3[0]}, [r0, :128], r0 @ encoding: [0xa0,0xf9,0x20,0x0b]
74 # CHECK: vld4.32 {d0[0], d1[0], d2[0], d3[0]}, [r0:128], r0 @ encoding: [0xa0,0xf9,0x20,0x0b]
7575 # CHECK: vld4.16 {d0[0], d2[0], d4[0], d6[0]}, [r0], r0 @ encoding: [0xa0,0xf9,0x20,0x07]
7676 # CHECK: vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r0], r0 @ encoding: [0xa0,0xf9,0x20,0x03]
2727 0xc9 0xf9 0xd9 0x94
2828
2929 # CHECK: vst1.16 {d0[0]}, [r0], r0 @ encoding: [0x80,0xf9,0x00,0x04]
30 # CHECK: vst1.16 {d16[0]}, [r3, :16], r3 @ encoding: [0xc3,0xf9,0x13,0x04]
30 # CHECK: vst1.16 {d16[0]}, [r3:16], r3 @ encoding: [0xc3,0xf9,0x13,0x04]
3131 # CHECK: vst1.16 {d16[1]}, [r4], r3 @ encoding: [0xc4,0xf9,0x43,0x04]
32 # CHECK: vst1.16 {d16[1]}, [r5, :16], r5 @ encoding: [0xc5,0xf9,0x55,0x04]
32 # CHECK: vst1.16 {d16[1]}, [r5:16], r5 @ encoding: [0xc5,0xf9,0x55,0x04]
3333 # CHECK: vst1.16 {d16[2]}, [r6], r5 @ encoding: [0xc6,0xf9,0x85,0x04]
34 # CHECK: vst1.16 {d23[2]}, [r7, :16], r5 @ encoding: [0xc7,0xf9,0x95,0x74]
34 # CHECK: vst1.16 {d23[2]}, [r7:16], r5 @ encoding: [0xc7,0xf9,0x95,0x74]
3535 # CHECK: vst1.16 {d24[3]}, [r8], r7 @ encoding: [0xc8,0xf9,0xc7,0x84]
36 # CHECK: vst1.16 {d25[3]}, [r9, :16], r9 @ encoding: [0xc9,0xf9,0xd9,0x94]
36 # CHECK: vst1.16 {d25[3]}, [r9:16], r9 @ encoding: [0xc9,0xf9,0xd9,0x94]
3737
3838 0x8a 0xf9 0x01 0xa8
3939 0xcb 0xf9 0x32 0x18
4141 0xcd 0xf9 0xb4 0x28
4242
4343 # CHECK: vst1.32 {d10[0]}, [r10], r1 @ encoding: [0x8a,0xf9,0x01,0xa8]
44 # CHECK: vst1.32 {d17[0]}, [r11, :32], r2 @ encoding: [0xcb,0xf9,0x32,0x18]
44 # CHECK: vst1.32 {d17[0]}, [r11:32], r2 @ encoding: [0xcb,0xf9,0x32,0x18]
4545 # CHECK: vst1.32 {d11[1]}, [r12], r3 @ encoding: [0x8c,0xf9,0x83,0xb8]
46 # CHECK: vst1.32 {d18[1]}, [sp, :32], r4 @ encoding: [0xcd,0xf9,0xb4,0x28]
46 # CHECK: vst1.32 {d18[1]}, [sp:32], r4 @ encoding: [0xcd,0xf9,0xb4,0x28]
4747
4848 0x81 0xf9 0x1f 0x44
4949 0x82 0xf9 0x8f 0x30
5050
51 # CHECK: vst1.16 {d4[0]}, [r1, :16] @ encoding: [0x81,0xf9,0x1f,0x44]
51 # CHECK: vst1.16 {d4[0]}, [r1:16] @ encoding: [0x81,0xf9,0x1f,0x44]
5252 # CHECK: vst1.8 {d3[4]}, [r2] @ encoding: [0x82,0xf9,0x8f,0x30]
5353
5454 0x83 0xf9 0x1d 0x24
5555 0x84 0xf9 0x8d 0x10
5656
57 # CHECK: vst1.16 {d2[0]}, [r3, :16]! @ encoding: [0x83,0xf9,0x1d,0x24]
57 # CHECK: vst1.16 {d2[0]}, [r3:16]! @ encoding: [0x83,0xf9,0x1d,0x24]
5858 # CHECK: vst1.8 {d1[4]}, [r4]! @ encoding: [0x84,0xf9,0x8d,0x10]
5959
6060 0x85 0xf9 0x10 0x04
6262 0x8e 0xf9 0x1a 0x84
6363 0x85 0xf9 0x1a 0x94
6464
65 # CHECK: vst1.16 {d0[0]}, [r5, :16], r0 @ encoding: [0x85,0xf9,0x10,0x04]
66 # CHECK: vst1.16 {d7[0]}, [r5, :16], r10 @ encoding: [0x85,0xf9,0x1a,0x74]
67 # CHECK: vst1.16 {d8[0]}, [lr, :16], r10 @ encoding: [0x8e,0xf9,0x1a,0x84]
68 # CHECK: vst1.16 {d9[0]}, [r5, :16], r10 @ encoding: [0x85,0xf9,0x1a,0x94]
65 # CHECK: vst1.16 {d0[0]}, [r5:16], r0 @ encoding: [0x85,0xf9,0x10,0x04]
66 # CHECK: vst1.16 {d7[0]}, [r5:16], r10 @ encoding: [0x85,0xf9,0x1a,0x74]
67 # CHECK: vst1.16 {d8[0]}, [lr:16], r10 @ encoding: [0x8e,0xf9,0x1a,0x84]
68 # CHECK: vst1.16 {d9[0]}, [r5:16], r10 @ encoding: [0x85,0xf9,0x1a,0x94]
6969
7070 0x81 0xf9 0x24 0x0b
7171 0x82 0xf9 0x25 0x07
7272 0x83 0xf9 0x26 0x03
7373
74 # CHECK: vst4.32 {d0[0], d1[0], d2[0], d3[0]}, [r1, :128], r4 @ encoding: [0x81,0xf9,0x24,0x0b]
74 # CHECK: vst4.32 {d0[0], d1[0], d2[0], d3[0]}, [r1:128], r4 @ encoding: [0x81,0xf9,0x24,0x0b]
7575 # CHECK: vst4.16 {d0[0], d2[0], d4[0], d6[0]}, [r2], r5 @ encoding: [0x82,0xf9,0x25,0x07]
7676 # CHECK: vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r3], r6 @ encoding: [0x83,0xf9,0x26,0x03]
13781378 # CHECK: vtbx.8 d20, {d16, d17, d18, d19}, d21
13791379
13801380 0x60 0xf9 0x1f 0x07
1381 # CHECK: vld1.8 {d16}, [r0, :64]
1381 # CHECK: vld1.8 {d16}, [r0:64]
13821382 0x60 0xf9 0x4f 0x07
13831383 # CHECK: vld1.16 {d16}, [r0]
13841384 0x60 0xf9 0x8f 0x07
13861386 0x60 0xf9 0xcf 0x07
13871387 # CHECK: vld1.64 {d16}, [r0]
13881388 0x60 0xf9 0x1f 0x0a
1389 # CHECK: vld1.8 {d16, d17}, [r0, :64]
1389 # CHECK: vld1.8 {d16, d17}, [r0:64]
13901390 0x60 0xf9 0x6f 0x0a
1391 # CHECK: vld1.16 {d16, d17}, [r0, :128]
1391 # CHECK: vld1.16 {d16, d17}, [r0:128]
13921392 0x60 0xf9 0x8f 0x0a
13931393 # CHECK: vld1.32 {d16, d17}, [r0]
13941394 0x60 0xf9 0xcf 0x0a
13951395 # CHECK: vld1.64 {d16, d17}, [r0]
13961396
13971397 0x60 0xf9 0x1f 0x08
1398 # CHECK: vld2.8 {d16, d17}, [r0, :64]
1398 # CHECK: vld2.8 {d16, d17}, [r0:64]
13991399 0x60 0xf9 0x6f 0x08
1400 # CHECK: vld2.16 {d16, d17}, [r0, :128]
1400 # CHECK: vld2.16 {d16, d17}, [r0:128]
14011401 0x60 0xf9 0x8f 0x08
14021402 # CHECK: vld2.32 {d16, d17}, [r0]
14031403 0x60 0xf9 0x1f 0x03
1404 # CHECK: vld2.8 {d16, d17, d18, d19}, [r0, :64]
1404 # CHECK: vld2.8 {d16, d17, d18, d19}, [r0:64]
14051405 0x60 0xf9 0x6f 0x03
1406 # CHECK: vld2.16 {d16, d17, d18, d19}, [r0, :128]
1406 # CHECK: vld2.16 {d16, d17, d18, d19}, [r0:128]
14071407 0x60 0xf9 0xbf 0x03
1408 # CHECK: vld2.32 {d16, d17, d18, d19}, [r0, :256]
1408 # CHECK: vld2.32 {d16, d17, d18, d19}, [r0:256]
14091409
14101410 0x60 0xf9 0x1f 0x04
1411 # CHECK: vld3.8 {d16, d17, d18}, [r0, :64]
1411 # CHECK: vld3.8 {d16, d17, d18}, [r0:64]
14121412 0x60 0xf9 0x4f 0x04
14131413 # CHECK: vld3.16 {d16, d17, d18}, [r0]
14141414 0x60 0xf9 0x8f 0x04
14151415 # CHECK: vld3.32 {d16, d17, d18}, [r0]
14161416 0x60 0xf9 0x1d 0x05
1417 # CHECK: vld3.8 {d16, d18, d20}, [r0, :64]!
1417 # CHECK: vld3.8 {d16, d18, d20}, [r0:64]!
14181418 0x60 0xf9 0x1d 0x15
1419 # CHECK: vld3.8 {d17, d19, d21}, [r0, :64]!
1419 # CHECK: vld3.8 {d17, d19, d21}, [r0:64]!
14201420 0x60 0xf9 0x4d 0x05
14211421 # CHECK: vld3.16 {d16, d18, d20}, [r0]!
14221422 0x60 0xf9 0x4d 0x15
14271427 # CHECK: vld3.32 {d17, d19, d21}, [r0]!
14281428
14291429 0x60 0xf9 0x1f 0x00
1430 # CHECK: vld4.8 {d16, d17, d18, d19}, [r0, :64]
1430 # CHECK: vld4.8 {d16, d17, d18, d19}, [r0:64]
14311431 0x60 0xf9 0x6f 0x00
1432 # CHECK: vld4.16 {d16, d17, d18, d19}, [r0, :128]
1432 # CHECK: vld4.16 {d16, d17, d18, d19}, [r0:128]
14331433 0x60 0xf9 0xbf 0x00
1434 # CHECK: vld4.32 {d16, d17, d18, d19}, [r0, :256]
1434 # CHECK: vld4.32 {d16, d17, d18, d19}, [r0:256]
14351435 0x60 0xf9 0x3d 0x01
1436 # CHECK: vld4.8 {d16, d18, d20, d22}, [r0, :256]!
1436 # CHECK: vld4.8 {d16, d18, d20, d22}, [r0:256]!
14371437 0x60 0xf9 0x3d 0x11
1438 # CHECK: vld4.8 {d17, d19, d21, d23}, [r0, :256]!
1438 # CHECK: vld4.8 {d17, d19, d21, d23}, [r0:256]!
14391439 0x60 0xf9 0x4d 0x01
14401440 # CHECK: vld4.16 {d16, d18, d20, d22}, [r0]!
14411441 0x60 0xf9 0x4d 0x11
14481448 0xe0 0xf9 0x6f 0x00
14491449 # CHECK: vld1.8 {d16[3]}, [r0]
14501450 0xe0 0xf9 0x9f 0x04
1451 # CHECK: vld1.16 {d16[2]}, [r0, :16]
1451 # CHECK: vld1.16 {d16[2]}, [r0:16]
14521452 0xe0 0xf9 0xbf 0x08
1453 # CHECK: vld1.32 {d16[1]}, [r0, :32]
1453 # CHECK: vld1.32 {d16[1]}, [r0:32]
14541454
14551455 0xe0 0xf9 0x3f 0x01
1456 # CHECK: vld2.8 {d16[1], d17[1]}, [r0, :16]
1456 # CHECK: vld2.8 {d16[1], d17[1]}, [r0:16]
14571457 0xe0 0xf9 0x5f 0x05
1458 # CHECK: vld2.16 {d16[1], d17[1]}, [r0, :32]
1458 # CHECK: vld2.16 {d16[1], d17[1]}, [r0:32]
14591459 0xe0 0xf9 0x8f 0x09
14601460 # CHECK: vld2.32 {d16[1], d17[1]}, [r0]
14611461 0xe0 0xf9 0x6f 0x15
14621462 # CHECK: vld2.16 {d17[1], d19[1]}, [r0]
14631463 0xe0 0xf9 0x5f 0x19
1464 # CHECK: vld2.32 {d17[0], d19[0]}, [r0, :64]
1464 # CHECK: vld2.32 {d17[0], d19[0]}, [r0:64]
14651465
14661466 0xe0 0xf9 0x2f 0x02
14671467 # CHECK: vld3.8 {d16[1], d17[1], d18[1]}, [r0]
14941494 # CHECK: vld3.32 {d0[], d2[], d4[]}, [r4], r5
14951495
14961496 0xe0 0xf9 0x3f 0x03
1497 # CHECK: vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0, :32]
1497 # CHECK: vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0:32]
14981498 0xe0 0xf9 0x4f 0x07
14991499 # CHECK: vld4.16 {d16[1], d17[1], d18[1], d19[1]}, [r0]
15001500 0xe0 0xf9 0xaf 0x0b
1501 # CHECK: vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0, :128]
1501 # CHECK: vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0:128]
15021502 0xe0 0xf9 0x7f 0x07
1503 # CHECK: vld4.16 {d16[1], d18[1], d20[1], d22[1]}, [r0, :64]
1503 # CHECK: vld4.16 {d16[1], d18[1], d20[1], d22[1]}, [r0:64]
15041504 0xe0 0xf9 0x4f 0x1b
15051505 # CHECK: vld4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0]
15061506
15071507 0xa4 0xf9 0x0f 0x0f
15081508 # CHECK: vld4.8 {d0[], d1[], d2[], d3[]}, [r4]
15091509 0xa4 0xf9 0x3f 0x0f
1510 # CHECK: vld4.8 {d0[], d2[], d4[], d6[]}, [r4, :32]
1510 # CHECK: vld4.8 {d0[], d2[], d4[], d6[]}, [r4:32]
15111511 0xa4 0xf9 0x1d 0x0f
1512 # CHECK: vld4.8 {d0[], d1[], d2[], d3[]}, [r4, :32]!
1512 # CHECK: vld4.8 {d0[], d1[], d2[], d3[]}, [r4:32]!
15131513 0xa4 0xf9 0x35 0x0f
1514 # CHECK: vld4.8 {d0[], d2[], d4[], d6[]}, [r4, :32], r5
1514 # CHECK: vld4.8 {d0[], d2[], d4[], d6[]}, [r4:32], r5
15151515 0xa4 0xf9 0x4f 0x0f
15161516 # CHECK: vld4.16 {d0[], d1[], d2[], d3[]}, [r4]
15171517 0xa4 0xf9 0x7f 0x0f
1518 # CHECK: vld4.16 {d0[], d2[], d4[], d6[]}, [r4, :64]
1518 # CHECK: vld4.16 {d0[], d2[], d4[], d6[]}, [r4:64]
15191519 0xa4 0xf9 0x5d 0x0f
1520 # CHECK: vld4.16 {d0[], d1[], d2[], d3[]}, [r4, :64]!
1520 # CHECK: vld4.16 {d0[], d1[], d2[], d3[]}, [r4:64]!
15211521 0xa4 0xf9 0x75 0x0f
1522 # CHECK: vld4.16 {d0[], d2[], d4[], d6[]}, [r4, :64], r5
1522 # CHECK: vld4.16 {d0[], d2[], d4[], d6[]}, [r4:64], r5
15231523 0xa4 0xf9 0x8f 0x0f
15241524 # CHECK: vld4.32 {d0[], d1[], d2[], d3[]}, [r4]
15251525 0xa4 0xf9 0xbf 0x0f
1526 # CHECK: vld4.32 {d0[], d2[], d4[], d6[]}, [r4, :64]
1526 # CHECK: vld4.32 {d0[], d2[], d4[], d6[]}, [r4:64]
15271527 0xa4 0xf9 0xdd 0x0f
1528 # CHECK: vld4.32 {d0[], d1[], d2[], d3[]}, [r4, :128]!
1528 # CHECK: vld4.32 {d0[], d1[], d2[], d3[]}, [r4:128]!
15291529 0xa4 0xf9 0xf5 0x0f
1530 # CHECK: vld4.32 {d0[], d2[], d4[], d6[]}, [r4, :128], r5
1530 # CHECK: vld4.32 {d0[], d2[], d4[], d6[]}, [r4:128], r5
15311531
15321532 0x40 0xf9 0x1f 0x07
1533 # CHECK: vst1.8 {d16}, [r0, :64]
1533 # CHECK: vst1.8 {d16}, [r0:64]
15341534 0x40 0xf9 0x4f 0x07
15351535 # CHECK: vst1.16 {d16}, [r0]
15361536 0x40 0xf9 0x8f 0x07
15381538 0x40 0xf9 0xcf 0x07
15391539 # CHECK: vst1.64 {d16}, [r0]
15401540 0x40 0xf9 0x1f 0x0a
1541 # CHECK: vst1.8 {d16, d17}, [r0, :64]
1541 # CHECK: vst1.8 {d16, d17}, [r0:64]
15421542 0x40 0xf9 0x6f 0x0a
1543 # CHECK: vst1.16 {d16, d17}, [r0, :128]
1543 # CHECK: vst1.16 {d16, d17}, [r0:128]
15441544 0x40 0xf9 0x8f 0x0a
15451545 # CHECK: vst1.32 {d16, d17}, [r0]
15461546 0x40 0xf9 0xcf 0x0a
15471547 # CHECK: vst1.64 {d16, d17}, [r0]
15481548
15491549 0x40 0xf9 0x1f 0x08
1550 # CHECK: vst2.8 {d16, d17}, [r0, :64]
1550 # CHECK: vst2.8 {d16, d17}, [r0:64]
15511551 0x40 0xf9 0x6f 0x08
1552 # CHECK: vst2.16 {d16, d17}, [r0, :128]
1552 # CHECK: vst2.16 {d16, d17}, [r0:128]
15531553 0x40 0xf9 0x8f 0x08
15541554 # CHECK: vst2.32 {d16, d17}, [r0]
15551555 0x40 0xf9 0x1f 0x03
1556 # CHECK: vst2.8 {d16, d17, d18, d19}, [r0, :64]
1556 # CHECK: vst2.8 {d16, d17, d18, d19}, [r0:64]
15571557 0x40 0xf9 0x6f 0x03
1558 # CHECK: vst2.16 {d16, d17, d18, d19}, [r0, :128]
1558 # CHECK: vst2.16 {d16, d17, d18, d19}, [r0:128]
15591559 0x40 0xf9 0xbf 0x03
1560 # CHECK: vst2.32 {d16, d17, d18, d19}, [r0, :256]
1560 # CHECK: vst2.32 {d16, d17, d18, d19}, [r0:256]
15611561
15621562 0x40 0xf9 0x1f 0x04
1563 # CHECK: vst3.8 {d16, d17, d18}, [r0, :64]
1563 # CHECK: vst3.8 {d16, d17, d18}, [r0:64]
15641564 0x40 0xf9 0x4f 0x04
15651565 # CHECK: vst3.16 {d16, d17, d18}, [r0]
15661566 0x40 0xf9 0x8f 0x04
15671567 # CHECK: vst3.32 {d16, d17, d18}, [r0]
15681568 0x40 0xf9 0x1d 0x05
1569 # CHECK: vst3.8 {d16, d18, d20}, [r0, :64]!
1569 # CHECK: vst3.8 {d16, d18, d20}, [r0:64]!
15701570 0x40 0xf9 0x1d 0x15
1571 # CHECK: vst3.8 {d17, d19, d21}, [r0, :64]!
1571 # CHECK: vst3.8 {d17, d19, d21}, [r0:64]!
15721572 0x40 0xf9 0x4d 0x05
15731573 # CHECK: vst3.16 {d16, d18, d20}, [r0]!
15741574 0x40 0xf9 0x4d 0x15
15791579 # CHECK: vst3.32 {d17, d19, d21}, [r0]!
15801580
15811581 0x40 0xf9 0x1f 0x00
1582 # CHECK: vst4.8 {d16, d17, d18, d19}, [r0, :64]
1582 # CHECK: vst4.8 {d16, d17, d18, d19}, [r0:64]
15831583 0x40 0xf9 0x6f 0x00
1584 # CHECK: vst4.16 {d16, d17, d18, d19}, [r0, :128]
1584 # CHECK: vst4.16 {d16, d17, d18, d19}, [r0:128]
15851585 0x40 0xf9 0x3d 0x01
1586 # CHECK: vst4.8 {d16, d18, d20, d22}, [r0, :256]!
1586 # CHECK: vst4.8 {d16, d18, d20, d22}, [r0:256]!
15871587 0x40 0xf9 0x3d 0x11
1588 # CHECK: vst4.8 {d17, d19, d21, d23}, [r0, :256]!
1588 # CHECK: vst4.8 {d17, d19, d21, d23}, [r0:256]!
15891589 0x40 0xf9 0x4d 0x01
15901590 # CHECK: vst4.16 {d16, d18, d20, d22}, [r0]!
15911591 0x40 0xf9 0x4d 0x11
15961596 # CHECK: vst4.32 {d17, d19, d21, d23}, [r0]!
15971597
15981598 0xc0 0xf9 0x3f 0x01
1599 # CHECK: vst2.8 {d16[1], d17[1]}, [r0, :16]
1599 # CHECK: vst2.8 {d16[1], d17[1]}, [r0:16]
16001600 0xc0 0xf9 0x5f 0x05
1601 # CHECK: vst2.16 {d16[1], d17[1]}, [r0, :32]
1601 # CHECK: vst2.16 {d16[1], d17[1]}, [r0:32]
16021602 0xc0 0xf9 0x8f 0x09
16031603 # CHECK: vst2.32 {d16[1], d17[1]}, [r0]
16041604 0xc0 0xf9 0x6f 0x15
16051605 # CHECK: vst2.16 {d17[1], d19[1]}, [r0]
16061606 0xc0 0xf9 0x5f 0x19
1607 # CHECK: vst2.32 {d17[0], d19[0]}, [r0, :64]
1607 # CHECK: vst2.32 {d17[0], d19[0]}, [r0:64]
16081608
16091609 0xc0 0xf9 0x2f 0x02
16101610 # CHECK: vst3.8 {d16[1], d17[1], d18[1]}, [r0]
16181618 # CHECK: vst3.32 {d16[0], d18[0], d20[0]}, [r0]
16191619
16201620 0xc0 0xf9 0x3f 0x03
1621 # CHECK: vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0, :32]
1621 # CHECK: vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0:32]
16221622 0xc0 0xf9 0x4f 0x07
16231623 # CHECK: vst4.16 {d16[1], d17[1], d18[1], d19[1]}, [r0]
16241624 0xc0 0xf9 0xaf 0x0b
1625 # CHECK: vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0, :128]
1625 # CHECK: vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0:128]
16261626 0xc0 0xf9 0xff 0x17
1627 # CHECK: vst4.16 {d17[3], d19[3], d21[3], d23[3]}, [r0, :64]
1627 # CHECK: vst4.16 {d17[3], d19[3], d21[3], d23[3]}, [r0:64]
16281628 0xc0 0xf9 0x4f 0x1b
16291629 # CHECK: vst4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0]
16301630
16311631 0x63 0xf9 0x37 0xc9
1632 # CHECK: vld2.8 {d28, d30}, [r3, :256], r7
1632 # CHECK: vld2.8 {d28, d30}, [r3:256], r7
16331633
16341634 # rdar://10798451
16351635 0xe7 0xf9 0x32 0x1d
1636 # CHECK vld2.8 {d17[], d19[]}, [r7, :16], r2
1636 # CHECK vld2.8 {d17[], d19[]}, [r7:16], r2
16371637 0xe7 0xf9 0x3d 0x1d
1638 # CHECK vld2.8 {d17[], d19[]}, [r7, :16]!
1638 # CHECK vld2.8 {d17[], d19[]}, [r7:16]!
16391639 0xe7 0xf9 0x3f 0x1d
1640 # CHECK vld2.8 {d17[], d19[]}, [r7, :16]
1640 # CHECK vld2.8 {d17[], d19[]}, [r7:16]
16411641
16421642 # rdar://11034702
16431643 0x04 0xf9 0x0d 0x87
20452045
20462046 # rdar://10798451
20472047 0xe7 0xf9 0x32 0x1d
2048 # CHECK: vld2.8 {d17[], d19[]}, [r7, :16], r2
2048 # CHECK: vld2.8 {d17[], d19[]}, [r7:16], r2
20492049 0xe7 0xf9 0x3d 0x1d
2050 # CHECK: vld2.8 {d17[], d19[]}, [r7, :16]!
2050 # CHECK: vld2.8 {d17[], d19[]}, [r7:16]!
20512051 0xe7 0xf9 0x3f 0x1d
2052 # CHECK: vld2.8 {d17[], d19[]}, [r7, :16]
2053
2052 # CHECK: vld2.8 {d17[], d19[]}, [r7:16]
2053