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[AMDGPU] Assembler: SOP* instruction fixes s_bitset0_b64, s_bitset1_b64 has 32-bit src0, not 64-bit. s_rfe_b64 has just one destination operand and no source. Uncomment S_BITCMP* and S_SETVSKIP, adjust SOPC_* classes for that. Add s_memrealtime test and change comments in smem.s to follow common style. Change test for s_memtime to use non-zero register to make it really test encoding. Add tests for s_buffer_load*. Add tests for SOPC instructions (same for SI and VI) Differential Revision: http://reviews.llvm.org/D18040 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263420 91177308-0d34-0410-b5e6-96231b3b80d8 Nikolay Haustov 4 years ago
6 changed file(s) with 162 addition(s) and 44 deletion(s). Raw diff Collapse all Expand all
900900 opName#" $sdst, $src0", pattern
901901 >;
902902
903 // 32-bit input, 64-bit output.
904 multiclass SOP1_64_32 pattern> : SOP1_m <
905 op, opName, (outs SReg_64:$sdst), (ins SSrc_32:$src0),
906 opName#" $sdst, $src0", pattern
907 >;
908
903909 class SOP2_Pseudo pattern> :
904910 SOP2,
905911 SIMCInstr {
963969 opName#" $sdst, $src0, $src1", pattern
964970 >;
965971
972 class SOPC_Base op, RegisterOperand rc0, RegisterOperand rc1,
973 string opName, list pattern = []> : SOPC <
974 op, (outs), (ins rc0:$src0, rc1:$src1),
975 opName#" $src0, $src1", pattern > {
976 let Defs = [SCC];
977 }
966978 class SOPC_Helper op, RegisterOperand rc, ValueType vt,
967 string opName, PatLeaf cond> : SOPC <
968 op, (outs), (ins rc:$src0, rc:$src1),
969 opName#" $src0, $src1",
979 string opName, PatLeaf cond> : SOPC_Base <
980 op, rc, rc, opName,
970981 [(set SCC, (si_setcc_uniform vt:$src0, vt:$src1, cond))] > {
971 let Defs = [SCC];
972 }
973
974 class SOPC_32 op, string opName, PatLeaf cond = COND_NULL>
982 }
983
984 class SOPC_CMP_32 op, string opName, PatLeaf cond = COND_NULL>
975985 : SOPC_Helper;
976986
977 class SOPC_64 op, string opName, PatLeaf cond = COND_NULL>
978 : SOPC_Helper;
987 class SOPC_32 op, string opName, list pattern = []>
988 : SOPC_Base;
989
990 class SOPC_64_32 op, string opName, list pattern = []>
991 : SOPC_Base;
979992
980993 class SOPK_Pseudo pattern> :
981994 SOPK ,
167167 >;
168168
169169 defm S_BITSET0_B32 : SOP1_32 , "s_bitset0_b32", []>;
170 defm S_BITSET0_B64 : SOP1_64 , "s_bitset0_b64", []>;
170 defm S_BITSET0_B64 : SOP1_64_32 , "s_bitset0_b64", []>;
171171 defm S_BITSET1_B32 : SOP1_32 , "s_bitset1_b32", []>;
172 defm S_BITSET1_B64 : SOP1_64 , "s_bitset1_b64", []>;
172 defm S_BITSET1_B64 : SOP1_64_32 , "s_bitset1_b64", []>;
173173 defm S_GETPC_B64 : SOP1_64_0 , "s_getpc_b64", []>;
174174 defm S_SETPC_B64 : SOP1_1 , "s_setpc_b64", []>;
175175 defm S_SWAPPC_B64 : SOP1_64 , "s_swappc_b64", []>;
176 defm S_RFE_B64 : SOP1_64 , "s_rfe_b64", []>;
176 defm S_RFE_B64 : SOP1_1 , "s_rfe_b64", []>;
177177
178178 let hasSideEffects = 1, Uses = [EXEC], Defs = [EXEC, SCC] in {
179179
343343 // SOPC Instructions
344344 //===----------------------------------------------------------------------===//
345345
346 def S_CMP_EQ_I32 : SOPC_32 <0x00000000, "s_cmp_eq_i32", COND_EQ>;
347 def S_CMP_LG_I32 : SOPC_32 <0x00000001, "s_cmp_lg_i32", COND_NE>;
348 def S_CMP_GT_I32 : SOPC_32 <0x00000002, "s_cmp_gt_i32", COND_SGT>;
349 def S_CMP_GE_I32 : SOPC_32 <0x00000003, "s_cmp_ge_i32", COND_SGE>;
350 def S_CMP_LT_I32 : SOPC_32 <0x00000004, "s_cmp_lt_i32", COND_SLT>;
351 def S_CMP_LE_I32 : SOPC_32 <0x00000005, "s_cmp_le_i32", COND_SLE>;
352 def S_CMP_EQ_U32 : SOPC_32 <0x00000006, "s_cmp_eq_u32", COND_EQ>;
353 def S_CMP_LG_U32 : SOPC_32 <0x00000007, "s_cmp_lg_u32", COND_NE >;
354 def S_CMP_GT_U32 : SOPC_32 <0x00000008, "s_cmp_gt_u32", COND_UGT>;
355 def S_CMP_GE_U32 : SOPC_32 <0x00000009, "s_cmp_ge_u32", COND_UGE>;
356 def S_CMP_LT_U32 : SOPC_32 <0x0000000a, "s_cmp_lt_u32", COND_ULT>;
357 def S_CMP_LE_U32 : SOPC_32 <0x0000000b, "s_cmp_le_u32", COND_ULE>;
358 ////def S_BITCMP0_B32 : SOPC_BITCMP0 <0x0000000c, "s_bitcmp0_b32", []>;
359 ////def S_BITCMP1_B32 : SOPC_BITCMP1 <0x0000000d, "s_bitcmp1_b32", []>;
360 ////def S_BITCMP0_B64 : SOPC_BITCMP0 <0x0000000e, "s_bitcmp0_b64", []>;
361 ////def S_BITCMP1_B64 : SOPC_BITCMP1 <0x0000000f, "s_bitcmp1_b64", []>;
362 //def S_SETVSKIP : SOPC_ <0x00000010, "s_setvskip", []>;
346 def S_CMP_EQ_I32 : SOPC_CMP_32 <0x00000000, "s_cmp_eq_i32", COND_EQ>;
347 def S_CMP_LG_I32 : SOPC_CMP_32 <0x00000001, "s_cmp_lg_i32", COND_NE>;
348 def S_CMP_GT_I32 : SOPC_CMP_32 <0x00000002, "s_cmp_gt_i32", COND_SGT>;
349 def S_CMP_GE_I32 : SOPC_CMP_32 <0x00000003, "s_cmp_ge_i32", COND_SGE>;
350 def S_CMP_LT_I32 : SOPC_CMP_32 <0x00000004, "s_cmp_lt_i32", COND_SLT>;
351 def S_CMP_LE_I32 : SOPC_CMP_32 <0x00000005, "s_cmp_le_i32", COND_SLE>;
352 def S_CMP_EQ_U32 : SOPC_CMP_32 <0x00000006, "s_cmp_eq_u32", COND_EQ>;
353 def S_CMP_LG_U32 : SOPC_CMP_32 <0x00000007, "s_cmp_lg_u32", COND_NE >;
354 def S_CMP_GT_U32 : SOPC_CMP_32 <0x00000008, "s_cmp_gt_u32", COND_UGT>;
355 def S_CMP_GE_U32 : SOPC_CMP_32 <0x00000009, "s_cmp_ge_u32", COND_UGE>;
356 def S_CMP_LT_U32 : SOPC_CMP_32 <0x0000000a, "s_cmp_lt_u32", COND_ULT>;
357 def S_CMP_LE_U32 : SOPC_CMP_32 <0x0000000b, "s_cmp_le_u32", COND_ULE>;
358 def S_BITCMP0_B32 : SOPC_32 <0x0000000c, "s_bitcmp0_b32">;
359 def S_BITCMP1_B32 : SOPC_32 <0x0000000d, "s_bitcmp1_b32">;
360 def S_BITCMP0_B64 : SOPC_64_32 <0x0000000e, "s_bitcmp0_b64">;
361 def S_BITCMP1_B64 : SOPC_64_32 <0x0000000f, "s_bitcmp1_b64">;
362 def S_SETVSKIP : SOPC_32 <0x00000010, "s_setvskip">;
363363
364364 //===----------------------------------------------------------------------===//
365365 // SOPK Instructions
22 // RUN: not llvm-mc -arch=amdgcn -mcpu=bonaire %s 2>&1 | FileCheck -check-prefix=NOSI %s
33
44 s_dcache_wb
5 ; VI: s_dcache_wb ; encoding: [0x00,0x00,0x84,0xc0,0x00,0x00,0x00,0x00]
6 ; NOSI: error: instruction not supported on this GPU
5 // VI: s_dcache_wb ; encoding: [0x00,0x00,0x84,0xc0,0x00,0x00,0x00,0x00]
6 // NOSI: error: instruction not supported on this GPU
77
88 s_dcache_wb_vol
9 ; VI: s_dcache_wb_vol ; encoding: [0x00,0x00,0x8c,0xc0,0x00,0x00,0x00,0x00]
10 ; NOSI: error: instruction not supported on this GPU
9 // VI: s_dcache_wb_vol ; encoding: [0x00,0x00,0x8c,0xc0,0x00,0x00,0x00,0x00]
10 // NOSI: error: instruction not supported on this GPU
11
12 s_memrealtime s[4:5]
13 // VI: s_memrealtime s[4:5] ; encoding: [0x00,0x01,0x94,0xc0,0x00,0x00,0x00,0x00]
14 // NOSI: error: instruction not supported on this GPU
7979 // GCN: s_load_dwordx16 s[88:103], s[2:3], s4 ; encoding: [0x04,0x02,0x2c,0xc1]
8080 // NOVI: error: invalid operand for instruction
8181
82 s_buffer_load_dword s1, s[4:7], 1
83 // GCN: s_buffer_load_dword s1, s[4:7], 0x1 ; encoding: [0x01,0x85,0x00,0xc2]
84 // VI: s_buffer_load_dword s1, s[4:7], 0x1 ; encoding: [0x42,0x00,0x22,0xc0,0x01,0x00,0x00,0x00]
85
86 s_buffer_load_dword s1, s[4:7], s4
87 // GCN: s_buffer_load_dword s1, s[4:7], s4 ; encoding: [0x04,0x84,0x00,0xc2]
88 // VI: s_buffer_load_dword s1, s[4:7], s4 ; encoding: [0x42,0x00,0x20,0xc0,0x04,0x00,0x00,0x00]
89
90 s_buffer_load_dwordx2 s[8:9], s[4:7], 1
91 // GCN: s_buffer_load_dwordx2 s[8:9], s[4:7], 0x1 ; encoding: [0x01,0x05,0x44,0xc2]
92 // VI: s_buffer_load_dwordx2 s[8:9], s[4:7], 0x1 ; encoding: [0x02,0x02,0x26,0xc0,0x01,0x00,0x00,0x00]
93
94 s_buffer_load_dwordx2 s[8:9], s[4:7], s4
95 // GCN: s_buffer_load_dwordx2 s[8:9], s[4:7], s4 ; encoding: [0x04,0x04,0x44,0xc2]
96 // VI: s_buffer_load_dwordx2 s[8:9], s[4:7], s4 ; encoding: [0x02,0x02,0x24,0xc0,0x04,0x00,0x00,0x00]
97
98 s_buffer_load_dwordx4 s[8:11], s[4:7], 1
99 // GCN: s_buffer_load_dwordx4 s[8:11], s[4:7], 0x1 ; encoding: [0x01,0x05,0x84,0xc2]
100 // VI: s_buffer_load_dwordx4 s[8:11], s[4:7], 0x1 ; encoding: [0x02,0x02,0x2a,0xc0,0x01,0x00,0x00,0x00]
101
102 s_buffer_load_dwordx4 s[8:11], s[4:7], s4
103 // GCN: s_buffer_load_dwordx4 s[8:11], s[4:7], s4 ; encoding: [0x04,0x04,0x84,0xc2]
104 // VI: s_buffer_load_dwordx4 s[8:11], s[4:7], s4 ; encoding: [0x02,0x02,0x28,0xc0,0x04,0x00,0x00,0x00]
105
106 s_buffer_load_dwordx4 s[100:103], s[4:7], s4
107 // GCN: s_buffer_load_dwordx4 s[100:103], s[4:7], s4 ; encoding: [0x04,0x04,0xb2,0xc2]
108 // NOVI: error: invalid operand for instruction
109
110 s_buffer_load_dwordx8 s[8:15], s[4:7], 1
111 // GCN: s_buffer_load_dwordx8 s[8:15], s[4:7], 0x1 ; encoding: [0x01,0x05,0xc4,0xc2]
112 // VI: s_buffer_load_dwordx8 s[8:15], s[4:7], 0x1 ; encoding: [0x02,0x02,0x2e,0xc0,0x01,0x00,0x00,0x00]
113
114 s_buffer_load_dwordx8 s[8:15], s[4:7], s4
115 // GCN: s_buffer_load_dwordx8 s[8:15], s[4:7], s4 ; encoding: [0x04,0x04,0xc4,0xc2]
116 // VI: s_buffer_load_dwordx8 s[8:15], s[4:7], s4 ; encoding: [0x02,0x02,0x2c,0xc0,0x04,0x00,0x00,0x00]
117
118 s_buffer_load_dwordx8 s[96:103], s[4:7], s4
119 // GCN: s_buffer_load_dwordx8 s[96:103], s[4:7], s4 ; encoding: [0x04,0x04,0xf0,0xc2]
120 // NOVI: error: invalid operand for instruction
121
122 s_buffer_load_dwordx16 s[16:31], s[4:7], 1
123 // GCN: s_buffer_load_dwordx16 s[16:31], s[4:7], 0x1 ; encoding: [0x01,0x05,0x08,0xc3]
124 // VI: s_buffer_load_dwordx16 s[16:31], s[4:7], 0x1 ; encoding: [0x02,0x04,0x32,0xc0,0x01,0x00,0x00,0x00]
125
126 s_buffer_load_dwordx16 s[16:31], s[4:7], s4
127 // GCN: s_buffer_load_dwordx16 s[16:31], s[4:7], s4 ; encoding: [0x04,0x04,0x08,0xc3]
128 // VI: s_buffer_load_dwordx16 s[16:31], s[4:7], s4 ; encoding: [0x02,0x04,0x30,0xc0,0x04,0x00,0x00,0x00]
129
130 s_buffer_load_dwordx16 s[88:103], s[4:7], s4
131 // GCN: s_buffer_load_dwordx16 s[88:103], s[4:7], s4 ; encoding: [0x04,0x04,0x2c,0xc3]
132 // NOVI: error: invalid operand for instruction
133
82134 s_dcache_inv
83135 // GCN: s_dcache_inv ; encoding: [0x00,0x00,0xc0,0xc7]
84136 // VI: s_dcache_inv ; encoding: [0x00,0x00,0x80,0xc0,0x00,0x00,0x00,0x00]
88140 // NOSI: error: instruction not supported on this GPU
89141 // VI: s_dcache_inv_vol ; encoding: [0x00,0x00,0x88,0xc0,0x00,0x00,0x00,0x00]
90142
91 s_memtime s[0:1]
92 // GCN: s_memtime s[0:1] ; encoding: [0x00,0x00,0x80,0xc7]
93 // VI: s_memtime s[0:1] ; encoding: [0x00,0x00,0x90,0xc0,0x00,0x00,0x00,0x00]
143 s_memtime s[4:5]
144 // GCN: s_memtime s[4:5] ; encoding: [0x00,0x00,0x82,0xc7]
145 // VI: s_memtime s[4:5] ; encoding: [0x00,0x01,0x90,0xc0,0x00,0x00,0x00,0x00]
120120 s_bitset0_b32 s1, s2
121121 // CHECK: s_bitset0_b32 s1, s2 ; encoding: [0x02,0x1b,0x81,0xbe]
122122
123 s_bitset0_b64 s[2:3], s[4:5]
124 // CHECK: s_bitset0_b64 s[2:3], s[4:5] ; encoding: [0x04,0x1c,0x82,0xbe]
123 s_bitset0_b64 s[2:3], s4
124 // CHECK: s_bitset0_b64 s[2:3], s4 ; encoding: [0x04,0x1c,0x82,0xbe]
125125
126126 s_bitset1_b32 s1, s2
127127 // CHECK: s_bitset1_b32 s1, s2 ; encoding: [0x02,0x1d,0x81,0xbe]
128128
129 s_bitset1_b64 s[2:3], s[4:5]
130 // CHECK: s_bitset1_b64 s[2:3], s[4:5] ; encoding: [0x04,0x1e,0x82,0xbe]
129 s_bitset1_b64 s[2:3], s4
130 // CHECK: s_bitset1_b64 s[2:3], s4 ; encoding: [0x04,0x1e,0x82,0xbe]
131131
132132 s_getpc_b64 s[2:3]
133133 // CHECK: s_getpc_b64 s[2:3] ; encoding: [0x00,0x1f,0x82,0xbe]
138138 s_swappc_b64 s[2:3], s[4:5]
139139 // CHECK: s_swappc_b64 s[2:3], s[4:5] ; encoding: [0x04,0x21,0x82,0xbe]
140140
141 s_rfe_b64 s[2:3], s[4:5]
142 // CHECK: s_rfe_b64 s[2:3], s[4:5] ; encoding: [0x04,0x22,0x82,0xbe]
141 s_rfe_b64 s[4:5]
142 // CHECK: s_rfe_b64 s[4:5] ; encoding: [0x04,0x22,0x80,0xbe]
143143
144144 s_and_saveexec_b64 s[2:3], s[4:5]
145145 // CHECK: s_and_saveexec_b64 s[2:3], s[4:5] ; encoding: [0x04,0x24,0x82,0xbe]
0 // RUN: llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s
1 // RUN: llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s
1 // RUN: llvm-mc -arch=amdgcn -mcpu=SI -show-encoding %s | FileCheck %s
2 // RUN: llvm-mc -arch=amdgcn -mcpu=fiji -show-encoding %s | FileCheck %s
23
34 //===----------------------------------------------------------------------===//
4 // Instructions
5 // SOPC Instructions
56 //===----------------------------------------------------------------------===//
67
78 s_cmp_eq_i32 s1, s2
89 // CHECK: s_cmp_eq_i32 s1, s2 ; encoding: [0x01,0x02,0x00,0xbf]
10
11 s_cmp_lg_i32 s1, s2
12 // CHECK: s_cmp_lg_i32 s1, s2 ; encoding: [0x01,0x02,0x01,0xbf]
13
14 s_cmp_gt_i32 s1, s2
15 // CHECK: s_cmp_gt_i32 s1, s2 ; encoding: [0x01,0x02,0x02,0xbf]
16
17 s_cmp_ge_i32 s1, s2
18 // CHECK: s_cmp_ge_i32 s1, s2 ; encoding: [0x01,0x02,0x03,0xbf]
19
20 s_cmp_lt_i32 s1, s2
21 // CHECK: s_cmp_lt_i32 s1, s2 ; encoding: [0x01,0x02,0x04,0xbf]
22
23 s_cmp_le_i32 s1, s2
24 // CHECK: s_cmp_le_i32 s1, s2 ; encoding: [0x01,0x02,0x05,0xbf]
25
26 s_cmp_eq_u32 s1, s2
27 // CHECK: s_cmp_eq_u32 s1, s2 ; encoding: [0x01,0x02,0x06,0xbf]
28
29 s_cmp_lg_u32 s1, s2
30 // CHECK: s_cmp_lg_u32 s1, s2 ; encoding: [0x01,0x02,0x07,0xbf]
31
32 s_cmp_gt_u32 s1, s2
33 // CHECK: s_cmp_gt_u32 s1, s2 ; encoding: [0x01,0x02,0x08,0xbf]
34
35 s_cmp_ge_u32 s1, s2
36 // CHECK: s_cmp_ge_u32 s1, s2 ; encoding: [0x01,0x02,0x09,0xbf]
37
38 s_cmp_lt_u32 s1, s2
39 // CHECK: s_cmp_lt_u32 s1, s2 ; encoding: [0x01,0x02,0x0a,0xbf]
40
41 s_cmp_le_u32 s1, s2
42 // CHECK: s_cmp_le_u32 s1, s2 ; encoding: [0x01,0x02,0x0b,0xbf]
43
44 s_bitcmp0_b32 s1, s2
45 // CHECK: s_bitcmp0_b32 s1, s2 ; encoding: [0x01,0x02,0x0c,0xbf]
46
47 s_bitcmp1_b32 s1, s2
48 // CHECK: s_bitcmp1_b32 s1, s2 ; encoding: [0x01,0x02,0x0d,0xbf]
49
50 s_bitcmp0_b64 s[2:3], s4
51 // CHECK: s_bitcmp0_b64 s[2:3], s4 ; encoding: [0x02,0x04,0x0e,0xbf]
52
53 s_bitcmp1_b64 s[2:3], s4
54 // CHECK: s_bitcmp1_b64 s[2:3], s4 ; encoding: [0x02,0x04,0x0f,0xbf]
55
56 s_setvskip s3, s5
57 // CHECK: s_setvskip s3, s5 ; encoding: [0x03,0x05,0x10,0xbf]