llvm.org GIT mirror llvm / 296925d
Fix PR5024. LiveVariables physical register defs should *commit* only after all of the defs are processed. Also fix a implicit_def propagation bug: a implicit_def of a physical register should be applied to uses of the sub-registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82616 91177308-0d34-0410-b5e6-96231b3b80d8 Evan Cheng 11 years ago
4 changed file(s) with 126 addition(s) and 34 deletion(s). Raw diff Collapse all Expand all
148148 bool HandlePhysRegKill(unsigned Reg, MachineInstr *MI);
149149
150150 void HandlePhysRegUse(unsigned Reg, MachineInstr *MI);
151 void HandlePhysRegDef(unsigned Reg, MachineInstr *MI);
151 void HandlePhysRegDef(unsigned Reg, MachineInstr *MI,
152 SmallVector &Defs,
153 SmallVector &SuperDefs);
154 void UpdatePhysRegDefs(MachineInstr *MI, SmallVector &Defs);
155 void UpdateSuperRegDefs(MachineInstr *MI, SmallVector &Defs);
152156
153157 /// FindLastPartialDef - Return the last partial def of the specified register.
154158 /// Also returns the sub-registers that're defined by the instruction.
140140 if (MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF) {
141141 unsigned Reg = MI->getOperand(0).getReg();
142142 ImpDefRegs.insert(Reg);
143 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
144 for (const unsigned *SS = tri_->getSubRegisters(Reg); *SS; ++SS)
145 ImpDefRegs.insert(*SS);
146 }
143147 ImpDefMIs.push_back(MI);
144148 continue;
145149 }
406406 return true;
407407 }
408408
409 void LiveVariables::HandlePhysRegDef(unsigned Reg, MachineInstr *MI) {
409 void LiveVariables::HandlePhysRegDef(unsigned Reg, MachineInstr *MI,
410 SmallVector &Defs,
411 SmallVector &SuperDefs) {
410412 // What parts of the register are previously defined?
411413 SmallSet Live;
412414 if (PhysRegDef[Reg] || PhysRegUse[Reg]) {
464466 // EAX =
465467 // AX = EAX, EAX
466468 // ...
467 /// = EAX
468 if (hasRegisterUseBelow(SuperReg, MI, MI->getParent())) {
469 MI->addOperand(MachineOperand::CreateReg(SuperReg, false/*IsDef*/,
470 true/*IsImp*/,true/*IsKill*/));
471 MI->addOperand(MachineOperand::CreateReg(SuperReg, true/*IsDef*/,
472 true/*IsImp*/));
473 PhysRegDef[SuperReg] = MI;
474 PhysRegUse[SuperReg] = NULL;
475 Processed.insert(SuperReg);
476 for (const unsigned *SS = TRI->getSubRegisters(SuperReg); *SS; ++SS) {
477 PhysRegDef[*SS] = MI;
478 PhysRegUse[*SS] = NULL;
479 Processed.insert(*SS);
480 }
481 } else {
482 // Otherwise, the super register is killed.
483 if (HandlePhysRegKill(SuperReg, MI)) {
484 PhysRegDef[SuperReg] = NULL;
485 PhysRegUse[SuperReg] = NULL;
486 for (const unsigned *SS = TRI->getSubRegisters(SuperReg); *SS; ++SS) {
487 PhysRegDef[*SS] = NULL;
488 PhysRegUse[*SS] = NULL;
489 Processed.insert(*SS);
490 }
491 }
492 }
469 // = EAX
470 SuperDefs.push_back(SuperReg);
471 Processed.insert(SuperReg);
472 for (const unsigned *SS = TRI->getSubRegisters(SuperReg); *SS; ++SS)
473 Processed.insert(*SS);
493474 }
494475 }
495476
496477 // Remember this def.
478 Defs.push_back(Reg);
479 }
480 }
481
482 void LiveVariables::UpdatePhysRegDefs(MachineInstr *MI,
483 SmallVector &Defs) {
484 while (!Defs.empty()) {
485 unsigned Reg = Defs.back();
486 Defs.pop_back();
497487 PhysRegDef[Reg] = MI;
498488 PhysRegUse[Reg] = NULL;
499489 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
504494 }
505495 }
506496
497 namespace {
498 struct RegSorter {
499 const TargetRegisterInfo *TRI;
500
501 RegSorter(const TargetRegisterInfo *tri) : TRI(tri) { }
502 bool operator()(unsigned A, unsigned B) {
503 if (TRI->isSubRegister(A, B))
504 return true;
505 else if (TRI->isSubRegister(B, A))
506 return false;
507 return A < B;
508 }
509 };
510 }
511
512 void LiveVariables::UpdateSuperRegDefs(MachineInstr *MI,
513 SmallVector &SuperDefs) {
514 // This instruction has defined part of some registers. If there are no
515 // more uses below MI, then the last use / def becomes kill / dead.
516 if (SuperDefs.empty())
517 return;
518
519 RegSorter RS(TRI);
520 std::sort(SuperDefs.begin(), SuperDefs.end(), RS);
521 SmallSet Processed;
522 for (unsigned j = 0, ee = SuperDefs.size(); j != ee; ++j) {
523 unsigned SuperReg = SuperDefs[j];
524 if (!Processed.insert(SuperReg))
525 continue;
526 if (hasRegisterUseBelow(SuperReg, MI, MI->getParent())) {
527 // Previous use / def is not the last use / dead def. It's now
528 // partially re-defined.
529 MI->addOperand(MachineOperand::CreateReg(SuperReg, false/*IsDef*/,
530 true/*IsImp*/,true/*IsKill*/));
531 MI->addOperand(MachineOperand::CreateReg(SuperReg, true/*IsDef*/,
532 true/*IsImp*/));
533 PhysRegDef[SuperReg] = MI;
534 PhysRegUse[SuperReg] = NULL;
535 for (const unsigned *SS = TRI->getSubRegisters(SuperReg); *SS; ++SS) {
536 Processed.insert(*SS);
537 PhysRegDef[*SS] = MI;
538 PhysRegUse[*SS] = NULL;
539 }
540 } else {
541 // Previous use / def is kill / dead. It's not being re-defined.
542 HandlePhysRegKill(SuperReg, MI);
543 PhysRegDef[SuperReg] = 0;
544 PhysRegUse[SuperReg] = NULL;
545 for (const unsigned *SS = TRI->getSubRegisters(SuperReg); *SS; ++SS) {
546 Processed.insert(*SS);
547 if (PhysRegDef[*SS] == MI)
548 continue; // This instruction may have defined it.
549 PhysRegDef[*SS] = MI;
550 PhysRegUse[*SS] = NULL;
551 }
552 }
553 }
554 SuperDefs.clear();
555 }
556
507557 bool LiveVariables::runOnMachineFunction(MachineFunction &mf) {
508558 MF = &mf;
509559 MRI = &mf.getRegInfo();
536586 MachineBasicBlock *MBB = *DFI;
537587
538588 // Mark live-in registers as live-in.
589 SmallVector Defs;
590 SmallVector SuperDefs;
539591 for (MachineBasicBlock::const_livein_iterator II = MBB->livein_begin(),
540592 EE = MBB->livein_end(); II != EE; ++II) {
541593 assert(TargetRegisterInfo::isPhysicalRegister(*II) &&
542594 "Cannot have a live-in virtual register!");
543 HandlePhysRegDef(*II, 0);
595 HandlePhysRegDef(*II, 0, Defs, SuperDefs);
596 UpdatePhysRegDefs(0, Defs);
597 SuperDefs.clear();
544598 }
545599
546600 // Loop over all of the instructions, processing them.
586640 unsigned MOReg = DefRegs[i];
587641 if (TargetRegisterInfo::isVirtualRegister(MOReg))
588642 HandleVirtRegDef(MOReg, MI);
589 else if (!ReservedRegisters[MOReg])
590 HandlePhysRegDef(MOReg, MI);
591 }
643 else if (!ReservedRegisters[MOReg]) {
644 HandlePhysRegDef(MOReg, MI, Defs, SuperDefs);
645 }
646 }
647
648 UpdateSuperRegDefs(MI, SuperDefs);
649 UpdatePhysRegDefs(MI, Defs);
592650 }
593651
594652 // Handle any virtual assignments from PHI nodes which might be at the
626684 // Loop over PhysRegDef / PhysRegUse, killing any registers that are
627685 // available at the end of the basic block.
628686 for (unsigned i = 0; i != NumRegs; ++i)
629 if (PhysRegDef[i] || PhysRegUse[i])
630 HandlePhysRegDef(i, 0);
687 if (PhysRegDef[i] || PhysRegUse[i]) {
688 HandlePhysRegDef(i, 0, Defs, SuperDefs);
689 UpdatePhysRegDefs(0, Defs);
690 SuperDefs.clear();
691 }
631692
632693 std::fill(PhysRegDef, PhysRegDef + NumRegs, (MachineInstr*)0);
633694 std::fill(PhysRegUse, PhysRegUse + NumRegs, (MachineInstr*)0);
0 ; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mattr=+neon
1
2 ; PR5024
3
4 %bar = type { %foo, %foo }
5 %foo = type { <4 x float> }
6
7 declare arm_aapcs_vfpcc float @aaa(%foo* nocapture) nounwind readonly
8
9 declare arm_aapcs_vfpcc %bar* @bbb(%bar*, <4 x float>, <4 x float>) nounwind
10
11 define arm_aapcs_vfpcc void @ccc(i8* nocapture %pBuffer, i32 %numItems) nounwind {
12 entry:
13 br i1 undef, label %return, label %bb.nph
14
15 bb.nph: ; preds = %entry
16 %0 = call arm_aapcs_vfpcc %bar* @bbb(%bar* undef, <4 x float> undef, <4 x float> undef) nounwind ; <%bar*> [#uses=0]
17 %1 = call arm_aapcs_vfpcc float @aaa(%foo* undef) nounwind ; [#uses=0]
18 unreachable
19
20 return: ; preds = %entry
21 ret void
22 }