llvm.org GIT mirror llvm / 293f71d
[AVX512] Unpack support in new shuffle lowering This now handles both 32 and 64-bit element sizes. In this version, the test are in vector-shuffle-512-v8.ll, canonicalized by Chandler's update_llc_test_checks.py. Part of <rdar://problem/17688758> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225838 91177308-0d34-0410-b5e6-96231b3b80d8 Adam Nemet 5 years ago
2 changed file(s) with 70 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
1074910749 ArrayRef Mask = SVOp->getMask();
1075010750 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
1075110751
10752 // X86 has dedicated unpack instructions that can handle specific blend
10753 // operations: UNPCKH and UNPCKL.
10754 if (isShuffleEquivalent(Mask, 0, 8, 2, 10, 4, 12, 6, 14))
10755 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f64, V1, V2);
10756 if (isShuffleEquivalent(Mask, 1, 9, 3, 11, 5, 13, 7, 15))
10757 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f64, V1, V2);
10758
1075210759 // FIXME: Implement direct support for this type!
1075310760 return splitAndLowerVectorShuffle(DL, MVT::v8f64, V1, V2, Mask, DAG);
1075410761 }
1076410771 ArrayRef Mask = SVOp->getMask();
1076510772 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
1076610773
10774 // Use dedicated unpack instructions for masks that match their pattern.
10775 if (isShuffleEquivalent(Mask,
10776 0, 16, 1, 17, 4, 20, 5, 21,
10777 8, 24, 9, 25, 12, 28, 13, 29))
10778 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16f32, V1, V2);
10779 if (isShuffleEquivalent(Mask,
10780 2, 18, 3, 19, 6, 22, 7, 23,
10781 10, 26, 11, 27, 14, 30, 15, 31))
10782 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16f32, V1, V2);
10783
1076710784 // FIXME: Implement direct support for this type!
1076810785 return splitAndLowerVectorShuffle(DL, MVT::v16f32, V1, V2, Mask, DAG);
1076910786 }
1077910796 ArrayRef Mask = SVOp->getMask();
1078010797 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
1078110798
10799 // X86 has dedicated unpack instructions that can handle specific blend
10800 // operations: UNPCKH and UNPCKL.
10801 if (isShuffleEquivalent(Mask, 0, 8, 2, 10, 4, 12, 6, 14))
10802 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i64, V1, V2);
10803 if (isShuffleEquivalent(Mask, 1, 9, 3, 11, 5, 13, 7, 15))
10804 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i64, V1, V2);
10805
1078210806 // FIXME: Implement direct support for this type!
1078310807 return splitAndLowerVectorShuffle(DL, MVT::v8i64, V1, V2, Mask, DAG);
1078410808 }
1079310817 ShuffleVectorSDNode *SVOp = cast(Op);
1079410818 ArrayRef Mask = SVOp->getMask();
1079510819 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10820
10821 // Use dedicated unpack instructions for masks that match their pattern.
10822 if (isShuffleEquivalent(Mask,
10823 0, 16, 1, 17, 4, 20, 5, 21,
10824 8, 24, 9, 25, 12, 28, 13, 29))
10825 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i32, V1, V2);
10826 if (isShuffleEquivalent(Mask,
10827 2, 18, 3, 19, 6, 22, 7, 23,
10828 10, 26, 11, 27, 14, 30, 15, 31))
10829 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i32, V1, V2);
1079610830
1079710831 // FIXME: Implement direct support for this type!
1079810832 return splitAndLowerVectorShuffle(DL, MVT::v16i32, V1, V2, Mask, DAG);
14171417 %shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32>
14181418 ret <8 x i64> %shuffle
14191419 }
1420
1421 define <8 x double> @shuffle_v4f64_082a4c6e(<8 x double> %a, <8 x double> %b) {
1422 ; ALL-LABEL: shuffle_v4f64_082a4c6e:
1423 ; ALL: # BB#0:
1424 ; ALL-NEXT: vunpcklpd {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[2],zmm1[2],zmm0[4],zmm1[4],zmm0[6],zmm1[6]
1425 ; ALL-NEXT: retq
1426 %shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32>
1427 ret <8 x double> %shuffle
1428 }
1429
1430 define <8 x i64> @shuffle_v4i64_082a4c6e(<8 x i64> %a, <8 x i64> %b) {
1431 ; ALL-LABEL: shuffle_v4i64_082a4c6e:
1432 ; ALL: # BB#0:
1433 ; ALL-NEXT: vpunpcklqdq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[2],zmm1[2],zmm0[4],zmm1[4],zmm0[6],zmm1[6]
1434 ; ALL-NEXT: retq
1435 %shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32>
1436 ret <8 x i64> %shuffle
1437 }
1438
1439 define <8 x double> @shuffle_v4f64_193b5d7f(<8 x double> %a, <8 x double> %b) {
1440 ; ALL-LABEL: shuffle_v4f64_193b5d7f:
1441 ; ALL: # BB#0:
1442 ; ALL-NEXT: vunpckhpd {{.*#+}} zmm0 = zmm0[1],zmm1[1],zmm0[3],zmm1[3],zmm0[5],zmm1[5],zmm0[7],zmm1[7]
1443 ; ALL-NEXT: retq
1444 %shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32>
1445 ret <8 x double> %shuffle
1446 }
1447
1448 define <8 x i64> @shuffle_v4i64_193b5d7f(<8 x i64> %a, <8 x i64> %b) {
1449 ; ALL-LABEL: shuffle_v4i64_193b5d7f:
1450 ; ALL: # BB#0:
1451 ; ALL-NEXT: vpunpckhqdq {{.*#+}} zmm0 = zmm0[1],zmm1[1],zmm0[3],zmm1[3],zmm0[5],zmm1[5],zmm0[7],zmm1[7]
1452 ; ALL-NEXT: retq
1453 %shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32>
1454 ret <8 x i64> %shuffle
1455 }