llvm.org GIT mirror llvm / 2938a00
Add a couple more heuristics to neuter machine cse some more. 1. Be careful with cse "cheap" expressions. e.g. constant materialization. Only cse them when the common expression is local or in a direct predecessor. We don't want cse of cheap instruction causing other expressions to be spilled. 2. Watch out for the case where the expression doesn't itself uses a virtual register. e.g. lea of frame object. If the common expression itself is used by copies (common for passing addresses to function calls), don't perform the cse. Since these expressions do not use a register, it creates a live range but doesn't close any, we want to be very careful with increasing register pressure. Note these are heuristics so machine cse doesn't make register allocator unhappy. Once we have proper live range splitting and re-materialization support in place, these should be evaluated again. Now machine cse is almost always a win on llvm nightly tests on x86 and x86_64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98121 91177308-0d34-0410-b5e6-96231b3b80d8 Evan Cheng 9 years ago
1 changed file(s) with 57 addition(s) and 13 deletion(s). Raw diff Collapse all Expand all
6060 MachineBasicBlock::const_iterator E);
6161 bool hasLivePhysRegDefUse(MachineInstr *MI, MachineBasicBlock *MBB);
6262 bool isCSECandidate(MachineInstr *MI);
63 bool isProfitableToCSE(unsigned Reg, MachineInstr *MI);
63 bool isProfitableToCSE(unsigned CSReg, unsigned Reg,
64 MachineInstr *CSMI, MachineInstr *MI);
6465 bool ProcessBlock(MachineDomTreeNode *Node);
6566 };
6667 } // end anonymous namespace
142143 return false;
143144 }
144145
146 /// hasLivePhysRegDefUse - Return true if the specified instruction read / write
147 /// physical registers (except for dead defs of physical registers).
145148 bool MachineCSE::hasLivePhysRegDefUse(MachineInstr *MI, MachineBasicBlock *MBB){
146149 unsigned PhysDef = 0;
147150 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
176179 return false;
177180 }
178181
182 static bool isCopy(const MachineInstr *MI, const TargetInstrInfo *TII) {
183 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
184 return TII->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) ||
185 MI->isExtractSubreg() || MI->isInsertSubreg() || MI->isSubregToReg();
186 }
187
179188 bool MachineCSE::isCSECandidate(MachineInstr *MI) {
180189 if (MI->isLabel() || MI->isPHI() || MI->isImplicitDef() ||
181190 MI->isKill() || MI->isInlineAsm())
182191 return false;
183192
184 // Ignore copies or instructions that read / write physical registers
185 // (except for dead defs of physical registers).
186 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
187 if (TII->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) ||
188 MI->isExtractSubreg() || MI->isInsertSubreg() || MI->isSubregToReg())
193 // Ignore copies.
194 if (isCopy(MI, TII))
189195 return false;
190196
191197 // Ignore stuff that we obviously can't move.
209215
210216 /// isProfitableToCSE - Return true if it's profitable to eliminate MI with a
211217 /// common expression that defines Reg.
212 bool MachineCSE::isProfitableToCSE(unsigned Reg, MachineInstr *MI) {
213 // FIXME: This "heuristic" works around the lack the live range splitting.
214 // If the common subexpression is used by PHIs, do not reuse it unless the
215 // defined value is already used in the BB of the new use.
218 bool MachineCSE::isProfitableToCSE(unsigned CSReg, unsigned Reg,
219 MachineInstr *CSMI, MachineInstr *MI) {
220 // FIXME: Heuristics that works around the lack the live range splitting.
221
222 // Heuristics #1: Don't cse "cheap" computating if the def is not local or in an
223 // immediate predecessor. We don't want to increase register pressure and end up
224 // causing other computation to be spilled.
225 if (MI->getDesc().isAsCheapAsAMove()) {
226 MachineBasicBlock *CSBB = CSMI->getParent();
227 MachineBasicBlock *BB = MI->getParent();
228 if (CSBB != BB &&
229 find(CSBB->succ_begin(), CSBB->succ_end(), BB) == CSBB->succ_end())
230 return false;
231 }
232
233 // Heuristics #2: If the expression doesn't not use a vr and the only use
234 // of the redundant computation are copies, do not cse.
235 bool HasVRegUse = false;
236 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
237 const MachineOperand &MO = MI->getOperand(i);
238 if (MO.isReg() && MO.isUse() && MO.getReg() &&
239 TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
240 HasVRegUse = true;
241 break;
242 }
243 }
244 if (!HasVRegUse) {
245 bool HasNonCopyUse = false;
246 for (MachineRegisterInfo::use_nodbg_iterator I = MRI->use_nodbg_begin(Reg),
247 E = MRI->use_nodbg_end(); I != E; ++I) {
248 MachineInstr *Use = &*I;
249 // Ignore copies.
250 if (!isCopy(Use, TII)) {
251 HasNonCopyUse = true;
252 break;
253 }
254 }
255 if (!HasNonCopyUse)
256 return false;
257 }
258
259 // Heuristics #3: If the common subexpression is used by PHIs, do not reuse
260 // it unless the defined value is already used in the BB of the new use.
216261 bool HasPHI = false;
217262 SmallPtrSet CSBBs;
218 for (MachineRegisterInfo::use_nodbg_iterator I =
219 MRI->use_nodbg_begin(Reg),
263 for (MachineRegisterInfo::use_nodbg_iterator I = MRI->use_nodbg_begin(CSReg),
220264 E = MRI->use_nodbg_end(); I != E; ++I) {
221265 MachineInstr *Use = &*I;
222266 HasPHI |= Use->isPHI();
281325 assert(TargetRegisterInfo::isVirtualRegister(OldReg) &&
282326 TargetRegisterInfo::isVirtualRegister(NewReg) &&
283327 "Do not CSE physical register defs!");
284 if (!isProfitableToCSE(NewReg, MI)) {
328 if (!isProfitableToCSE(NewReg, OldReg, CSMI, MI)) {
285329 DoCSE = false;
286330 break;
287331 }