llvm.org GIT mirror llvm / 2928650
Let each target decide byval alignment. For X86, it's 4-byte unless the aggregare contains SSE vector(s). For x86-64, it's max of 8 or alignment of the type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46286 91177308-0d34-0410-b5e6-96231b3b80d8 Evan Cheng 12 years ago
7 changed file(s) with 85 addition(s) and 5 deletion(s). Raw diff Collapse all Expand all
404404 return VT == MVT::iPTR ? PointerTy : VT;
405405 }
406406
407 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
408 /// function arguments in the caller parameter area.
409 virtual unsigned getByValTypeAlignment(const Type *Ty) const;
410
407411 /// getRegisterType - Return the type of registers that this ValueType will
408412 /// eventually require.
409413 MVT::ValueType getRegisterType(MVT::ValueType VT) const {
432436 }
433437 assert(0 && "Unsupported extended type!");
434438 }
435
439
436440 /// hasTargetDAGCombine - If true, the target has custom DAG combine
437441 /// transformations that it can perform for the specified node.
438442 bool hasTargetDAGCombine(ISD::NodeType NT) const {
671671 allowUnalignedMemoryAccesses = true; // x86 supports it!
672672 }
673673
674 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
675 /// the desired ByVal argument alignment.
676 static void getMaxByValAlign(const Type *Ty, unsigned &MaxAlign) {
677 if (MaxAlign == 16)
678 return;
679 if (const VectorType *VTy = dyn_cast(Ty)) {
680 if (VTy->getBitWidth() == 128)
681 MaxAlign = 16;
682 else if (VTy->getBitWidth() == 64)
683 if (MaxAlign < 8)
684 MaxAlign = 8;
685 } else if (const ArrayType *ATy = dyn_cast(Ty)) {
686 unsigned EltAlign = 0;
687 getMaxByValAlign(ATy->getElementType(), EltAlign);
688 if (EltAlign > MaxAlign)
689 MaxAlign = EltAlign;
690 } else if (const StructType *STy = dyn_cast(Ty)) {
691 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
692 unsigned EltAlign = 0;
693 getMaxByValAlign(STy->getElementType(i), EltAlign);
694 if (EltAlign > MaxAlign)
695 MaxAlign = EltAlign;
696 if (MaxAlign == 16)
697 break;
698 }
699 }
700 return;
701 }
702
703 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
704 /// function arguments in the caller parameter area. For X86, aggregates
705 /// that contains are placed at 16-byte boundaries while the rest are at
706 /// 4-byte boundaries.
707 unsigned X86TargetLowering::getByValTypeAlignment(const Type *Ty) const {
708 if (Subtarget->is64Bit())
709 return getTargetData()->getABITypeAlignment(Ty);
710 unsigned Align = 4;
711 getMaxByValAlign(Ty, Align);
712 return Align;
713 }
674714
675715 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
676716 /// jumptable.
321321 /// getStackPtrReg - Return the stack pointer register we are using: either
322322 /// ESP or RSP.
323323 unsigned getStackPtrReg() const { return X86StackPtr; }
324
325 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
326 /// function arguments in the caller parameter area. For X86, aggregates
327 /// that contains are placed at 16-byte boundaries while the rest are at
328 /// 4-byte boundaries.
329 virtual unsigned getByValTypeAlignment(const Type *Ty) const;
324330
325331 /// LowerOperation - Provide custom lowering hooks for some operations.
326332 ///
None ; RUN: llvm-as < %s | llc -march=x86-64 | grep rep.movsl | count 2
1 ; RUN: llvm-as < %s | llc -march=x86 | grep rep.movsw | count 2
0 ; RUN: llvm-as < %s | llc -march=x86-64 | grep rep.movsw | count 2
1 ; RUN: llvm-as < %s | llc -march=x86 | grep rep.movsl | count 2
22
33 %struct.s = type { i16, i16, i16, i16, i16, i16 }
44
None ; RUN: llvm-as < %s | llc -march=x86-64 | grep rep.movsl | count 2
1 ; RUN: llvm-as < %s | llc -march=x86 | grep rep.movsb | count 2
0 ; RUN: llvm-as < %s | llc -march=x86-64 | grep rep.movsb | count 2
1 ; RUN: llvm-as < %s | llc -march=x86 | grep rep.movsl | count 2
22
33 %struct.s = type { i8, i8, i8, i8, i8, i8 }
44
0 ; RUN: llvm-as < %s | llc -march=x86 | grep add | not grep 16
1
2 %struct.W = type { x86_fp80, x86_fp80 }
3 @B = global %struct.W { x86_fp80 0xK4001A000000000000000, x86_fp80 0xK4001C000000000000000 }, align 32
4 @.cpx = internal constant %struct.W { x86_fp80 0xK4001E000000000000000, x86_fp80 0xK40028000000000000000 }
5
6 define i32 @main() nounwind {
7 entry:
8 tail call void (i32, ...)* @bar( i32 3, %struct.W* byval @.cpx ) nounwind
9 tail call void (i32, ...)* @baz( i32 3, %struct.W* byval @B ) nounwind
10 ret i32 undef
11 }
12
13 declare void @bar(i32, ...)
14
15 declare void @baz(i32, ...)
0 ; RUN: llvm-as < %s | llc -march=x86 | grep add | grep 16
1
2 %struct.S = type { <2 x i64> }
3
4 define i32 @main() nounwind {
5 entry:
6 %s = alloca %struct.S ; <%struct.S*> [#uses=2]
7 %tmp15 = getelementptr %struct.S* %s, i32 0, i32 0 ; <<2 x i64>*> [#uses=1]
8 store <2 x i64> < i64 8589934595, i64 1 >, <2 x i64>* %tmp15, align 16
9 call void @t( i32 1, %struct.S* byval %s ) nounwind
10 ret i32 0
11 }
12
13 declare void @t(i32, %struct.S* byval )