llvm.org GIT mirror llvm / 28f08c9
ARM refactor away a bunch of VLD/VST pseudo instructions. With the new composite physical registers to represent arbitrary pairs of DPR registers, we don't need the pseudo-registers anymore. Get rid of a bunch of them that use DPR register pairs and just use the real instructions directly instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152045 91177308-0d34-0410-b5e6-96231b3b80d8 Jim Grosbach 8 years ago
13 changed file(s) with 241 addition(s) and 247 deletion(s). Raw diff Collapse all Expand all
251251 /// Reg so its sub-register of index SubIdx is Reg.
252252 unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx,
253253 const MCRegisterClass *RC) const {
254 for (const unsigned *SRs = getSuperRegisters(Reg); unsigned SR = *SRs;++SRs)
254 for (const uint16_t *SRs = getSuperRegisters(Reg); unsigned SR = *SRs;++SRs)
255255 if (Reg == getSubReg(SR, SubIdx) && RC->contains(SR))
256256 return SR;
257257 return 0;
759759 if (ARM::QPRRegClass.hasSubClassEq(RC)) {
760760 // Use aligned spills if the stack can be realigned.
761761 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
762 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q64Pseudo))
762 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q64))
763763 .addFrameIndex(FI).addImm(16)
764764 .addReg(SrcReg, getKillRegState(isKill))
765765 .addMemOperand(MMO));
844844 return MI->getOperand(0).getReg();
845845 }
846846 break;
847 case ARM::VST1q64Pseudo:
847 case ARM::VST1q64:
848848 if (MI->getOperand(0).isFI() &&
849849 MI->getOperand(2).getSubReg() == 0) {
850850 FrameIndex = MI->getOperand(0).getIndex();
908908 case 16:
909909 if (ARM::QPRRegClass.hasSubClassEq(RC)) {
910910 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
911 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q64Pseudo), DestReg)
911 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q64), DestReg)
912912 .addFrameIndex(FI).addImm(16)
913913 .addMemOperand(MMO));
914914 } else {
988988 return MI->getOperand(0).getReg();
989989 }
990990 break;
991 case ARM::VLD1q64Pseudo:
991 case ARM::VLD1q64:
992992 if (MI->getOperand(1).isFI() &&
993993 MI->getOperand(0).getSubReg() == 0) {
994994 FrameIndex = MI->getOperand(1).getIndex();
26932693 if (DefAlign < 8 && Subtarget.isCortexA9())
26942694 switch (DefMCID.getOpcode()) {
26952695 default: break;
2696 case ARM::VLD1q8Pseudo:
2697 case ARM::VLD1q16Pseudo:
2698 case ARM::VLD1q32Pseudo:
2699 case ARM::VLD1q64Pseudo:
2700 case ARM::VLD1q8PseudoWB_register:
2701 case ARM::VLD1q16PseudoWB_register:
2702 case ARM::VLD1q32PseudoWB_register:
2703 case ARM::VLD1q64PseudoWB_register:
2704 case ARM::VLD1q8PseudoWB_fixed:
2705 case ARM::VLD1q16PseudoWB_fixed:
2706 case ARM::VLD1q32PseudoWB_fixed:
2707 case ARM::VLD1q64PseudoWB_fixed:
2708 case ARM::VLD2d8Pseudo:
2709 case ARM::VLD2d16Pseudo:
2710 case ARM::VLD2d32Pseudo:
2696 case ARM::VLD1q8:
2697 case ARM::VLD1q16:
2698 case ARM::VLD1q32:
2699 case ARM::VLD1q64:
2700 case ARM::VLD1q8wb_register:
2701 case ARM::VLD1q16wb_register:
2702 case ARM::VLD1q32wb_register:
2703 case ARM::VLD1q64wb_register:
2704 case ARM::VLD1q8wb_fixed:
2705 case ARM::VLD1q16wb_fixed:
2706 case ARM::VLD1q32wb_fixed:
2707 case ARM::VLD1q64wb_fixed:
2708 case ARM::VLD2d8:
2709 case ARM::VLD2d16:
2710 case ARM::VLD2d32:
27112711 case ARM::VLD2q8Pseudo:
27122712 case ARM::VLD2q16Pseudo:
27132713 case ARM::VLD2q32Pseudo:
2714 case ARM::VLD2d8PseudoWB_fixed:
2715 case ARM::VLD2d16PseudoWB_fixed:
2716 case ARM::VLD2d32PseudoWB_fixed:
2714 case ARM::VLD2d8wb_fixed:
2715 case ARM::VLD2d16wb_fixed:
2716 case ARM::VLD2d32wb_fixed:
27172717 case ARM::VLD2q8PseudoWB_fixed:
27182718 case ARM::VLD2q16PseudoWB_fixed:
27192719 case ARM::VLD2q32PseudoWB_fixed:
2720 case ARM::VLD2d8PseudoWB_register:
2721 case ARM::VLD2d16PseudoWB_register:
2722 case ARM::VLD2d32PseudoWB_register:
2720 case ARM::VLD2d8wb_register:
2721 case ARM::VLD2d16wb_register:
2722 case ARM::VLD2d32wb_register:
27232723 case ARM::VLD2q8PseudoWB_register:
27242724 case ARM::VLD2q16PseudoWB_register:
27252725 case ARM::VLD2q32PseudoWB_register:
147147
148148 { ARM::VLD1d64QPseudo, ARM::VLD1d64Q, true, false, false, SingleSpc, 4, 1 ,false},
149149 { ARM::VLD1d64TPseudo, ARM::VLD1d64T, true, false, false, SingleSpc, 3, 1 ,false},
150 { ARM::VLD1q16Pseudo, ARM::VLD1q16, true, false, false, SingleSpc, 2, 4 ,false},
151 { ARM::VLD1q16PseudoWB_fixed, ARM::VLD1q16wb_fixed,true,false,false,SingleSpc, 2, 4 ,false},
152 { ARM::VLD1q16PseudoWB_register, ARM::VLD1q16wb_register, true, true, true, SingleSpc, 2, 4 ,false},
153 { ARM::VLD1q32Pseudo, ARM::VLD1q32, true, false, false, SingleSpc, 2, 2 ,false},
154 { ARM::VLD1q32PseudoWB_fixed, ARM::VLD1q32wb_fixed,true,false, false,SingleSpc, 2, 2 ,false},
155 { ARM::VLD1q32PseudoWB_register, ARM::VLD1q32wb_register, true, true, true, SingleSpc, 2, 2 ,false},
156 { ARM::VLD1q64Pseudo, ARM::VLD1q64, true, false, false, SingleSpc, 2, 1 ,false},
157 { ARM::VLD1q64PseudoWB_fixed, ARM::VLD1q64wb_fixed,true,false, false,SingleSpc, 2, 2 ,false},
158 { ARM::VLD1q64PseudoWB_register, ARM::VLD1q64wb_register, true, true, true, SingleSpc, 2, 1 ,false},
159 { ARM::VLD1q8Pseudo, ARM::VLD1q8, true, false, false, SingleSpc, 2, 8 ,false},
160 { ARM::VLD1q8PseudoWB_fixed, ARM::VLD1q8wb_fixed,true,false, false, SingleSpc, 2, 8 ,false},
161 { ARM::VLD1q8PseudoWB_register, ARM::VLD1q8wb_register,true,true, true,SingleSpc,2,8,false},
162150
163151 { ARM::VLD2DUPd16Pseudo, ARM::VLD2DUPd16, true, false, false, SingleSpc, 2, 4,false},
164152 { ARM::VLD2DUPd16PseudoWB_fixed, ARM::VLD2DUPd16wb_fixed, true, true, false, SingleSpc, 2, 4,false},
181169 { ARM::VLD2LNq32Pseudo, ARM::VLD2LNq32, true, false, false, EvenDblSpc, 2, 2 ,true},
182170 { ARM::VLD2LNq32Pseudo_UPD, ARM::VLD2LNq32_UPD, true, true, true, EvenDblSpc, 2, 2 ,true},
183171
184 { ARM::VLD2d16Pseudo, ARM::VLD2d16, true, false, false, SingleSpc, 2, 4 ,false},
185 { ARM::VLD2d16PseudoWB_fixed, ARM::VLD2d16wb_fixed, true, true, false, SingleSpc, 2, 4 ,false},
186 { ARM::VLD2d16PseudoWB_register, ARM::VLD2d16wb_register, true, true, true, SingleSpc, 2, 4 ,false},
187 { ARM::VLD2d32Pseudo, ARM::VLD2d32, true, false, false, SingleSpc, 2, 2 ,false},
188 { ARM::VLD2d32PseudoWB_fixed, ARM::VLD2d32wb_fixed, true, true, false, SingleSpc, 2, 2 ,false},
189 { ARM::VLD2d32PseudoWB_register, ARM::VLD2d32wb_register, true, true, true, SingleSpc, 2, 2 ,false},
190 { ARM::VLD2d8Pseudo, ARM::VLD2d8, true, false, false, SingleSpc, 2, 8 ,false},
191 { ARM::VLD2d8PseudoWB_fixed, ARM::VLD2d8wb_fixed, true, true, false, SingleSpc, 2, 8 ,false},
192 { ARM::VLD2d8PseudoWB_register, ARM::VLD2d8wb_register, true, true, true, SingleSpc, 2, 8 ,false},
193
194172 { ARM::VLD2q16Pseudo, ARM::VLD2q16, true, false, false, SingleSpc, 4, 4 ,false},
195173 { ARM::VLD2q16PseudoWB_fixed, ARM::VLD2q16wb_fixed, true, true, false, SingleSpc, 4, 4 ,false},
196174 { ARM::VLD2q16PseudoWB_register, ARM::VLD2q16wb_register, true, true, true, SingleSpc, 4, 4 ,false},
285263 { ARM::VST1d64TPseudoWB_fixed, ARM::VST1d64Twb_fixed, false, true, false, SingleSpc, 3, 1 ,false},
286264 { ARM::VST1d64TPseudoWB_register, ARM::VST1d64Twb_register, false, true, true, SingleSpc, 3, 1 ,false},
287265
288 { ARM::VST1q16Pseudo, ARM::VST1q16, false, false, false, SingleSpc, 2, 4 ,false},
289 { ARM::VST1q16PseudoWB_fixed, ARM::VST1q16wb_fixed, false, true, false, SingleSpc, 2, 4 ,false},
290 { ARM::VST1q16PseudoWB_register, ARM::VST1q16wb_register, false, true, true, SingleSpc, 2, 4 ,false},
291 { ARM::VST1q32Pseudo, ARM::VST1q32, false, false, false, SingleSpc, 2, 2 ,false},
292 { ARM::VST1q32PseudoWB_fixed, ARM::VST1q32wb_fixed, false, true, false, SingleSpc, 2, 2 ,false},
293 { ARM::VST1q32PseudoWB_register, ARM::VST1q32wb_register, false, true, true, SingleSpc, 2, 2 ,false},
294 { ARM::VST1q64Pseudo, ARM::VST1q64, false, false, false, SingleSpc, 2, 1 ,false},
295 { ARM::VST1q64PseudoWB_fixed, ARM::VST1q64wb_fixed, false, true, false, SingleSpc, 2, 1 ,false},
296 { ARM::VST1q64PseudoWB_register, ARM::VST1q64wb_register, false, true, true, SingleSpc, 2, 1 ,false},
297 { ARM::VST1q8Pseudo, ARM::VST1q8, false, false, false, SingleSpc, 2, 8 ,false},
298 { ARM::VST1q8PseudoWB_fixed, ARM::VST1q8wb_fixed, false, true, false, SingleSpc, 2, 8 ,false},
299 { ARM::VST1q8PseudoWB_register, ARM::VST1q8wb_register, false, true, true, SingleSpc, 2, 8 ,false},
300
301266 { ARM::VST2LNd16Pseudo, ARM::VST2LNd16, false, false, false, SingleSpc, 2, 4 ,true},
302267 { ARM::VST2LNd16Pseudo_UPD, ARM::VST2LNd16_UPD, false, true, true, SingleSpc, 2, 4 ,true},
303268 { ARM::VST2LNd32Pseudo, ARM::VST2LNd32, false, false, false, SingleSpc, 2, 2 ,true},
308273 { ARM::VST2LNq16Pseudo_UPD, ARM::VST2LNq16_UPD, false, true, true, EvenDblSpc, 2, 4,true},
309274 { ARM::VST2LNq32Pseudo, ARM::VST2LNq32, false, false, false, EvenDblSpc, 2, 2,true},
310275 { ARM::VST2LNq32Pseudo_UPD, ARM::VST2LNq32_UPD, false, true, true, EvenDblSpc, 2, 2,true},
311
312 { ARM::VST2d16Pseudo, ARM::VST2d16, false, false, false, SingleSpc, 2, 4 ,false},
313 { ARM::VST2d16PseudoWB_fixed, ARM::VST2d16wb_fixed, false, true, false, SingleSpc, 2, 4 ,false},
314 { ARM::VST2d16PseudoWB_register, ARM::VST2d16wb_register, false, true, true, SingleSpc, 2, 4 ,false},
315 { ARM::VST2d32Pseudo, ARM::VST2d32, false, false, false, SingleSpc, 2, 2 ,false},
316 { ARM::VST2d32PseudoWB_fixed, ARM::VST2d32wb_fixed, false, true, false, SingleSpc, 2, 2 ,false},
317 { ARM::VST2d32PseudoWB_register, ARM::VST2d32wb_register, false, true, true, SingleSpc, 2, 2 ,false},
318 { ARM::VST2d8Pseudo, ARM::VST2d8, false, false, false, SingleSpc, 2, 8 ,false},
319 { ARM::VST2d8PseudoWB_fixed, ARM::VST2d8wb_fixed, false, true, false, SingleSpc, 2, 8 ,false},
320 { ARM::VST2d8PseudoWB_register, ARM::VST2d8wb_register, false, true, true, SingleSpc, 2, 8 ,false},
321276
322277 { ARM::VST2q16Pseudo, ARM::VST2q16, false, false, false, SingleSpc, 4, 4 ,false},
323278 { ARM::VST2q16PseudoWB_fixed, ARM::VST2q16wb_fixed, false, true, false, SingleSpc, 4, 4 ,false},
10931048 return true;
10941049 }
10951050
1096 case ARM::VLD1q8Pseudo:
1097 case ARM::VLD1q16Pseudo:
1098 case ARM::VLD1q32Pseudo:
1099 case ARM::VLD1q64Pseudo:
1100 case ARM::VLD1q8PseudoWB_register:
1101 case ARM::VLD1q16PseudoWB_register:
1102 case ARM::VLD1q32PseudoWB_register:
1103 case ARM::VLD1q64PseudoWB_register:
1104 case ARM::VLD1q8PseudoWB_fixed:
1105 case ARM::VLD1q16PseudoWB_fixed:
1106 case ARM::VLD1q32PseudoWB_fixed:
1107 case ARM::VLD1q64PseudoWB_fixed:
1108 case ARM::VLD2d8Pseudo:
1109 case ARM::VLD2d16Pseudo:
1110 case ARM::VLD2d32Pseudo:
11111051 case ARM::VLD2q8Pseudo:
11121052 case ARM::VLD2q16Pseudo:
11131053 case ARM::VLD2q32Pseudo:
1114 case ARM::VLD2d8PseudoWB_fixed:
1115 case ARM::VLD2d16PseudoWB_fixed:
1116 case ARM::VLD2d32PseudoWB_fixed:
11171054 case ARM::VLD2q8PseudoWB_fixed:
11181055 case ARM::VLD2q16PseudoWB_fixed:
11191056 case ARM::VLD2q32PseudoWB_fixed:
1120 case ARM::VLD2d8PseudoWB_register:
1121 case ARM::VLD2d16PseudoWB_register:
1122 case ARM::VLD2d32PseudoWB_register:
11231057 case ARM::VLD2q8PseudoWB_register:
11241058 case ARM::VLD2q16PseudoWB_register:
11251059 case ARM::VLD2q32PseudoWB_register:
11881122 ExpandVLD(MBBI);
11891123 return true;
11901124
1191 case ARM::VST1q8Pseudo:
1192 case ARM::VST1q16Pseudo:
1193 case ARM::VST1q32Pseudo:
1194 case ARM::VST1q64Pseudo:
1195 case ARM::VST1q8PseudoWB_fixed:
1196 case ARM::VST1q16PseudoWB_fixed:
1197 case ARM::VST1q32PseudoWB_fixed:
1198 case ARM::VST1q64PseudoWB_fixed:
1199 case ARM::VST1q8PseudoWB_register:
1200 case ARM::VST1q16PseudoWB_register:
1201 case ARM::VST1q32PseudoWB_register:
1202 case ARM::VST1q64PseudoWB_register:
1203 case ARM::VST2d8Pseudo:
1204 case ARM::VST2d16Pseudo:
1205 case ARM::VST2d32Pseudo:
12061125 case ARM::VST2q8Pseudo:
12071126 case ARM::VST2q16Pseudo:
12081127 case ARM::VST2q32Pseudo:
1209 case ARM::VST2d8PseudoWB_fixed:
1210 case ARM::VST2d16PseudoWB_fixed:
1211 case ARM::VST2d32PseudoWB_fixed:
12121128 case ARM::VST2q8PseudoWB_fixed:
12131129 case ARM::VST2q16PseudoWB_fixed:
12141130 case ARM::VST2q32PseudoWB_fixed:
1215 case ARM::VST2d8PseudoWB_register:
1216 case ARM::VST2d16PseudoWB_register:
1217 case ARM::VST2d32PseudoWB_register:
12181131 case ARM::VST2q8PseudoWB_register:
12191132 case ARM::VST2q16PseudoWB_register:
12201133 case ARM::VST2q32PseudoWB_register:
13321245 ExpandLaneOp(MBBI);
13331246 return true;
13341247
1335 case ARM::VTBL2Pseudo: ExpandVTBL(MBBI, ARM::VTBL2, false); return true;
13361248 case ARM::VTBL3Pseudo: ExpandVTBL(MBBI, ARM::VTBL3, false); return true;
13371249 case ARM::VTBL4Pseudo: ExpandVTBL(MBBI, ARM::VTBL4, false); return true;
1338 case ARM::VTBX2Pseudo: ExpandVTBL(MBBI, ARM::VTBX2, true); return true;
13391250 case ARM::VTBX3Pseudo: ExpandVTBL(MBBI, ARM::VTBX3, true); return true;
13401251 case ARM::VTBX4Pseudo: ExpandVTBL(MBBI, ARM::VTBX4, true); return true;
13411252 }
829829 ARM::QPRRegisterClass);
830830 MBB.addLiveIn(SupReg);
831831 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VST1q64))
832 .addReg(ARM::R4).addImm(16).addReg(NextReg)
833 .addReg(SupReg, RegState::ImplicitKill));
832 .addReg(ARM::R4).addImm(16).addReg(SupReg));
834833 NextReg += 2;
835834 NumAlignedDPRCS2Regs -= 2;
836835 }
943942 if (NumAlignedDPRCS2Regs >= 2) {
944943 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
945944 ARM::QPRRegisterClass);
946 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VLD1q64), NextReg)
947 .addReg(ARM::R4).addImm(16)
948 .addReg(SupReg, RegState::ImplicitDefine));
945 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VLD1q64), SupReg)
946 .addReg(ARM::R4).addImm(16));
949947 NextReg += 2;
950948 NumAlignedDPRCS2Regs -= 2;
951949 }
15621562 case ARM::VLD1q16wb_fixed: return ARM::VLD1q16wb_register;
15631563 case ARM::VLD1q32wb_fixed: return ARM::VLD1q32wb_register;
15641564 case ARM::VLD1q64wb_fixed: return ARM::VLD1q64wb_register;
1565 case ARM::VLD1q8PseudoWB_fixed: return ARM::VLD1q8PseudoWB_register;
1566 case ARM::VLD1q16PseudoWB_fixed: return ARM::VLD1q16PseudoWB_register;
1567 case ARM::VLD1q32PseudoWB_fixed: return ARM::VLD1q32PseudoWB_register;
1568 case ARM::VLD1q64PseudoWB_fixed: return ARM::VLD1q64PseudoWB_register;
15691565
15701566 case ARM::VST1d8wb_fixed: return ARM::VST1d8wb_register;
15711567 case ARM::VST1d16wb_fixed: return ARM::VST1d16wb_register;
15751571 case ARM::VST1q16wb_fixed: return ARM::VST1q16wb_register;
15761572 case ARM::VST1q32wb_fixed: return ARM::VST1q32wb_register;
15771573 case ARM::VST1q64wb_fixed: return ARM::VST1q64wb_register;
1578 case ARM::VST1q8PseudoWB_fixed: return ARM::VST1q8PseudoWB_register;
1579 case ARM::VST1q16PseudoWB_fixed: return ARM::VST1q16PseudoWB_register;
1580 case ARM::VST1q32PseudoWB_fixed: return ARM::VST1q32PseudoWB_register;
1581 case ARM::VST1q64PseudoWB_fixed: return ARM::VST1q64PseudoWB_register;
15821574 case ARM::VST1d64TPseudoWB_fixed: return ARM::VST1d64TPseudoWB_register;
15831575 case ARM::VST1d64QPseudoWB_fixed: return ARM::VST1d64QPseudoWB_register;
15841576
1585 case ARM::VLD2d8PseudoWB_fixed: return ARM::VLD2d8PseudoWB_register;
1586 case ARM::VLD2d16PseudoWB_fixed: return ARM::VLD2d16PseudoWB_register;
1587 case ARM::VLD2d32PseudoWB_fixed: return ARM::VLD2d32PseudoWB_register;
1577 case ARM::VLD2d8wb_fixed: return ARM::VLD2d8wb_register;
1578 case ARM::VLD2d16wb_fixed: return ARM::VLD2d16wb_register;
1579 case ARM::VLD2d32wb_fixed: return ARM::VLD2d32wb_register;
15881580 case ARM::VLD2q8PseudoWB_fixed: return ARM::VLD2q8PseudoWB_register;
15891581 case ARM::VLD2q16PseudoWB_fixed: return ARM::VLD2q16PseudoWB_register;
15901582 case ARM::VLD2q32PseudoWB_fixed: return ARM::VLD2q32PseudoWB_register;
15911583
1592 case ARM::VST2d8PseudoWB_fixed: return ARM::VST2d8PseudoWB_register;
1593 case ARM::VST2d16PseudoWB_fixed: return ARM::VST2d16PseudoWB_register;
1594 case ARM::VST2d32PseudoWB_fixed: return ARM::VST2d32PseudoWB_register;
1584 case ARM::VST2d8wb_fixed: return ARM::VST2d8wb_register;
1585 case ARM::VST2d16wb_fixed: return ARM::VST2d16wb_register;
1586 case ARM::VST2d32wb_fixed: return ARM::VST2d32wb_register;
15951587 case ARM::VST2q8PseudoWB_fixed: return ARM::VST2q8PseudoWB_register;
15961588 case ARM::VST2q16PseudoWB_fixed: return ARM::VST2q16PseudoWB_register;
15971589 case ARM::VST2q32PseudoWB_fixed: return ARM::VST2q32PseudoWB_register;
16721664 Opc = getVLDSTRegisterUpdateOpcode(Opc);
16731665 // We use a VLD1 for v1i64 even if the pseudo says vld2/3/4, so
16741666 // check for that explicitly too. Horribly hacky, but temporary.
1675 if ((NumVecs != 1 && NumVecs != 2 && Opc != ARM::VLD1q64PseudoWB_fixed) ||
1667 if ((NumVecs != 1 && NumVecs != 2 && Opc != ARM::VLD1q64wb_fixed) ||
16761668 !isa(Inc.getNode()))
16771669 Ops.push_back(isa(Inc.getNode()) ? Reg0 : Inc);
16781670 }
18221814 Opc = getVLDSTRegisterUpdateOpcode(Opc);
18231815 // We use a VST1 for v1i64 even if the pseudo says vld2/3/4, so
18241816 // check for that explicitly too. Horribly hacky, but temporary.
1825 if ((NumVecs > 2 && Opc != ARM::VST1q64PseudoWB_fixed) ||
1817 if ((NumVecs > 2 && Opc != ARM::VST1q64wb_fixed) ||
18261818 !isa(Inc.getNode()))
18271819 Ops.push_back(isa(Inc.getNode()) ? Reg0 : Inc);
18281820 }
29372929 case ARMISD::VLD1_UPD: {
29382930 unsigned DOpcodes[] = { ARM::VLD1d8wb_fixed, ARM::VLD1d16wb_fixed,
29392931 ARM::VLD1d32wb_fixed, ARM::VLD1d64wb_fixed };
2940 unsigned QOpcodes[] = { ARM::VLD1q8PseudoWB_fixed,
2941 ARM::VLD1q16PseudoWB_fixed,
2942 ARM::VLD1q32PseudoWB_fixed,
2943 ARM::VLD1q64PseudoWB_fixed };
2932 unsigned QOpcodes[] = { ARM::VLD1q8wb_fixed,
2933 ARM::VLD1q16wb_fixed,
2934 ARM::VLD1q32wb_fixed,
2935 ARM::VLD1q64wb_fixed };
29442936 return SelectVLD(N, true, 1, DOpcodes, QOpcodes, 0);
29452937 }
29462938
29472939 case ARMISD::VLD2_UPD: {
2948 unsigned DOpcodes[] = { ARM::VLD2d8PseudoWB_fixed,
2949 ARM::VLD2d16PseudoWB_fixed,
2950 ARM::VLD2d32PseudoWB_fixed,
2951 ARM::VLD1q64PseudoWB_fixed};
2940 unsigned DOpcodes[] = { ARM::VLD2d8wb_fixed,
2941 ARM::VLD2d16wb_fixed,
2942 ARM::VLD2d32wb_fixed,
2943 ARM::VLD1q64wb_fixed};
29522944 unsigned QOpcodes[] = { ARM::VLD2q8PseudoWB_fixed,
29532945 ARM::VLD2q16PseudoWB_fixed,
29542946 ARM::VLD2q32PseudoWB_fixed };
29572949
29582950 case ARMISD::VLD3_UPD: {
29592951 unsigned DOpcodes[] = { ARM::VLD3d8Pseudo_UPD, ARM::VLD3d16Pseudo_UPD,
2960 ARM::VLD3d32Pseudo_UPD, ARM::VLD1q64PseudoWB_fixed};
2952 ARM::VLD3d32Pseudo_UPD, ARM::VLD1q64wb_fixed};
29612953 unsigned QOpcodes0[] = { ARM::VLD3q8Pseudo_UPD,
29622954 ARM::VLD3q16Pseudo_UPD,
29632955 ARM::VLD3q32Pseudo_UPD };
29692961
29702962 case ARMISD::VLD4_UPD: {
29712963 unsigned DOpcodes[] = { ARM::VLD4d8Pseudo_UPD, ARM::VLD4d16Pseudo_UPD,
2972 ARM::VLD4d32Pseudo_UPD, ARM::VLD1q64PseudoWB_fixed};
2964 ARM::VLD4d32Pseudo_UPD, ARM::VLD1q64wb_fixed};
29732965 unsigned QOpcodes0[] = { ARM::VLD4q8Pseudo_UPD,
29742966 ARM::VLD4q16Pseudo_UPD,
29752967 ARM::VLD4q32Pseudo_UPD };
30062998 case ARMISD::VST1_UPD: {
30072999 unsigned DOpcodes[] = { ARM::VST1d8wb_fixed, ARM::VST1d16wb_fixed,
30083000 ARM::VST1d32wb_fixed, ARM::VST1d64wb_fixed };
3009 unsigned QOpcodes[] = { ARM::VST1q8PseudoWB_fixed,
3010 ARM::VST1q16PseudoWB_fixed,
3011 ARM::VST1q32PseudoWB_fixed,
3012 ARM::VST1q64PseudoWB_fixed };
3001 unsigned QOpcodes[] = { ARM::VST1q8wb_fixed,
3002 ARM::VST1q16wb_fixed,
3003 ARM::VST1q32wb_fixed,
3004 ARM::VST1q64wb_fixed };
30133005 return SelectVST(N, true, 1, DOpcodes, QOpcodes, 0);
30143006 }
30153007
30163008 case ARMISD::VST2_UPD: {
3017 unsigned DOpcodes[] = { ARM::VST2d8PseudoWB_fixed,
3018 ARM::VST2d16PseudoWB_fixed,
3019 ARM::VST2d32PseudoWB_fixed,
3020 ARM::VST1q64PseudoWB_fixed};
3009 unsigned DOpcodes[] = { ARM::VST2d8wb_fixed,
3010 ARM::VST2d16wb_fixed,
3011 ARM::VST2d32wb_fixed,
3012 ARM::VST1q64wb_fixed};
30213013 unsigned QOpcodes[] = { ARM::VST2q8PseudoWB_fixed,
30223014 ARM::VST2q16PseudoWB_fixed,
30233015 ARM::VST2q32PseudoWB_fixed };
31873179 case Intrinsic::arm_neon_vld1: {
31883180 unsigned DOpcodes[] = { ARM::VLD1d8, ARM::VLD1d16,
31893181 ARM::VLD1d32, ARM::VLD1d64 };
3190 unsigned QOpcodes[] = { ARM::VLD1q8Pseudo, ARM::VLD1q16Pseudo,
3191 ARM::VLD1q32Pseudo, ARM::VLD1q64Pseudo };
3182 unsigned QOpcodes[] = { ARM::VLD1q8, ARM::VLD1q16,
3183 ARM::VLD1q32, ARM::VLD1q64};
31923184 return SelectVLD(N, false, 1, DOpcodes, QOpcodes, 0);
31933185 }
31943186
31953187 case Intrinsic::arm_neon_vld2: {
3196 unsigned DOpcodes[] = { ARM::VLD2d8Pseudo, ARM::VLD2d16Pseudo,
3197 ARM::VLD2d32Pseudo, ARM::VLD1q64Pseudo };
3188 unsigned DOpcodes[] = { ARM::VLD2d8, ARM::VLD2d16,
3189 ARM::VLD2d32, ARM::VLD1q64 };
31983190 unsigned QOpcodes[] = { ARM::VLD2q8Pseudo, ARM::VLD2q16Pseudo,
31993191 ARM::VLD2q32Pseudo };
32003192 return SelectVLD(N, false, 2, DOpcodes, QOpcodes, 0);
32483240 case Intrinsic::arm_neon_vst1: {
32493241 unsigned DOpcodes[] = { ARM::VST1d8, ARM::VST1d16,
32503242 ARM::VST1d32, ARM::VST1d64 };
3251 unsigned QOpcodes[] = { ARM::VST1q8Pseudo, ARM::VST1q16Pseudo,
3252 ARM::VST1q32Pseudo, ARM::VST1q64Pseudo };
3243 unsigned QOpcodes[] = { ARM::VST1q8, ARM::VST1q16,
3244 ARM::VST1q32, ARM::VST1q64 };
32533245 return SelectVST(N, false, 1, DOpcodes, QOpcodes, 0);
32543246 }
32553247
32563248 case Intrinsic::arm_neon_vst2: {
3257 unsigned DOpcodes[] = { ARM::VST2d8Pseudo, ARM::VST2d16Pseudo,
3258 ARM::VST2d32Pseudo, ARM::VST1q64Pseudo };
3249 unsigned DOpcodes[] = { ARM::VST2d8, ARM::VST2d16,
3250 ARM::VST2d32, ARM::VST1q64 };
32593251 unsigned QOpcodes[] = { ARM::VST2q8Pseudo, ARM::VST2q16Pseudo,
32603252 ARM::VST2q32Pseudo };
32613253 return SelectVST(N, false, 2, DOpcodes, QOpcodes, 0);
33163308 break;
33173309
33183310 case Intrinsic::arm_neon_vtbl2:
3319 return SelectVTBL(N, false, 2, ARM::VTBL2Pseudo);
3311 return SelectVTBL(N, false, 2, ARM::VTBL2);
33203312 case Intrinsic::arm_neon_vtbl3:
33213313 return SelectVTBL(N, false, 3, ARM::VTBL3Pseudo);
33223314 case Intrinsic::arm_neon_vtbl4:
33233315 return SelectVTBL(N, false, 4, ARM::VTBL4Pseudo);
33243316
33253317 case Intrinsic::arm_neon_vtbx2:
3326 return SelectVTBL(N, true, 2, ARM::VTBX2Pseudo);
3318 return SelectVTBL(N, true, 2, ARM::VTBX2);
33273319 case Intrinsic::arm_neon_vtbx3:
33283320 return SelectVTBL(N, true, 3, ARM::VTBX3Pseudo);
33293321 case Intrinsic::arm_neon_vtbx4:
33573349 Ops.push_back(N->getOperand(2));
33583350 Ops.push_back(getAL(CurDAG)); // Predicate
33593351 Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // Predicate Register
3360 return CurDAG->getMachineNode(ARM::VTBL2Pseudo, dl, VT,
3352 return CurDAG->getMachineNode(ARM::VTBL2, dl, VT,
33613353 Ops.data(), Ops.size());
33623354 }
33633355
9595 }
9696 def VecListTwoD : RegisterOperand {
9797 let ParserMatchClass = VecListTwoDAsmOperand;
98 }
99 // FIXME: Replace all VecListTwoD with VecListDPair
100 def VecListDPairAsmOperand : AsmOperandClass {
101 let Name = "VecListDPair";
102 let ParserMethod = "parseVectorList";
103 let RenderMethod = "addVecListOperands";
104 }
105 def VecListDPair : RegisterOperand {
106 let ParserMatchClass = VecListDPairAsmOperand;
98107 }
99108 // Register list of three sequential D registers.
100109 def VecListThreeDAsmOperand : AsmOperandClass {
592601 let DecoderMethod = "DecodeVLDInstruction";
593602 }
594603 class VLD1Q op7_4, string Dt>
595 : NLdSt<0,0b10,0b1010,op7_4, (outs VecListTwoD:$Vd),
604 : NLdSt<0,0b10,0b1010,op7_4, (outs VecListDPair:$Vd),
596605 (ins addrmode6:$Rn), IIC_VLD1x2,
597606 "vld1", Dt, "$Vd, $Rn", "", []> {
598607 let Rm = 0b1111;
609618 def VLD1q16 : VLD1Q<{0,1,?,?}, "16">;
610619 def VLD1q32 : VLD1Q<{1,0,?,?}, "32">;
611620 def VLD1q64 : VLD1Q<{1,1,?,?}, "64">;
612
613 def VLD1q8Pseudo : VLDQPseudo;
614 def VLD1q16Pseudo : VLDQPseudo;
615 def VLD1q32Pseudo : VLDQPseudo;
616 def VLD1q64Pseudo : VLDQPseudo;
617621
618622 // ...with address register writeback:
619623 multiclass VLD1DWB op7_4, string Dt> {
636640 }
637641 }
638642 multiclass VLD1QWB op7_4, string Dt> {
639 def _fixed : NLdSt<0,0b10,0b1010,op7_4, (outs VecListTwoD:$Vd, GPR:$wb),
643 def _fixed : NLdSt<0,0b10,0b1010,op7_4, (outs VecListDPair:$Vd, GPR:$wb),
640644 (ins addrmode6:$Rn), IIC_VLD1x2u,
641645 "vld1", Dt, "$Vd, $Rn!",
642646 "$Rn.addr = $wb", []> {
645649 let DecoderMethod = "DecodeVLDInstruction";
646650 let AsmMatchConverter = "cvtVLDwbFixed";
647651 }
648 def _register : NLdSt<0,0b10,0b1010,op7_4, (outs VecListTwoD:$Vd, GPR:$wb),
652 def _register : NLdSt<0,0b10,0b1010,op7_4, (outs VecListDPair:$Vd, GPR:$wb),
649653 (ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1x2u,
650654 "vld1", Dt, "$Vd, $Rn, $Rm",
651655 "$Rn.addr = $wb", []> {
663667 defm VLD1q16wb : VLD1QWB<{0,1,?,?}, "16">;
664668 defm VLD1q32wb : VLD1QWB<{1,0,?,?}, "32">;
665669 defm VLD1q64wb : VLD1QWB<{1,1,?,?}, "64">;
666
667 def VLD1q8PseudoWB_fixed : VLDQWBfixedPseudo;
668 def VLD1q16PseudoWB_fixed : VLDQWBfixedPseudo;
669 def VLD1q32PseudoWB_fixed : VLDQWBfixedPseudo;
670 def VLD1q64PseudoWB_fixed : VLDQWBfixedPseudo;
671 def VLD1q8PseudoWB_register : VLDQWBregisterPseudo;
672 def VLD1q16PseudoWB_register : VLDQWBregisterPseudo;
673 def VLD1q32PseudoWB_register : VLDQWBregisterPseudo;
674 def VLD1q64PseudoWB_register : VLDQWBregisterPseudo;
675670
676671 // ...with 3 registers
677672 class VLD1D3 op7_4, string Dt>
766761 let DecoderMethod = "DecodeVLDInstruction";
767762 }
768763
769 def VLD2d8 : VLD2<0b1000, {0,0,?,?}, "8", VecListTwoD, IIC_VLD2>;
770 def VLD2d16 : VLD2<0b1000, {0,1,?,?}, "16", VecListTwoD, IIC_VLD2>;
771 def VLD2d32 : VLD2<0b1000, {1,0,?,?}, "32", VecListTwoD, IIC_VLD2>;
764 def VLD2d8 : VLD2<0b1000, {0,0,?,?}, "8", VecListDPair, IIC_VLD2>;
765 def VLD2d16 : VLD2<0b1000, {0,1,?,?}, "16", VecListDPair, IIC_VLD2>;
766 def VLD2d32 : VLD2<0b1000, {1,0,?,?}, "32", VecListDPair, IIC_VLD2>;
772767
773768 def VLD2q8 : VLD2<0b0011, {0,0,?,?}, "8", VecListFourD, IIC_VLD2x2>;
774769 def VLD2q16 : VLD2<0b0011, {0,1,?,?}, "16", VecListFourD, IIC_VLD2x2>;
775770 def VLD2q32 : VLD2<0b0011, {1,0,?,?}, "32", VecListFourD, IIC_VLD2x2>;
776
777 def VLD2d8Pseudo : VLDQPseudo;
778 def VLD2d16Pseudo : VLDQPseudo;
779 def VLD2d32Pseudo : VLDQPseudo;
780771
781772 def VLD2q8Pseudo : VLDQQPseudo;
782773 def VLD2q16Pseudo : VLDQQPseudo;
804795 }
805796 }
806797
807 defm VLD2d8wb : VLD2WB<0b1000, {0,0,?,?}, "8", VecListTwoD, IIC_VLD2u>;
808 defm VLD2d16wb : VLD2WB<0b1000, {0,1,?,?}, "16", VecListTwoD, IIC_VLD2u>;
809 defm VLD2d32wb : VLD2WB<0b1000, {1,0,?,?}, "32", VecListTwoD, IIC_VLD2u>;
798 defm VLD2d8wb : VLD2WB<0b1000, {0,0,?,?}, "8", VecListDPair, IIC_VLD2u>;
799 defm VLD2d16wb : VLD2WB<0b1000, {0,1,?,?}, "16", VecListDPair, IIC_VLD2u>;
800 defm VLD2d32wb : VLD2WB<0b1000, {1,0,?,?}, "32", VecListDPair, IIC_VLD2u>;
810801
811802 defm VLD2q8wb : VLD2WB<0b0011, {0,0,?,?}, "8", VecListFourD, IIC_VLD2x2u>;
812803 defm VLD2q16wb : VLD2WB<0b0011, {0,1,?,?}, "16", VecListFourD, IIC_VLD2x2u>;
813804 defm VLD2q32wb : VLD2WB<0b0011, {1,0,?,?}, "32", VecListFourD, IIC_VLD2x2u>;
814
815 def VLD2d8PseudoWB_fixed : VLDQWBfixedPseudo;
816 def VLD2d16PseudoWB_fixed : VLDQWBfixedPseudo;
817 def VLD2d32PseudoWB_fixed : VLDQWBfixedPseudo;
818 def VLD2d8PseudoWB_register : VLDQWBregisterPseudo;
819 def VLD2d16PseudoWB_register : VLDQWBregisterPseudo;
820 def VLD2d32PseudoWB_register : VLDQWBregisterPseudo;
821805
822806 def VLD2q8PseudoWB_fixed : VLDQQWBfixedPseudo;
823807 def VLD2q16PseudoWB_fixed : VLDQQWBfixedPseudo;
15961580 let DecoderMethod = "DecodeVSTInstruction";
15971581 }
15981582 class VST1Q op7_4, string Dt>
1599 : NLdSt<0,0b00,0b1010,op7_4, (outs), (ins addrmode6:$Rn, VecListTwoD:$Vd),
1583 : NLdSt<0,0b00,0b1010,op7_4, (outs), (ins addrmode6:$Rn, VecListDPair:$Vd),
16001584 IIC_VST1x2, "vst1", Dt, "$Vd, $Rn", "", []> {
16011585 let Rm = 0b1111;
16021586 let Inst{5-4} = Rn{5-4};
16121596 def VST1q16 : VST1Q<{0,1,?,?}, "16">;
16131597 def VST1q32 : VST1Q<{1,0,?,?}, "32">;
16141598 def VST1q64 : VST1Q<{1,1,?,?}, "64">;
1615
1616 def VST1q8Pseudo : VSTQPseudo;
1617 def VST1q16Pseudo : VSTQPseudo;
1618 def VST1q32Pseudo : VSTQPseudo;
1619 def VST1q64Pseudo : VSTQPseudo;
16201599
16211600 // ...with address register writeback:
16221601 multiclass VST1DWB op7_4, string Dt> {
16411620 }
16421621 multiclass VST1QWB op7_4, string Dt> {
16431622 def _fixed : NLdSt<0,0b00,0b1010,op7_4, (outs GPR:$wb),
1644 (ins addrmode6:$Rn, VecListTwoD:$Vd), IIC_VLD1x2u,
1623 (ins addrmode6:$Rn, VecListDPair:$Vd), IIC_VLD1x2u,
16451624 "vst1", Dt, "$Vd, $Rn!",
16461625 "$Rn.addr = $wb", []> {
16471626 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
16501629 let AsmMatchConverter = "cvtVSTwbFixed";
16511630 }
16521631 def _register : NLdSt<0,0b00,0b1010,op7_4, (outs GPR:$wb),
1653 (ins addrmode6:$Rn, rGPR:$Rm, VecListTwoD:$Vd),
1632 (ins addrmode6:$Rn, rGPR:$Rm, VecListDPair:$Vd),
16541633 IIC_VLD1x2u,
16551634 "vst1", Dt, "$Vd, $Rn, $Rm",
16561635 "$Rn.addr = $wb", []> {
16691648 defm VST1q16wb : VST1QWB<{0,1,?,?}, "16">;
16701649 defm VST1q32wb : VST1QWB<{1,0,?,?}, "32">;
16711650 defm VST1q64wb : VST1QWB<{1,1,?,?}, "64">;
1672
1673 def VST1q8PseudoWB_fixed : VSTQWBfixedPseudo;
1674 def VST1q16PseudoWB_fixed : VSTQWBfixedPseudo;
1675 def VST1q32PseudoWB_fixed : VSTQWBfixedPseudo;
1676 def VST1q64PseudoWB_fixed : VSTQWBfixedPseudo;
1677 def VST1q8PseudoWB_register : VSTQWBregisterPseudo;
1678 def VST1q16PseudoWB_register : VSTQWBregisterPseudo;
1679 def VST1q32PseudoWB_register : VSTQWBregisterPseudo;
1680 def VST1q64PseudoWB_register : VSTQWBregisterPseudo;
16811651
16821652 // ...with 3 registers
16831653 class VST1D3 op7_4, string Dt>
17781748 let DecoderMethod = "DecodeVSTInstruction";
17791749 }
17801750
1781 def VST2d8 : VST2<0b1000, {0,0,?,?}, "8", VecListTwoD, IIC_VST2>;
1782 def VST2d16 : VST2<0b1000, {0,1,?,?}, "16", VecListTwoD, IIC_VST2>;
1783 def VST2d32 : VST2<0b1000, {1,0,?,?}, "32", VecListTwoD, IIC_VST2>;
1751 def VST2d8 : VST2<0b1000, {0,0,?,?}, "8", VecListDPair, IIC_VST2>;
1752 def VST2d16 : VST2<0b1000, {0,1,?,?}, "16", VecListDPair, IIC_VST2>;
1753 def VST2d32 : VST2<0b1000, {1,0,?,?}, "32", VecListDPair, IIC_VST2>;
17841754
17851755 def VST2q8 : VST2<0b0011, {0,0,?,?}, "8", VecListFourD, IIC_VST2x2>;
17861756 def VST2q16 : VST2<0b0011, {0,1,?,?}, "16", VecListFourD, IIC_VST2x2>;
17871757 def VST2q32 : VST2<0b0011, {1,0,?,?}, "32", VecListFourD, IIC_VST2x2>;
1788
1789 def VST2d8Pseudo : VSTQPseudo;
1790 def VST2d16Pseudo : VSTQPseudo;
1791 def VST2d32Pseudo : VSTQPseudo;
17921758
17931759 def VST2q8Pseudo : VSTQQPseudo;
17941760 def VST2q16Pseudo : VSTQQPseudo;
18361802 }
18371803 }
18381804
1839 defm VST2d8wb : VST2DWB<0b1000, {0,0,?,?}, "8", VecListTwoD>;
1840 defm VST2d16wb : VST2DWB<0b1000, {0,1,?,?}, "16", VecListTwoD>;
1841 defm VST2d32wb : VST2DWB<0b1000, {1,0,?,?}, "32", VecListTwoD>;
1805 defm VST2d8wb : VST2DWB<0b1000, {0,0,?,?}, "8", VecListDPair>;
1806 defm VST2d16wb : VST2DWB<0b1000, {0,1,?,?}, "16", VecListDPair>;
1807 defm VST2d32wb : VST2DWB<0b1000, {1,0,?,?}, "32", VecListDPair>;
18421808
18431809 defm VST2q8wb : VST2QWB<{0,0,?,?}, "8">;
18441810 defm VST2q16wb : VST2QWB<{0,1,?,?}, "16">;
18451811 defm VST2q32wb : VST2QWB<{1,0,?,?}, "32">;
1846
1847 def VST2d8PseudoWB_fixed : VSTQWBfixedPseudo;
1848 def VST2d16PseudoWB_fixed : VSTQWBfixedPseudo;
1849 def VST2d32PseudoWB_fixed : VSTQWBfixedPseudo;
1850 def VST2d8PseudoWB_register : VSTQWBregisterPseudo;
1851 def VST2d16PseudoWB_register : VSTQWBregisterPseudo;
1852 def VST2d32PseudoWB_register : VSTQWBregisterPseudo;
18531812
18541813 def VST2q8PseudoWB_fixed : VSTQQWBfixedPseudo;
18551814 def VST2q16PseudoWB_fixed : VSTQQWBfixedPseudo;
54435402 let hasExtraSrcRegAllocReq = 1 in {
54445403 def VTBL2
54455404 : N3V<1,1,0b11,0b1001,0,0, (outs DPR:$Vd),
5446 (ins VecListTwoD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTB2,
5405 (ins VecListDPair:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTB2,
54475406 "vtbl", "8", "$Vd, $Vn, $Vm", "", []>;
54485407 def VTBL3
54495408 : N3V<1,1,0b11,0b1010,0,0, (outs DPR:$Vd),
54565415 "vtbl", "8", "$Vd, $Vn, $Vm", "", []>;
54575416 } // hasExtraSrcRegAllocReq = 1
54585417
5459 def VTBL2Pseudo
5460 : PseudoNeonI<(outs DPR:$dst), (ins QPR:$tbl, DPR:$src), IIC_VTB2, "", []>;
54615418 def VTBL3Pseudo
54625419 : PseudoNeonI<(outs DPR:$dst), (ins QQPR:$tbl, DPR:$src), IIC_VTB3, "", []>;
54635420 def VTBL4Pseudo
54735430 let hasExtraSrcRegAllocReq = 1 in {
54745431 def VTBX2
54755432 : N3V<1,1,0b11,0b1001,1,0, (outs DPR:$Vd),
5476 (ins DPR:$orig, VecListTwoD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTBX2,
5433 (ins DPR:$orig, VecListDPair:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTBX2,
54775434 "vtbx", "8", "$Vd, $Vn, $Vm", "$orig = $Vd", []>;
54785435 def VTBX3
54795436 : N3V<1,1,0b11,0b1010,1,0, (outs DPR:$Vd),
54885445 "$orig = $Vd", []>;
54895446 } // hasExtraSrcRegAllocReq = 1
54905447
5491 def VTBX2Pseudo
5492 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QPR:$tbl, DPR:$src),
5493 IIC_VTBX2, "$orig = $dst", []>;
54945448 def VTBX3Pseudo
54955449 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QQPR:$tbl, DPR:$src),
54965450 IIC_VTBX3, "$orig = $dst", []>;
303303
304304 // Register class representing a pair of consecutive D registers.
305305 // Use the Q registers for the even-odd pairs.
306 def DPair : RegisterClass<"ARM", [v2i64], 128, (interleave QPR, TuplesOE2D)>;
306 def DPair : RegisterClass<"ARM", [v2i64], 128, (interleave QPR, TuplesOE2D)> {
307 // Allocate starting at non-VFP2 registers D16-D31 first.
308 let AltOrders = [(rotl DPair, 16)];
309 let AltOrderSelect = [{ return 1; }];
310 }
307311
308312 // Pseudo-registers representing 3 consecutive D registers.
309313 def Tuples3D : RegisterTuples<[dsub_0, dsub_1, dsub_2],
4343 class ARMAsmParser : public MCTargetAsmParser {
4444 MCSubtargetInfo &STI;
4545 MCAsmParser &Parser;
46 const MCRegisterInfo *MRI;
4647
4748 // Map of register aliases registers via the .req directive.
4849 StringMap RegisterReqs;
234235 ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser)
235236 : MCTargetAsmParser(), STI(_STI), Parser(_Parser) {
236237 MCAsmParserExtension::Initialize(_Parser);
238
239 // Cache the MCRegisterInfo.
240 MRI = &getContext().getRegisterInfo();
237241
238242 // Initialize the set of available features.
239243 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
10851089 return VectorList.Count == 2;
10861090 }
10871091
1092 bool isVecListDPair() const {
1093 if (!isSingleSpacedVectorList()) return false;
1094 return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1095 .contains(VectorList.RegNum));
1096 }
1097
10881098 bool isVecListThreeD() const {
10891099 if (!isSingleSpacedVectorList()) return false;
10901100 return VectorList.Count == 3;
29682978 switch (LaneKind) {
29692979 case NoLanes:
29702980 E = Parser.getTok().getLoc();
2981 // VLD1 wants a DPair register.
2982 // FIXME: Make the rest of the two-reg instructions want the same
2983 // thing.
2984 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
2985 &ARMMCRegisterClasses[ARM::DPairRegClassID]);
2986
29712987 Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E));
29722988 break;
29732989 case AllLanes:
31373153
31383154 switch (LaneKind) {
31393155 case NoLanes:
3156 if (Count == 2 && Spacing == 1)
3157 // VLD1 wants a DPair register.
3158 // FIXME: Make the rest of the two-reg instructions want the same
3159 // thing.
3160 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0,
3161 &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3162
3163
31403164 Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count,
31413165 (Spacing == 2), S, E));
31423166 break;
124124 uint64_t Address,
125125 const void *Decoder);
126126 static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
127 uint64_t Address, const void *Decoder);
128 static DecodeStatus DecodeDPairRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
127129 uint64_t Address, const void *Decoder);
128130
129131 static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val,
982984 RegNo >>= 1;
983985
984986 unsigned Register = QPRDecoderTable[RegNo];
987 Inst.addOperand(MCOperand::CreateReg(Register));
988 return MCDisassembler::Success;
989 }
990
991 static const unsigned DPairDecoderTable[] = {
992 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6,
993 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12,
994 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18,
995 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24,
996 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30,
997 ARM::Q15
998 };
999
1000 static DecodeStatus DecodeDPairRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
1001 uint64_t Address, const void *Decoder) {
1002 if (RegNo > 30)
1003 return MCDisassembler::Fail;
1004
1005 unsigned Register = DPairDecoderTable[RegNo];
9851006 Inst.addOperand(MCOperand::CreateReg(Register));
9861007 return MCDisassembler::Success;
9871008 }
19521973 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
19531974
19541975 // First output register
1955 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
1956 return MCDisassembler::Fail;
1976 switch (Inst.getOpcode()) {
1977 case ARM::VLD1q16:
1978 case ARM::VLD1q32:
1979 case ARM::VLD1q64:
1980 case ARM::VLD1q8:
1981 case ARM::VLD1q16wb_fixed:
1982 case ARM::VLD1q16wb_register:
1983 case ARM::VLD1q32wb_fixed:
1984 case ARM::VLD1q32wb_register:
1985 case ARM::VLD1q64wb_fixed:
1986 case ARM::VLD1q64wb_register:
1987 case ARM::VLD1q8wb_fixed:
1988 case ARM::VLD1q8wb_register:
1989 case ARM::VLD2d16:
1990 case ARM::VLD2d32:
1991 case ARM::VLD2d8:
1992 case ARM::VLD2d16wb_fixed:
1993 case ARM::VLD2d16wb_register:
1994 case ARM::VLD2d32wb_fixed:
1995 case ARM::VLD2d32wb_register:
1996 case ARM::VLD2d8wb_fixed:
1997 case ARM::VLD2d8wb_register:
1998 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
1999 return MCDisassembler::Fail;
2000 break;
2001 default:
2002 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2003 return MCDisassembler::Fail;
2004 }
19572005
19582006 // Second output register
19592007 switch (Inst.getOpcode()) {
22842332
22852333
22862334 // First input register
2287 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2288 return MCDisassembler::Fail;
2335 switch (Inst.getOpcode()) {
2336 case ARM::VST1q16:
2337 case ARM::VST1q32:
2338 case ARM::VST1q64:
2339 case ARM::VST1q8:
2340 case ARM::VST1q16wb_fixed:
2341 case ARM::VST1q16wb_register:
2342 case ARM::VST1q32wb_fixed:
2343 case ARM::VST1q32wb_register:
2344 case ARM::VST1q64wb_fixed:
2345 case ARM::VST1q64wb_register:
2346 case ARM::VST1q8wb_fixed:
2347 case ARM::VST1q8wb_register:
2348 case ARM::VST2d16:
2349 case ARM::VST2d32:
2350 case ARM::VST2d8:
2351 case ARM::VST2d16wb_fixed:
2352 case ARM::VST2d16wb_register:
2353 case ARM::VST2d32wb_fixed:
2354 case ARM::VST2d32wb_register:
2355 case ARM::VST2d8wb_fixed:
2356 case ARM::VST2d8wb_register:
2357 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2358 return MCDisassembler::Fail;
2359 break;
2360 default:
2361 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2362 return MCDisassembler::Fail;
2363 }
22892364
22902365 // Second input register
22912366 switch (Inst.getOpcode()) {
26512726 return MCDisassembler::Fail; // Writeback
26522727 }
26532728
2654 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder)))
2655 return MCDisassembler::Fail;
2729 switch (Inst.getOpcode()) {
2730 case ARM::VTBL2:
2731 case ARM::VTBX2:
2732 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder)))
2733 return MCDisassembler::Fail;
2734 break;
2735 default:
2736 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder)))
2737 return MCDisassembler::Fail;
2738 }
26562739
26572740 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
26582741 return MCDisassembler::Fail;
1717 #include "llvm/MC/MCInst.h"
1818 #include "llvm/MC/MCAsmInfo.h"
1919 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCRegisterInfo.h"
2021 #include "llvm/Support/raw_ostream.h"
2122 using namespace llvm;
2223
10321033 << getRegisterName(MI->getOperand(OpNum).getReg() + 1) << "}";
10331034 }
10341035
1036 void ARMInstPrinter::printVectorListDPair(const MCInst *MI, unsigned OpNum,
1037 raw_ostream &O) {
1038 unsigned Reg = MI->getOperand(OpNum).getReg();
1039 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1040 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1);
1041 O << "{" << getRegisterName(Reg0) << ", " << getRegisterName(Reg1) << "}";
1042 }
1043
10351044 void ARMInstPrinter::printVectorListThree(const MCInst *MI, unsigned OpNum,
10361045 raw_ostream &O) {
10371046 // Normally, it's not safe to use register enum values directly with
133133 void printVectorIndex(const MCInst *MI, unsigned OpNum, raw_ostream &O);
134134 void printVectorListOne(const MCInst *MI, unsigned OpNum, raw_ostream &O);
135135 void printVectorListTwo(const MCInst *MI, unsigned OpNum, raw_ostream &O);
136 void printVectorListDPair(const MCInst *MI, unsigned OpNum, raw_ostream &O);
136137 void printVectorListThree(const MCInst *MI, unsigned OpNum, raw_ostream &O);
137138 void printVectorListFour(const MCInst *MI, unsigned OpNum, raw_ostream &O);
138139 void printVectorListOneAllLanes(const MCInst *MI, unsigned OpNum,
184184 case S29: case D29: return 29;
185185 case S30: case D30: return 30;
186186 case S31: case D31: return 31;
187
188 // Composite registers use the regnum of the first register in the list.
189 case D1_D2: return 1;
190 case D3_D5: return 3;
191 case D5_D7: return 5;
192 case D7_D9: return 7;
193 case D9_D10: return 9;
194 case D11_D12: return 11;
195 case D13_D14: return 13;
196 case D15_D16: return 15;
197 case D17_D18: return 17;
198 case D19_D20: return 19;
199 case D21_D22: return 21;
200 case D23_D24: return 23;
201 case D25_D26: return 25;
202 case D27_D28: return 27;
203 case D29_D30: return 29;
187204 }
188205 }
189206
574574 REG("QQQQPR");
575575 REG("VecListOneD");
576576 REG("VecListTwoD");
577 REG("VecListDPair");
577578 REG("VecListThreeD");
578579 REG("VecListFourD");
579580 REG("VecListTwoQ");