llvm.org GIT mirror llvm / 28b77e9
Add codegen support for vector select (in the IR this means a select with a vector condition); such selects become VSELECT codegen nodes. This patch also removes VSETCC codegen nodes, unifying them with SETCC nodes (codegen was actually often using SETCC for vector SETCC already). This ensures that various DAG combiner optimizations kick in for vector comparisons. Passes dragonegg bootstrap with no testsuite regressions (nightly testsuite as well as "make check-all"). Patch mostly by Nadav Rotem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139159 91177308-0d34-0410-b5e6-96231b3b80d8 Duncan Sands 8 years ago
36 changed file(s) with 254 addition(s) and 140 deletion(s). Raw diff Collapse all Expand all
322322 // i1 then the high bits must conform to getBooleanContents.
323323 SELECT,
324324
325 // Select with a vector condition (op #0) and two vector operands (ops #1
326 // and #2), returning a vector result. All vectors have the same length.
327 // Much like the scalar select and setcc, each bit in the condition selects
328 // whether the corresponding result element is taken from op #1 or op #2.
329 VSELECT,
330
325331 // Select with condition operator - This selects between a true value and
326332 // a false value (ops #2 and #3) based on the boolean result of comparing
327333 // the lhs and rhs (ops #0 and #1) of a conditional expression with the
332338 // true. If the result value type is not i1 then the high bits conform
333339 // to getBooleanContents. The operands to this are the left and right
334340 // operands to compare (ops #0, and #1) and the condition code to compare
335 // them with (op #2) as a CondCodeSDNode.
341 // them with (op #2) as a CondCodeSDNode. If the operands are vector types
342 // then the result type must also be a vector type.
336343 SETCC,
337
338 // RESULT = VSETCC(LHS, RHS, COND) operator - This evaluates to a vector of
339 // integer elements with all bits of the result elements set to true if the
340 // comparison is true or all cleared if the comparison is false. The
341 // operands to this are the left and right operands to compare (LHS/RHS) and
342 // the condition code to compare them with (COND) as a CondCodeSDNode.
343 VSETCC,
344344
345345 // SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded
346346 // integer shift operations, just like ADD/SUB_PARTS. The operation
559559 ///
560560 SDValue getSetCC(DebugLoc DL, EVT VT, SDValue LHS, SDValue RHS,
561561 ISD::CondCode Cond) {
562 assert(LHS.getValueType().isVector() == RHS.getValueType().isVector() &&
563 "Cannot compare scalars to vectors");
564 assert(LHS.getValueType().isVector() == VT.isVector() &&
565 "Cannot compare scalars to vectors");
562566 return getNode(ISD::SETCC, DL, VT, LHS, RHS, getCondCode(Cond));
563 }
564
565 /// getVSetCC - Helper function to make it easier to build VSetCC's nodes
566 /// if you just have an ISD::CondCode instead of an SDValue.
567 ///
568 SDValue getVSetCC(DebugLoc DL, EVT VT, SDValue LHS, SDValue RHS,
569 ISD::CondCode Cond) {
570 return getNode(ISD::VSETCC, DL, VT, LHS, RHS, getCondCode(Cond));
571567 }
572568
573569 /// getSelectCC - Helper function to make it easier to build SelectCC's if you
437437 return MVT::INVALID_SIMPLE_VALUE_TYPE;
438438 }
439439
440 /// changeVectorElementTypeToInteger - Return a vector with the same number
441 /// of elements as this vector, but with the element type converted to an
442 /// integer type with the same bitwidth.
443 EVT changeVectorElementTypeToInteger() const {
444 if (!isSimple())
445 return changeExtendedVectorElementTypeToInteger();
446 MVT EltTy = getSimpleVT().getVectorElementType();
447 unsigned BitWidth = EltTy.getSizeInBits();
448 MVT IntTy = MVT::getIntegerVT(BitWidth);
449 MVT VecTy = MVT::getVectorVT(IntTy, getVectorNumElements());
450 assert(VecTy != MVT::INVALID_SIMPLE_VALUE_TYPE &&
451 "Simple vector VT not representable by simple integer vector VT!");
452 return VecTy;
453 }
454
440455 /// isSimple - Test if the given EVT is simple (as opposed to being
441456 /// extended).
442457 bool isSimple() const {
673688 // Methods for handling the Extended-type case in functions above.
674689 // These are all out-of-line to prevent users of this header file
675690 // from having a dependency on Type.h.
691 EVT changeExtendedVectorElementTypeToInteger() const;
676692 static EVT getExtendedIntegerVT(LLVMContext &C, unsigned BitWidth);
677693 static EVT getExtendedVectorVT(LLVMContext &C, EVT VT,
678694 unsigned NumElements);
112112 ZeroOrNegativeOneBooleanContent // All bits equal to bit 0.
113113 };
114114
115 static ISD::NodeType getExtendForContent(BooleanContent Content) {
116 switch (Content) {
117 default:
118 assert(false && "Unknown BooleanContent!");
119 case UndefinedBooleanContent:
120 // Extend by adding rubbish bits.
121 return ISD::ANY_EXTEND;
122 case ZeroOrOneBooleanContent:
123 // Extend by adding zero bits.
124 return ISD::ZERO_EXTEND;
125 case ZeroOrNegativeOneBooleanContent:
126 // Extend by copying the sign bit.
127 return ISD::SIGN_EXTEND;
128 }
129 }
130
115131 /// NOTE: The constructor takes ownership of TLOF.
116132 explicit TargetLowering(const TargetMachine &TM,
117133 const TargetLoweringObjectFile *TLOF);
147163 /// the condition operand of SELECT and BRCOND nodes. In the case of
148164 /// BRCOND the argument passed is MVT::Other since there are no other
149165 /// operands to get a type hint from.
150 virtual
151 MVT::SimpleValueType getSetCCResultType(EVT VT) const;
166 virtual EVT getSetCCResultType(EVT VT) const;
152167
153168 /// getCmpLibcallReturnType - Return the ValueType for comparison
154169 /// libcalls. Comparions libcalls include floating point comparion calls,
161176 /// "Boolean values" are special true/false values produced by nodes like
162177 /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND.
163178 /// Not to be confused with general values promoted from i1.
164 BooleanContent getBooleanContents() const { return BooleanContents;}
179 /// Some cpus distinguish between vectors of boolean and scalars; the isVec
180 /// parameter selects between the two kinds. For example on X86 a scalar
181 /// boolean should be zero extended from i1, while the elements of a vector
182 /// of booleans should be sign extended from i1.
183 BooleanContent getBooleanContents(bool isVec) const {
184 return isVec ? BooleanVectorContents : BooleanContents;
185 }
165186
166187 /// getSchedulingPreference - Return target scheduling preference.
167188 Sched::Preference getSchedulingPreference() const {
937958 /// setBooleanContents - Specify how the target extends the result of a
938959 /// boolean value from i1 to a wider type. See getBooleanContents.
939960 void setBooleanContents(BooleanContent Ty) { BooleanContents = Ty; }
961 /// setBooleanVectorContents - Specify how the target extends the result
962 /// of a vector boolean value from a vector of i1 to a wider type. See
963 /// getBooleanContents.
964 void setBooleanVectorContents(BooleanContent Ty) {
965 BooleanVectorContents = Ty;
966 }
940967
941968 /// setSchedulingPreference - Specify the target scheduling preference.
942969 void setSchedulingPreference(Sched::Preference Pref) {
16561683 /// BooleanContents - Information about the contents of the high-bits in
16571684 /// boolean values held in a type wider than i1. See getBooleanContents.
16581685 BooleanContent BooleanContents;
1686 /// BooleanVectorContents - Information about the contents of the high-bits
1687 /// in boolean vector values when the element type is wider than i1. See
1688 /// getBooleanContents.
1689 BooleanContent BooleanVectorContents;
16591690
16601691 /// SchedPreferenceInfo - The target scheduling preference: shortest possible
16611692 /// total cycles or lowest register usage.
37563756 if (VT.isInteger() &&
37573757 (VT0 == MVT::i1 ||
37583758 (VT0.isInteger() &&
3759 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent)) &&
3759 TLI.getBooleanContents(false) == TargetLowering::ZeroOrOneBooleanContent)) &&
37603760 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) {
37613761 SDValue XORNode;
37623762 if (VT == VT0)
41114111 // we know that the element size of the sext'd result matches the
41124112 // element size of the compare operands.
41134113 if (VT.getSizeInBits() == N0VT.getSizeInBits())
4114 return DAG.getVSetCC(N->getDebugLoc(), VT, N0.getOperand(0),
4114 return DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0),
41154115 N0.getOperand(1),
41164116 cast(N0.getOperand(2))->get());
41174117 // If the desired elements are smaller or larger than the source
41254125 EVT::getVectorVT(*DAG.getContext(), MatchingElementType,
41264126 N0VT.getVectorNumElements());
41274127 SDValue VsetCC =
4128 DAG.getVSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0),
4128 DAG.getSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0),
41294129 N0.getOperand(1),
41304130 cast(N0.getOperand(2))->get());
41314131 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT);
43414341 // we know that the element size of the sext'd result matches the
43424342 // element size of the compare operands.
43434343 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
4344 DAG.getVSetCC(N->getDebugLoc(), VT, N0.getOperand(0),
4344 DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0),
43454345 N0.getOperand(1),
43464346 cast(N0.getOperand(2))->get()),
43474347 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT,
43574357 EVT::getVectorVT(*DAG.getContext(), MatchingElementType,
43584358 N0VT.getVectorNumElements());
43594359 SDValue VsetCC =
4360 DAG.getVSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0),
4360 DAG.getSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0),
43614361 N0.getOperand(1),
43624362 cast(N0.getOperand(2))->get());
43634363 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
45254525 // we know that the element size of the sext'd result matches the
45264526 // element size of the compare operands.
45274527 if (VT.getSizeInBits() == N0VT.getSizeInBits())
4528 return DAG.getVSetCC(N->getDebugLoc(), VT, N0.getOperand(0),
4528 return DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0),
45294529 N0.getOperand(1),
45304530 cast(N0.getOperand(2))->get());
45314531 // If the desired elements are smaller or larger than the source
45394539 EVT::getVectorVT(*DAG.getContext(), MatchingElementType,
45404540 N0VT.getVectorNumElements());
45414541 SDValue VsetCC =
4542 DAG.getVSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0),
4542 DAG.getSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0),
45434543 N0.getOperand(1),
45444544 cast(N0.getOperand(2))->get());
45454545 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT);
75467546
75477547 // fold select C, 16, 0 -> shl C, 4
75487548 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() &&
7549 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent) {
7549 TLI.getBooleanContents(N0.getValueType().isVector()) ==
7550 TargetLowering::ZeroOrOneBooleanContent) {
75507551
75517552 // If the caller doesn't want us to simplify this into a zext of a compare,
75527553 // don't do it.
474474
475475 SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) {
476476 EVT SVT = TLI.getSetCCResultType(N->getOperand(0).getValueType());
477 assert(isTypeLegal(SVT) && "Illegal SetCC type!");
478 DebugLoc dl = N->getDebugLoc();
477
478 DebugLoc dl = N->getDebugLoc();
479 assert(SVT.isVector() == N->getOperand(0).getValueType().isVector() &&
480 "Vector compare must return a vector result!");
479481
480482 // Get the SETCC result using the canonical SETCC type.
481 SDValue SetCC = DAG.getNode(ISD::SETCC, dl, SVT, N->getOperand(0),
483 SDValue SetCC = DAG.getNode(N->getOpcode(), dl, SVT, N->getOperand(0),
482484 N->getOperand(1), N->getOperand(2));
483485
484486 // Convert to the expected type.
728730 case ISD::MEMBARRIER: Res = PromoteIntOp_MEMBARRIER(N); break;
729731 case ISD::SCALAR_TO_VECTOR:
730732 Res = PromoteIntOp_SCALAR_TO_VECTOR(N); break;
733 case ISD::VSELECT:
731734 case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break;
732735 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break;
733736 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break;
920923 }
921924
922925 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) {
923 assert(OpNo == 0 && "Only know how to promote condition");
926 assert(OpNo == 0 && "Only know how to promote the condition!");
927 SDValue Cond = N->getOperand(0);
928 EVT OpTy = N->getOperand(1).getValueType();
924929
925930 // Promote all the way up to the canonical SetCC type.
926 EVT SVT = TLI.getSetCCResultType(N->getOperand(1).getValueType());
927 SDValue Cond = PromoteTargetBoolean(N->getOperand(0), SVT);
928
929 return SDValue(DAG.UpdateNodeOperands(N, Cond,
930 N->getOperand(1), N->getOperand(2)), 0);
931 EVT SVT = TLI.getSetCCResultType(N->getOpcode() == ISD::SELECT ?
932 OpTy.getScalarType() : OpTy);
933 Cond = PromoteTargetBoolean(Cond, SVT);
934
935 return SDValue(DAG.UpdateNodeOperands(N, Cond, N->getOperand(1),
936 N->getOperand(2)), 0);
931937 }
932938
933939 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo) {
11121112 /// type i1, the bits of which conform to getBooleanContents.
11131113 SDValue DAGTypeLegalizer::PromoteTargetBoolean(SDValue Bool, EVT VT) {
11141114 DebugLoc dl = Bool.getDebugLoc();
1115 ISD::NodeType ExtendCode;
1116 switch (TLI.getBooleanContents()) {
1117 default:
1118 assert(false && "Unknown BooleanContent!");
1119 case TargetLowering::UndefinedBooleanContent:
1120 // Extend to VT by adding rubbish bits.
1121 ExtendCode = ISD::ANY_EXTEND;
1122 break;
1123 case TargetLowering::ZeroOrOneBooleanContent:
1124 // Extend to VT by adding zero bits.
1125 ExtendCode = ISD::ZERO_EXTEND;
1126 break;
1127 case TargetLowering::ZeroOrNegativeOneBooleanContent: {
1128 // Extend to VT by copying the sign bit.
1129 ExtendCode = ISD::SIGN_EXTEND;
1130 break;
1131 }
1132 }
1115 ISD::NodeType ExtendCode =
1116 TargetLowering::getExtendForContent(TLI.getBooleanContents(VT.isVector()));
11331117 return DAG.getNode(ExtendCode, dl, VT, Bool);
11341118 }
11351119
271271 SDValue PromoteIntOp_SELECT(SDNode *N, unsigned OpNo);
272272 SDValue PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo);
273273 SDValue PromoteIntOp_SETCC(SDNode *N, unsigned OpNo);
274 SDValue PromoteIntOp_VSETCC(SDNode *N, unsigned OpNo);
274275 SDValue PromoteIntOp_Shift(SDNode *N);
275276 SDValue PromoteIntOp_SIGN_EXTEND(SDNode *N);
276277 SDValue PromoteIntOp_SINT_TO_FP(SDNode *N);
572573 SDValue SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N);
573574 SDValue SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo);
574575 SDValue SplitVecOp_CONCAT_VECTORS(SDNode *N);
576 SDValue SplitVecOp_VSETCC(SDNode *N);
575577 SDValue SplitVecOp_FP_ROUND(SDNode *N);
576578
577579 //===--------------------------------------------------------------------===//
438438
439439 void DAGTypeLegalizer::SplitRes_SELECT(SDNode *N, SDValue &Lo,
440440 SDValue &Hi) {
441 SDValue LL, LH, RL, RH;
441 SDValue LL, LH, RL, RH, CL, CH;
442442 DebugLoc dl = N->getDebugLoc();
443443 GetSplitOp(N->getOperand(1), LL, LH);
444444 GetSplitOp(N->getOperand(2), RL, RH);
445445
446446 SDValue Cond = N->getOperand(0);
447 Lo = DAG.getNode(ISD::SELECT, dl, LL.getValueType(), Cond, LL, RL);
448 Hi = DAG.getNode(ISD::SELECT, dl, LH.getValueType(), Cond, LH, RH);
447 CL = CH = Cond;
448 if (Cond.getValueType().isVector()) {
449 assert(Cond.getValueType().getVectorElementType() == MVT::i1 &&
450 "Condition legalized before result?");
451 unsigned NumElements = Cond.getValueType().getVectorNumElements();
452 EVT VCondTy = EVT::getVectorVT(*DAG.getContext(), MVT::i1, NumElements / 2);
453 CL = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VCondTy, Cond,
454 DAG.getIntPtrConstant(0));
455 CH = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VCondTy, Cond,
456 DAG.getIntPtrConstant(NumElements / 2));
457 }
458
459 Lo = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), CL, LL, RL);
460 Hi = DAG.getNode(N->getOpcode(), dl, LH.getValueType(), CH, LH, RH);
449461 }
450462
451463 void DAGTypeLegalizer::SplitRes_SELECT_CC(SDNode *N, SDValue &Lo,
157157 case ISD::CTPOP:
158158 case ISD::SELECT:
159159 case ISD::SELECT_CC:
160 case ISD::VSETCC:
160 case ISD::SETCC:
161161 case ISD::ZERO_EXTEND:
162162 case ISD::ANY_EXTEND:
163163 case ISD::TRUNCATE:
213213 Result = ExpandUINT_TO_FLOAT(Op);
214214 else if (Node->getOpcode() == ISD::FNEG)
215215 Result = ExpandFNEG(Op);
216 else if (Node->getOpcode() == ISD::VSETCC)
216 else if (Node->getOpcode() == ISD::SETCC)
217217 Result = UnrollVSETCC(Op);
218218 else
219219 Result = DAG.UnrollVectorOp(Op.getNode());
6363 case ISD::SETCC: R = ScalarizeVecRes_SETCC(N); break;
6464 case ISD::UNDEF: R = ScalarizeVecRes_UNDEF(N); break;
6565 case ISD::VECTOR_SHUFFLE: R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break;
66 case ISD::VSETCC: R = ScalarizeVecRes_VSETCC(N); break;
67
6866 case ISD::ANY_EXTEND:
6967 case ISD::CTLZ:
7068 case ISD::CTPOP:
243241 }
244242
245243 SDValue DAGTypeLegalizer::ScalarizeVecRes_SETCC(SDNode *N) {
244 assert(N->getValueType(0).isVector() ==
245 N->getOperand(0).getValueType().isVector() &&
246 "Scalar/Vector type mismatch");
247
248 if (N->getValueType(0).isVector()) return ScalarizeVecRes_VSETCC(N);
249
246250 SDValue LHS = GetScalarizedVector(N->getOperand(0));
247251 SDValue RHS = GetScalarizedVector(N->getOperand(1));
248252 DebugLoc DL = N->getDebugLoc();
265269 }
266270
267271 SDValue DAGTypeLegalizer::ScalarizeVecRes_VSETCC(SDNode *N) {
272 assert(N->getValueType(0).isVector() &&
273 N->getOperand(0).getValueType().isVector() &&
274 "Operand types must be vectors");
275
268276 SDValue LHS = GetScalarizedVector(N->getOperand(0));
269277 SDValue RHS = GetScalarizedVector(N->getOperand(1));
270278 EVT NVT = N->getValueType(0).getVectorElementType();
271 EVT SVT = TLI.getSetCCResultType(LHS.getValueType());
272279 DebugLoc DL = N->getDebugLoc();
273280
274281 // Turn it into a scalar SETCC.
275 SDValue Res = DAG.getNode(ISD::SETCC, DL, SVT, LHS, RHS, N->getOperand(2));
276
277 // VSETCC always returns a sign-extended value, while SETCC may not. The
278 // SETCC result type may not match the vector element type. Correct these.
279 if (NVT.bitsLE(SVT)) {
280 // The SETCC result type is bigger than the vector element type.
281 // Ensure the SETCC result is sign-extended.
282 if (TLI.getBooleanContents() !=
283 TargetLowering::ZeroOrNegativeOneBooleanContent)
284 Res = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, SVT, Res,
285 DAG.getValueType(MVT::i1));
286 // Truncate to the final type.
287 return DAG.getNode(ISD::TRUNCATE, DL, NVT, Res);
288 }
289
290 // The SETCC result type is smaller than the vector element type.
291 // If the SetCC result is not sign-extended, chop it down to MVT::i1.
292 if (TLI.getBooleanContents() !=
293 TargetLowering::ZeroOrNegativeOneBooleanContent)
294 Res = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Res);
295 // Sign extend to the final type.
296 return DAG.getNode(ISD::SIGN_EXTEND, DL, NVT, Res);
282 SDValue Res = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS,
283 N->getOperand(2));
284 // Vectors may have a different boolean contents to scalars. Promote the
285 // value appropriately.
286 ISD::NodeType ExtendCode =
287 TargetLowering::getExtendForContent(TLI.getBooleanContents(true));
288 return DAG.getNode(ExtendCode, DL, NVT, Res);
297289 }
298290
299291
422414 llvm_unreachable("Do not know how to split the result of this operator!");
423415
424416 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break;
417 case ISD::VSELECT:
425418 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
426419 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
427420 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
438431 SplitVecRes_LOAD(cast(N), Lo, Hi);
439432 break;
440433 case ISD::SETCC:
441 case ISD::VSETCC:
442434 SplitVecRes_SETCC(N, Lo, Hi);
443435 break;
444436 case ISD::VECTOR_SHUFFLE:
745737 }
746738
747739 void DAGTypeLegalizer::SplitVecRes_SETCC(SDNode *N, SDValue &Lo, SDValue &Hi) {
740 assert(N->getValueType(0).isVector() &&
741 N->getOperand(0).getValueType().isVector() &&
742 "Operand types must be vectors");
743
748744 EVT LoVT, HiVT;
749745 DebugLoc DL = N->getDebugLoc();
750746 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
970966 dbgs() << "\n";
971967 #endif
972968 llvm_unreachable("Do not know how to split this operator's operand!");
973
969 case ISD::SETCC: Res = SplitVecOp_VSETCC(N); break;
974970 case ISD::BITCAST: Res = SplitVecOp_BITCAST(N); break;
975971 case ISD::EXTRACT_SUBVECTOR: Res = SplitVecOp_EXTRACT_SUBVECTOR(N); break;
976972 case ISD::EXTRACT_VECTOR_ELT:Res = SplitVecOp_EXTRACT_VECTOR_ELT(N); break;
11671163 return DAG.getNode(ISD::BUILD_VECTOR, DL, N->getValueType(0),
11681164 &Elts[0], Elts.size());
11691165 }
1166
1167 SDValue DAGTypeLegalizer::SplitVecOp_VSETCC(SDNode *N) {
1168 assert(N->getValueType(0).isVector() &&
1169 N->getOperand(0).getValueType().isVector() &&
1170 "Operand types must be vectors");
1171 // The result has a legal vector type, but the input needs splitting.
1172 SDValue Lo0, Hi0, Lo1, Hi1, LoRes, HiRes;
1173 DebugLoc DL = N->getDebugLoc();
1174 GetSplitVector(N->getOperand(0), Lo0, Hi0);
1175 GetSplitVector(N->getOperand(1), Lo1, Hi1);
1176 unsigned PartElements = Lo0.getValueType().getVectorNumElements();
1177 EVT PartResVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1, PartElements);
1178 EVT WideResVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1, 2*PartElements);
1179
1180 LoRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Lo0, Lo1, N->getOperand(2));
1181 HiRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Hi0, Hi1, N->getOperand(2));
1182 SDValue Con = DAG.getNode(ISD::CONCAT_VECTORS, DL, WideResVT, LoRes, HiRes);
1183 return PromoteTargetBoolean(Con, N->getValueType(0));
1184 }
1185
11701186
11711187 SDValue DAGTypeLegalizer::SplitVecOp_FP_ROUND(SDNode *N) {
11721188 // The result has a legal vector type, but the input needs splitting.
12281244 case ISD::VECTOR_SHUFFLE:
12291245 Res = WidenVecRes_VECTOR_SHUFFLE(cast(N));
12301246 break;
1231 case ISD::VSETCC:
1232 Res = WidenVecRes_VSETCC(N);
1233 break;
1234
12351247 case ISD::ADD:
12361248 case ISD::AND:
12371249 case ISD::BSWAP:
19281940 }
19291941
19301942 SDValue DAGTypeLegalizer::WidenVecRes_SETCC(SDNode *N) {
1943 assert(N->getValueType(0).isVector() ==
1944 N->getOperand(0).getValueType().isVector() &&
1945 "Scalar/Vector type mismatch");
1946 if (N->getValueType(0).isVector()) return WidenVecRes_VSETCC(N);
1947
19311948 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
19321949 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
19331950 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
19661983 }
19671984
19681985 SDValue DAGTypeLegalizer::WidenVecRes_VSETCC(SDNode *N) {
1986 assert(N->getValueType(0).isVector() &&
1987 N->getOperand(0).getValueType().isVector() &&
1988 "Operands must be vectors");
19691989 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
19701990 unsigned WidenNumElts = WidenVT.getVectorNumElements();
19711991
19832003 InOp2.getValueType() == WidenInVT &&
19842004 "Input not widened to expected type!");
19852005 (void)WidenInVT;
1986 return DAG.getNode(ISD::VSETCC, N->getDebugLoc(),
2006 return DAG.getNode(ISD::SETCC, N->getDebugLoc(),
19872007 WidenVT, InOp1, InOp2, N->getOperand(2));
19882008 }
19892009
926926 assert(VT.isInteger() && "Cannot create FP integer constant!");
927927
928928 EVT EltVT = VT.getScalarType();
929 assert(Val.getBitWidth() == EltVT.getSizeInBits() &&
929 const ConstantInt *Elt = &Val;
930
931 // In some cases the vector type is legal but the element type is illegal and
932 // needs to be promoted, for example v8i8 on ARM. In this case, promote the
933 // inserted value (the type does not need to match the vector element type).
934 // Any extra bits introduced will be truncated away.
935 if (VT.isVector() && TLI.getTypeAction(*getContext(), EltVT) ==
936 TargetLowering::TypePromoteInteger) {
937 EltVT = TLI.getTypeToTransformTo(*getContext(), EltVT);
938 APInt NewVal = Elt->getValue().zext(EltVT.getSizeInBits());
939 Elt = ConstantInt::get(*getContext(), NewVal);
940 }
941
942 assert(Elt->getBitWidth() == EltVT.getSizeInBits() &&
930943 "APInt size does not match type size!");
931
932944 unsigned Opc = isT ? ISD::TargetConstant : ISD::Constant;
933945 FoldingSetNodeID ID;
934946 AddNodeIDNode(ID, Opc, getVTList(EltVT), 0, 0);
935 ID.AddPointer(&Val);
947 ID.AddPointer(Elt);
936948 void *IP = 0;
937949 SDNode *N = NULL;
938950 if ((N = CSEMap.FindNodeOrInsertPos(ID, IP)))
940952 return SDValue(N, 0);
941953
942954 if (!N) {
943 N = new (NodeAllocator) ConstantSDNode(isT, &Val, EltVT);
955 N = new (NodeAllocator) ConstantSDNode(isT, Elt, EltVT);
944956 CSEMap.InsertNode(N, IP);
945957 AllNodes.push_back(N);
946958 }
17191731 // The boolean result conforms to getBooleanContents. Fall through.
17201732 case ISD::SETCC:
17211733 // If we know the result of a setcc has the top bits zero, use this info.
1722 if (TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent &&
1723 BitWidth > 1)
1734 if (TLI.getBooleanContents(Op.getValueType().isVector()) ==
1735 TargetLowering::ZeroOrOneBooleanContent && BitWidth > 1)
17241736 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
17251737 return;
17261738 case ISD::SHL:
21542166 // The boolean result conforms to getBooleanContents. Fall through.
21552167 case ISD::SETCC:
21562168 // If setcc returns 0/-1, all bits are sign bits.
2157 if (TLI.getBooleanContents() ==
2169 if (TLI.getBooleanContents(Op.getValueType().isVector()) ==
21582170 TargetLowering::ZeroOrNegativeOneBooleanContent)
21592171 return VTBits;
21602172 break;
59645976
59655977 case ISD::FPOWI: return "fpowi";
59665978 case ISD::SETCC: return "setcc";
5967 case ISD::VSETCC: return "vsetcc";
59685979 case ISD::SELECT: return "select";
5980 case ISD::VSELECT: return "vselect";
59695981 case ISD::SELECT_CC: return "select_cc";
59705982 case ISD::INSERT_VECTOR_ELT: return "insert_vector_elt";
59715983 case ISD::EXTRACT_VECTOR_ELT: return "extract_vector_elt";
26252625 SDValue Cond = getValue(I.getOperand(0));
26262626 SDValue TrueVal = getValue(I.getOperand(1));
26272627 SDValue FalseVal = getValue(I.getOperand(2));
2628 ISD::NodeType OpCode = Cond.getValueType().isVector() ?
2629 ISD::VSELECT : ISD::SELECT;
26282630
26292631 for (unsigned i = 0; i != NumValues; ++i)
2630 Values[i] = DAG.getNode(ISD::SELECT, getCurDebugLoc(),
2631 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i),
2632 Values[i] = DAG.getNode(OpCode, getCurDebugLoc(),
2633 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i),
26322634 Cond,
26332635 SDValue(TrueVal.getNode(),
26342636 TrueVal.getResNo() + i),
608608 ExceptionPointerRegister = 0;
609609 ExceptionSelectorRegister = 0;
610610 BooleanContents = UndefinedBooleanContent;
611 BooleanVectorContents = UndefinedBooleanContent;
611612 SchedPreferenceInfo = Sched::Latency;
612613 JumpBufSize = 0;
613614 JumpBufAlignment = 0;
914915 }
915916
916917
917 MVT::SimpleValueType TargetLowering::getSetCCResultType(EVT VT) const {
918 EVT TargetLowering::getSetCCResultType(EVT VT) const {
919 assert(!VT.isVector() && "No default SetCC type for vectors!");
918920 return PointerTy.SimpleTy;
919921 }
920922
21902192 }
21912193 } else if (N1C->getAPIntValue() == 1 &&
21922194 (VT == MVT::i1 ||
2193 getBooleanContents() == ZeroOrOneBooleanContent)) {
2195 getBooleanContents(false) == ZeroOrOneBooleanContent)) {
21942196 SDValue Op0 = N0;
21952197 if (Op0.getOpcode() == ISD::TRUNCATE)
21962198 Op0 = Op0.getOperand(0);
105105
106106 EVT ElemTy = VT.getVectorElementType();
107107 if (ElemTy != MVT::i64 && ElemTy != MVT::f64)
108 setOperationAction(ISD::VSETCC, VT.getSimpleVT(), Custom);
108 setOperationAction(ISD::SETCC, VT.getSimpleVT(), Custom);
109109 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom);
110110 if (ElemTy != MVT::i32) {
111111 setOperationAction(ISD::SINT_TO_FP, VT.getSimpleVT(), Expand);
176176 Subtarget = &TM.getSubtarget();
177177 RegInfo = TM.getRegisterInfo();
178178 Itins = TM.getInstrItineraryData();
179
180 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
179181
180182 if (Subtarget->isTargetDarwin()) {
181183 // Uses VFP for Thumb libfuncs if available.
452454 setOperationAction(ISD::FDIV, MVT::v2f64, Expand);
453455 setOperationAction(ISD::FREM, MVT::v2f64, Expand);
454456 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand);
455 setOperationAction(ISD::VSETCC, MVT::v2f64, Expand);
457 setOperationAction(ISD::SETCC, MVT::v2f64, Expand);
456458 setOperationAction(ISD::FNEG, MVT::v2f64, Expand);
457459 setOperationAction(ISD::FABS, MVT::v2f64, Expand);
458460 setOperationAction(ISD::FSQRT, MVT::v2f64, Expand);
484486 setOperationAction(ISD::SDIV, MVT::v8i8, Custom);
485487 setOperationAction(ISD::UDIV, MVT::v4i16, Custom);
486488 setOperationAction(ISD::UDIV, MVT::v8i8, Custom);
487 setOperationAction(ISD::VSETCC, MVT::v1i64, Expand);
488 setOperationAction(ISD::VSETCC, MVT::v2i64, Expand);
489 setOperationAction(ISD::SETCC, MVT::v1i64, Expand);
490 setOperationAction(ISD::SETCC, MVT::v2i64, Expand);
489491 // Neon does not have single instruction SINT_TO_FP and UINT_TO_FP with
490492 // a destination type that is wider than the source.
491493 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom);
929931 }
930932 }
931933
934 EVT ARMTargetLowering::getSetCCResultType(EVT VT) const {
935 if (!VT.isVector()) return getPointerTy();
936 return VT.changeVectorElementTypeToInteger();
937 }
938
932939 /// getRegClassFor - Return the register class that should be used for the
933940 /// specified value type.
934941 TargetRegisterClass *ARMTargetLowering::getRegClassFor(EVT VT) const {
49244931 case ISD::SRL_PARTS:
49254932 case ISD::SRA_PARTS: return LowerShiftRightParts(Op, DAG);
49264933 case ISD::CTTZ: return LowerCTTZ(Op.getNode(), DAG, Subtarget);
4927 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
4934 case ISD::SETCC: return LowerVSETCC(Op, DAG);
49284935 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG, Subtarget);
49294936 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
49304937 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
253253 SelectionDAG &DAG) const;
254254
255255 virtual const char *getTargetNodeName(unsigned Opcode) const;
256
257 /// getSetCCResultType - Return the value type to use for ISD::SETCC.
258 virtual EVT getSetCCResultType(EVT VT) const;
256259
257260 virtual MachineBasicBlock *
258261 EmitInstrWithCustomInserter(MachineInstr *MI,
4848 // Set up the TargetLowering object.
4949 //I am having problems with shr n i8 1
5050 setBooleanContents(ZeroOrOneBooleanContent);
51 setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
5152
5253 addRegisterClass(MVT::i64, Alpha::GPRCRegisterClass);
5354 addRegisterClass(MVT::f64, Alpha::F8RCRegisterClass);
167168 computeRegisterProperties();
168169 }
169170
170 MVT::SimpleValueType AlphaTargetLowering::getSetCCResultType(EVT VT) const {
171 EVT AlphaTargetLowering::getSetCCResultType(EVT VT) const {
171172 return MVT::i64;
172173 }
173174
6565 virtual MVT getShiftAmountTy(EVT LHSTy) const { return MVT::i64; }
6666
6767 /// getSetCCResultType - Get the SETCC result ValueType
68 virtual MVT::SimpleValueType getSetCCResultType(EVT VT) const;
68 virtual EVT getSetCCResultType(EVT VT) const;
6969
7070 /// LowerOperation - Provide custom lowering hooks for some operations.
7171 ///
4141 BlackfinTargetLowering::BlackfinTargetLowering(TargetMachine &TM)
4242 : TargetLowering(TM, new TargetLoweringObjectFileELF()) {
4343 setBooleanContents(ZeroOrOneBooleanContent);
44 setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
4445 setStackPointerRegisterToSaveRestore(BF::SP);
4546 setIntDivIsCheap(false);
4647
134135 }
135136 }
136137
137 MVT::SimpleValueType BlackfinTargetLowering::getSetCCResultType(EVT VT) const {
138 EVT BlackfinTargetLowering::getSetCCResultType(EVT VT) const {
138139 // SETCC always sets the CC register. Technically that is an i1 register, but
139140 // that type is not legal, so we treat it as an i32 register.
140141 return MVT::i32;
3232 public:
3333 BlackfinTargetLowering(TargetMachine &TM);
3434 virtual MVT getShiftAmountTy(EVT LHSTy) const { return MVT::i16; }
35 virtual MVT::SimpleValueType getSetCCResultType(EVT VT) const;
35 virtual EVT getSetCCResultType(EVT VT) const;
3636 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
3737 virtual void ReplaceNodeResults(SDNode *N,
3838 SmallVectorImpl &Results,
438438 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
439439
440440 setBooleanContents(ZeroOrNegativeOneBooleanContent);
441 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent); // FIXME: Is this correct?
441442
442443 setStackPointerRegisterToSaveRestore(SPU::R1);
443444
497498 // Return the Cell SPU's SETCC result type
498499 //===----------------------------------------------------------------------===//
499500
500 MVT::SimpleValueType SPUTargetLowering::getSetCCResultType(EVT VT) const {
501 EVT SPUTargetLowering::getSetCCResultType(EVT VT) const {
501502 // i8, i16 and i32 are valid SETCC result types
502503 MVT::SimpleValueType retval;
503504
106106 virtual const char *getTargetNodeName(unsigned Opcode) const;
107107
108108 /// getSetCCResultType - Return the ValueType for ISD::SETCC
109 virtual MVT::SimpleValueType getSetCCResultType(EVT VT) const;
109 virtual EVT getSetCCResultType(EVT VT) const;
110110
111111 virtual MVT getShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
112112
5858 // MBlaze does not have i1 type, so use i32 for
5959 // setcc operations results (slt, sgt, ...).
6060 setBooleanContents(ZeroOrOneBooleanContent);
61 setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
6162
6263 // Set up the register classes
6364 addRegisterClass(MVT::i32, MBlaze::GPRRegisterClass);
186187 computeRegisterProperties();
187188 }
188189
189 MVT::SimpleValueType MBlazeTargetLowering::getSetCCResultType(EVT VT) const {
190 EVT MBlazeTargetLowering::getSetCCResultType(EVT VT) const {
190191 return MVT::i32;
191192 }
192193
101101 virtual const char *getTargetNodeName(unsigned Opcode) const;
102102
103103 /// getSetCCResultType - get the ISD::SETCC result ValueType
104 MVT::SimpleValueType getSetCCResultType(EVT VT) const;
104 EVT getSetCCResultType(EVT VT) const;
105105
106106 private:
107107 // Subtarget Info
7878
7979 setStackPointerRegisterToSaveRestore(MSP430::SPW);
8080 setBooleanContents(ZeroOrOneBooleanContent);
81 setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
8182 setSchedulingPreference(Sched::Latency);
8283
8384 // We have post-incremented loads / stores.
8787 // Mips does not have i1 type, so use i32 for
8888 // setcc operations results (slt, sgt, ...).
8989 setBooleanContents(ZeroOrOneBooleanContent);
90 setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
9091
9192 // Set up the register classes
9293 addRegisterClass(MVT::i32, Mips::CPURegsRegisterClass);
218219 return SVT == MVT::i32 || SVT == MVT::i16;
219220 }
220221
221 MVT::SimpleValueType MipsTargetLowering::getSetCCResultType(EVT VT) const {
222 EVT MipsTargetLowering::getSetCCResultType(EVT VT) const {
222223 return MVT::i32;
223224 }
224225
107107 virtual const char *getTargetNodeName(unsigned Opcode) const;
108108
109109 /// getSetCCResultType - get the ISD::SETCC result ValueType
110 MVT::SimpleValueType getSetCCResultType(EVT VT) const;
110 EVT getSetCCResultType(EVT VT) const;
111111
112112 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
113113 private:
4747 addRegisterClass(MVT::f64, PTX::RegF64RegisterClass);
4848
4949 setBooleanContents(ZeroOrOneBooleanContent);
50 setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
5051 setMinFunctionAlignment(2);
5152
5253 ////////////////////////////////////
105106 computeRegisterProperties();
106107 }
107108
108 MVT::SimpleValueType PTXTargetLowering::getSetCCResultType(EVT VT) const {
109 EVT PTXTargetLowering::getSetCCResultType(EVT VT) const {
109110 return MVT::i1;
110111 }
111112
7070 DebugLoc dl, SelectionDAG &DAG,
7171 SmallVectorImpl &InVals) const;
7272
73 virtual MVT::SimpleValueType getSetCCResultType(EVT VT) const;
73 virtual EVT getSetCCResultType(EVT VT) const;
7474
7575 private:
7676 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
369369 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand);
370370
371371 setBooleanContents(ZeroOrOneBooleanContent);
372 setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
372373
373374 if (TM.getSubtarget().isPPC64()) {
374375 setStackPointerRegisterToSaveRestore(PPC::X1);
468469 }
469470 }
470471
471 MVT::SimpleValueType PPCTargetLowering::getSetCCResultType(EVT VT) const {
472 EVT PPCTargetLowering::getSetCCResultType(EVT VT) const {
472473 return MVT::i32;
473474 }
474475
245245 virtual MVT getShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
246246
247247 /// getSetCCResultType - Return the ISD::SETCC ValueType
248 virtual MVT::SimpleValueType getSetCCResultType(EVT VT) const;
248 virtual EVT getSetCCResultType(EVT VT) const;
249249
250250 /// getPreIndexedAddressParts - returns true by value, base pointer and
251251 /// offset pointer and addressing mode by reference if the node's address
8080 setSchedulingPreference(Sched::RegPressure);
8181
8282 setBooleanContents(ZeroOrOneBooleanContent);
83 setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
8384
8485 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
8586 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
180180
181181 // X86 is weird, it always uses i8 for shift amounts and setcc results.
182182 setBooleanContents(ZeroOrOneBooleanContent);
183 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
184 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
183185
184186 // For 64-bit since we have so many registers use the ILP scheduler, for
185187 // 32-bit code use the register pressure specific scheduling.
709711 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
710712 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
711713 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
712 setOperationAction(ISD::VSETCC, (MVT::SimpleValueType)VT, Expand);
714 setOperationAction(ISD::SETCC, (MVT::SimpleValueType)VT, Expand);
713715 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
714716 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
715717 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
786788 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
787789 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
788790 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
789 setOperationAction(ISD::VSETCC, MVT::v4f32, Custom);
791 setOperationAction(ISD::SETCC, MVT::v4f32, Custom);
790792 }
791793
792794 if (!UseSoftFloat && Subtarget->hasXMMInt()) {
816818 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
817819 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
818820
819 setOperationAction(ISD::VSETCC, MVT::v2f64, Custom);
820 setOperationAction(ISD::VSETCC, MVT::v16i8, Custom);
821 setOperationAction(ISD::VSETCC, MVT::v8i16, Custom);
822 setOperationAction(ISD::VSETCC, MVT::v4i32, Custom);
821 setOperationAction(ISD::SETCC, MVT::v2f64, Custom);
822 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
823 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
824 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
823825
824826 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
825827 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
949951 }
950952
951953 if (Subtarget->hasSSE42() || Subtarget->hasAVX())
952 setOperationAction(ISD::VSETCC, MVT::v2i64, Custom);
954 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
953955
954956 if (!UseSoftFloat && Subtarget->hasAVX()) {
955957 addRegisterClass(MVT::v32i8, X86::VR256RegisterClass);
10011003 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
10021004 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
10031005
1004 setOperationAction(ISD::VSETCC, MVT::v32i8, Custom);
1005 setOperationAction(ISD::VSETCC, MVT::v16i16, Custom);
1006 setOperationAction(ISD::VSETCC, MVT::v8i32, Custom);
1007 setOperationAction(ISD::VSETCC, MVT::v4i64, Custom);
1006 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1007 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1008 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1009 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
10081010
10091011 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
10101012 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
11441146 }
11451147
11461148
1147 MVT::SimpleValueType X86TargetLowering::getSetCCResultType(EVT VT) const {
1148 return MVT::i8;
1149 EVT X86TargetLowering::getSetCCResultType(EVT VT) const {
1150 if (!VT.isVector()) return MVT::i8;
1151 return VT.changeVectorElementTypeToInteger();
11491152 }
11501153
11511154
83188321 }
83198322
83208323 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
8324
8325 if (Op.getValueType().isVector()) return LowerVSETCC(Op, DAG);
8326
83218327 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
83228328 SDValue Op0 = Op.getOperand(0);
83238329 SDValue Op1 = Op.getOperand(1);
83738379 static SDValue Lower256IntVETCC(SDValue Op, SelectionDAG &DAG) {
83748380 EVT VT = Op.getValueType();
83758381
8376 assert(VT.getSizeInBits() == 256 && Op.getOpcode() == ISD::VSETCC &&
8382 assert(VT.getSizeInBits() == 256 && Op.getOpcode() == ISD::SETCC &&
83778383 "Unsupported value type for operation");
83788384
83798385 int NumElems = VT.getVectorNumElements();
1003710043 SDNode* Node = Op.getNode();
1003810044 EVT ExtraVT = cast(Node->getOperand(1))->getVT();
1003910045 EVT VT = Node->getValueType(0);
10040
1004110046 if (Subtarget->hasSSE2() && VT.isVector()) {
1004210047 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
1004310048 ExtraVT.getScalarType().getSizeInBits();
1034310348 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
1034410349 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
1034510350 case ISD::SETCC: return LowerSETCC(Op, DAG);
10346 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
1034710351 case ISD::SELECT: return LowerSELECT(Op, DAG);
1034810352 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
1034910353 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
571571 /// DAG node.
572572 virtual const char *getTargetNodeName(unsigned Opcode) const;
573573
574 /// getSetCCResultType - Return the ISD::SETCC ValueType
575 virtual MVT::SimpleValueType getSetCCResultType(EVT VT) const;
574 /// getSetCCResultType - Return the value type to use for ISD::SETCC.
575 virtual EVT getSetCCResultType(EVT VT) const;
576576
577577 /// computeMaskedBitsForTargetNode - Determine which of the bits specified
578578 /// in Mask are known to be either zero or one and return them in the
8080
8181 // Use i32 for setcc operations results (slt, sgt, ...).
8282 setBooleanContents(ZeroOrOneBooleanContent);
83 setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
8384
8485 // XCore does not have the NodeTypes below.
8586 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
1717 #include "llvm/DerivedTypes.h"
1818 #include "llvm/Support/ErrorHandling.h"
1919 using namespace llvm;
20
21 EVT EVT::changeExtendedVectorElementTypeToInteger() const {
22 LLVMContext &Context = LLVMTy->getContext();
23 EVT IntTy = getIntegerVT(Context, getVectorElementType().getSizeInBits());
24 return getVectorVT(Context, IntTy, getVectorNumElements());
25 }
2026
2127 EVT EVT::getExtendedIntegerVT(LLVMContext &Context, unsigned BitWidth) {
2228 EVT VT;