llvm.org GIT mirror llvm / 27b1252
ARM: fixup more tests to specify the target more explicitly This changes the tests that were targeting ARM EABI to explicitly specify the environment rather than relying on the default. This breaks with the new Windows on ARM support when running the tests on Windows where the default environment is no longer EABI. Take the opportunity to avoid a pointless redirect (helps when trying to debug with providing a command line invocation which can be copy and pasted) and removing a few greps in favour of FileCheck. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205541 91177308-0d34-0410-b5e6-96231b3b80d8 Saleem Abdulrasool 5 years ago
222 changed file(s) with 565 addition(s) and 335 deletion(s). Raw diff Collapse all Expand all
None ; RUN: llc < %s -march=arm -mattr=+neon -mcpu=cortex-a9
0 ; RUN: llc -mtriple=arm-eabi -mattr=+neon -mcpu=cortex-a9 %s -o /dev/null
11
22 define arm_aapcs_vfpcc <4 x float> @foo(i8* nocapture %pBuffer, i32 %numItems) nounwind {
33 %1 = ptrtoint i8* %pBuffer to i32
None ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
11 ; pr4926
22
33 define void @test_vget_lanep16() nounwind {
None ; RUN: llc < %s -march=arm
0 ; RUN: llc -mtriple=arm-eabi %s -o /dev/null
11
22 define void @"java.lang.String::getChars"([84 x i8]* %method, i32 %base_pc, [788 x i8]* %thread) {
33 %1 = sub i32 undef, 48 ; [#uses=1]
None ; RUN: llc -march=arm -mattr=+neon < %s
1 ; Radar 7770501: Don't crash on SELECT and SELECT_CC with NEON vector values.
0 ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o /dev/null
1 ; rdar://7770501 : Don't crash on SELECT and SELECT_CC with NEON vector values.
22
33 define void @vDSP_FFT16_copv(float* nocapture %O, float* nocapture %I, i32 %Direction) nounwind {
44 entry:
None ; RUN: llc < %s -march=arm -mcpu=arm1136jf-s
0 ; RUN: llc -mtriple=arm-eabi -mcpu=arm1136jf-s %s -o /dev/null
11 ; Radar 7854640
22
33 define void @test() nounwind {
None ; RUN: llc < %s -march=arm -mattr=+neon -O0 -optimize-regalloc -regalloc=basic
0 ; RUN: llc -mtriple=arm-eabi -mattr=+neon -O0 -optimize-regalloc -regalloc=basic %s -o /dev/null
11
22 ; This test would crash the rewriter when trying to handle a spill after one of
33 ; the @llvm.arm.neon.vld3.v8i8 defined three parts of a register.
None ; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 %s -o - | FileCheck %s
11 ; Radar 7872877
22
33 define void @test(float* %fltp, i32 %packedValue, float* %table) nounwind {
None ; RUN: llc < %s -march=arm -mattr=+neon
1 ; Radar 8084742
0 ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o /dev/null
1 ; rdar://8084742
22
33 %struct.__int8x8x2_t = type { [2 x <8 x i8>] }
44
None ; RUN: llc < %s -march=arm -mattr=+neon
0 ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o /dev/null
11
22 @.str271 = external constant [21 x i8], align 4 ; <[21 x i8]*> [#uses=1]
33 @llvm.used = appending global [1 x i8*] [i8* bitcast (i32 (i32, i8**)* @main to i8*)], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0]
None ; RUN: llc -march=arm -mcpu=cortex-a8 < %s | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 %s -o - | FileCheck %s
11
22 ; Trigger multiple NEON stores.
33 ; CHECK: vst1.64
None ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
11 ; PR11319
22
33 @i8_res = global <2 x i8>
None ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
11 ; PR11319
22
33 @src1_v2i16 = global <2 x i16>
None ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
11
22 define <2 x i32> @test1(<2 x double>* %A) {
33 ; CHECK: test1
None ; RUN: llc < %s -march=arm -float-abi=soft -mcpu=cortex-a9 | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -float-abi=soft -mcpu=cortex-a9 %s -o - | FileCheck %s
11
22 @A = global <4 x float>
33
None ; RUN: llc < %s -march=arm -mcpu=cortex-a9 -enable-unsafe-fp-math
0 ; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a9 -enable-unsafe-fp-math %s -o /dev/null
11 ;target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:64:128-a0:0:64-n32-S64"
22 ;target triple = "armv7-none-linux-gnueabi"
33
None ; RUN: llc -O1 -march=arm -mcpu=cortex-a9 < %s | FileCheck -check-prefix=A9-CHECK %s
1 ; RUN: llc -O1 -march=arm -mcpu=swift < %s | FileCheck -check-prefix=SWIFT-CHECK %s
0 ; RUN: llc -O1 -mtriple=arm-eabi -mcpu=cortex-a9 %s -o - \
1 ; RUN: | FileCheck -check-prefix=A9-CHECK %s
2
3 ; RUN: llc -O1 -mtriple=arm-eabi -mcpu=swift %s -o - \
4 ; RUN: | FileCheck -check-prefix=SWIFT-CHECK %s
5
26 ; Check that swift doesn't use vmov.32. .
37
48 define <2 x i32> @testuvec(<2 x i32> %A, <2 x i32> %B) nounwind {
None ; RUN: llc -march=arm -mcpu=swift < %s | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -mcpu=swift %s -o - | FileCheck %s
11 ;
22
33 define void @f(i32 %x, i32* %p) nounwind ssp {
None ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
11
22 ; PR12281
33 ; Test generataion of code for vmull instruction when multiplying 128-bit
None ; RUN: llc < %s -march=arm -mcpu=arm7tdmi | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -mcpu=arm7tdmi %s -o - | FileCheck %s
11
22 ; movw is only legal for V6T2 and later.
33 ; rdar://12300648
None ; RUN: not llc < %s -march=arm -mcpu=cortex-a8 2>&1 | FileCheck %s
0 ; RUN: not llc -mtriple=arm-eabi -mcpu=cortex-a8 %s -o - 2>&1 | FileCheck %s
11
22 ; Check for error message:
33 ; CHECK: non-trivial scalar-to-vector conversion, possible invalid constraint for vector type
None ; RUN: not llc < %s -march=arm -mcpu=cortex-a8 2>&1 | FileCheck %s
0 ; RUN: not llc -mtriple=arm-eabi -mcpu=cortex-a8 %s -o - 2>&1 | FileCheck %s
11
22 ; Check for error message:
33 ; CHECK: scalar-to-vector conversion failed, possible invalid constraint for vector type
None ; RUN: llc < %s -march=arm -mattr=+neon -print-before=post-RA-sched > %t 2>&1 && FileCheck < %t %s
0 ; RUN: llc -mtriple=arm-eabi -mattr=+neon -print-before=post-RA-sched %s -o - 2>&1 \
1 ; RUN: | FileCheck %s
12
23 define void @vst(i8* %m, [4 x i64] %v) {
34 entry:
None RUN: llc -O0 -march=arm -asm-verbose < %S/../Inputs/DbgValueOtherTargets.ll | FileCheck %S/../Inputs/DbgValueOtherTargets.ll
0 RUN: llc -O0 -mtriple=arm-eabi -asm-verbose %S/../Inputs/DbgValueOtherTargets.ll -o - | FileCheck %S/../Inputs/DbgValueOtherTargets.ll
None ; RUN: llc < %s -march=arm -float-abi=hard -mcpu=cortex-a15 -mattr=+neon,+neonfp | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -float-abi=hard -mcpu=cortex-a15 -mattr=+neon,+neonfp %s -o - \
1 ; RUN: | FileCheck %s
12
23 ; This test checks that the VMLxForwarting feature is disabled for A15.
34 ; CHECK: fun_a:
None ; RUN: llc < %s -march=arm -mcpu=cortex-a15 | FileCheck %s
0 ; RUN: llc -mtriple=arm -mcpu=cortex-a15 %s -o - | FileCheck %s
11
22 ; CHECK: a
33 define i32 @a(i32 %x) {
0 ; REQUIRES: asserts
1 ; RUN: llc < %s -march=arm -stats 2>&1 | grep asm-printer | grep 4
1 ; RUN: llc -mtriple=arm-eabi -stats %s -o - 2>&1 | FileCheck %s
22
33 define i32 @t1(i32 %a) {
44 %b = mul i32 %a, 9
1313 %d = load i32* %c
1414 ret i32 %d
1515 }
16
17 ; CHECK: 4 asm-printer
18
None ; RUN: llc < %s -march=arm
0 ; RUN: llc -mtriple=arm-eabi %s -o /dev/null
11
22 ; Check that codegen for an addrspace cast succeeds without error.
33 define <4 x i32 addrspace(1)*> @f (<4 x i32*> %x) {
None ; RUN: llc < %s -march=arm | FileCheck -check-prefix=ARM %s
1 ; RUN: llc < %s -march=thumb | FileCheck -check-prefix=THUMB %s
2 ; RUN: llc < %s -march=thumb -mcpu=arm1156t2-s -mattr=+thumb2 \
0 ; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck -check-prefix=ARM %s
1 ; RUN: llc -mtriple=thumb-eabi %s -o - | FileCheck -check-prefix=THUMB %s
2 ; RUN: llc -mtriple=thumb-eabi -mcpu=arm1156t2-s -mattr=+thumb2 %s -o - \
33 ; RUN: | FileCheck -check-prefix=T2 %s
4 ; RUN: llc < %s -mtriple=thumbv8 | FileCheck -check-prefix=V8 %s
4 ; RUN: llc -mtriple=thumbv8-eabi %s -o - | FileCheck -check-prefix=V8 %s
55
66 ; FIXME: The -march=thumb test doesn't change if -disable-peephole is specified.
77
None ; RUN: llc < %s -march=arm
0 ; RUN: llc -mtriple=arm-eabi %s -o /dev/null
11
22 define void @frame_dummy() {
33 entry:
None ; RUN: llc < %s -march=arm -mattr=+vfp2 -no-integrated-as | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -mattr=+vfp2 -no-integrated-as %s -o - | FileCheck %s
11
22 define i32 @foo(float %scale, float %scale2) nounwind {
33 entry:
None ; RUN: llc < %s -march=arm | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s
11
22 ; This loop is rewritten with an indvar which counts down, which
33 ; frees up a register from holding the trip count.
None ; RUN: llc -march=arm -mcpu=cortex-a9 < %s | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a9 %s -o - | FileCheck %s
11
22 ; CHECK-LABEL: max:
33 define i32 @max(i8 %ctx, i32* %ptr, i32 %val)
None ; RUN: llc < %s -march=arm -mattr=+v6t2 | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -mattr=+v6t2 %s -o - | FileCheck %s
11
22 ; 4278190095 = 0xff00000f
33 define i32 @f1(i32 %a) {
None ; RUN: llc -march=arm -mattr=+v6t2 < %s | FileCheck %s
0 ; RUN: llc -mtriple=arm -mattr=+v6t2 %s -o - | FileCheck %s
11
22 %struct.F = type { [3 x i8], i8 }
33
None ; RUN: llc < %s -march=arm -mattr=+v7 | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -mattr=+v7 %s -o - | FileCheck %s
11
22 define i32 @sbfx1(i32 %a) {
33 ; CHECK: sbfx1
None ; RUN: llc < %s -march=arm | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s
11
22 define i32 @f1(i32 %a, i32 %b) {
33 %tmp = xor i32 %b, 4294967295
None ; RUN: llc < %s -march=arm | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s
11
22 define i32 @f1(i32 %a, i32 %b) {
33 entry:
None ; RUN: llc < %s -march=arm -mattr=+v4t | FileCheck %s -check-prefix=CHECKV4
1 ; RUN: llc < %s -march=arm -mattr=+v5t | FileCheck %s -check-prefix=CHECKV5
2 ; RUN: llc < %s -mtriple=armv6-linux-gnueabi\
3 ; RUN: -relocation-model=pic | FileCheck %s -check-prefix=CHECKELF
0 ; RUN: llc -mtriple=arm-eabi -mattr=+v4t %s -o - \
1 ; RUN: | FileCheck %s -check-prefix=CHECKV4
2
3 ; RUN: llc -mtriple=arm-eabi -mattr=+v5t %s -o - \
4 ; RUN: | FileCheck %s -check-prefix=CHECKV5
5
6 ; RUN: llc -mtriple=armv6-linux-gnueabi -relocation-model=pic %s -o - \
7 ; RUN: | FileCheck %s -check-prefix=CHECKELF
48
59 @t = weak global i32 ()* null ; [#uses=1]
610
None ; RUN: llc < %s -march=arm | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s
11
22 define i64 @f1(i64 %a, i64 %b) {
33 ; CHECK-LABEL: f1:
None ; RUN: llc < %s -march=arm -mattr=+v5t | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -mattr=+v5t %s -o - | FileCheck %s
11
22 declare i32 @llvm.ctlz.i32(i32, i1)
33
None ; RUN: llc < %s -march=arm -mattr=+v6,+vfp2 | \
1 ; RUN: grep vcmpe.f32
0 ; RUN: llc -mtriple=arm-eabi -mattr=+v6,+vfp2 %s -o - | FileCheck %s
21
32 define void @test3(float* %glob, i32 %X) {
43 entry:
1716 }
1817
1918 declare i32 @bar(...)
19
20 ; CHECK: vcmpe.f32
21
None ; RUN: llc < %s -march=arm -mattr=+v6t2 | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -mattr=+v6t2 %s -o - | FileCheck %s
11
22 declare i32 @llvm.cttz.i32(i32, i1)
33
None ; RUN: llc < %s -march=arm
0 ; RUN: llc -mtriple=arm-eabi %s -o /dev/null
11
22 %struct.comment = type { i8**, i32*, i32, i8* }
33 %struct.info = type { i32, i32, i32, i32, i32, i32, i32, i8* }
None ; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 %s -o - | FileCheck %s
11 ; rdar://12771555
22
33 define void @foo(i16* %ptr, i32 %a) nounwind {
None ; RUN: llc < %s -march=arm
0 ; RUN: llc -mtriple=arm-eabi %s -o /dev/null
1
12 @handler_installed.6144.b = external global i1 ; [#uses=1]
23
34 define void @__mf_sigusr1_respond() {
None ; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2
1 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=NFP0
2 ; RUN: llc < %s -mtriple=arm-eabi -mcpu=cortex-a8 | FileCheck %s -check-prefix=CORTEXA8
3 ; RUN: llc < %s -mtriple=arm-eabi -mcpu=cortex-a8 --enable-unsafe-fp-math | FileCheck %s -check-prefix=CORTEXA8U
4 ; RUN: llc < %s -mtriple=arm-darwin -mcpu=cortex-a8 | FileCheck %s -check-prefix=CORTEXA8U
5 ; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s -check-prefix=CORTEXA9
0 ; RUN: llc -mtriple=arm-eabi -mattr=+vfp2 %s -o - \
1 ; RUN: | FileCheck %s -check-prefix=VFP2
2
3 ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - \
4 ; RUN: | FileCheck %s -check-prefix=NFP0
5
6 ; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 %s -o - \
7 ; RUN: | FileCheck %s -check-prefix=CORTEXA8
8
9 ; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 --enable-unsafe-fp-math %s -o - \
10 ; RUN: | FileCheck %s -check-prefix=CORTEXA8U
11
12 ; RUN: llc -mtriple=arm-darwin -mcpu=cortex-a8 %s -o - \
13 ; RUN: | FileCheck %s -check-prefix=CORTEXA8U
14
15 ; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a9 %s -o - \
16 ; RUN: | FileCheck %s -check-prefix=CORTEXA9
617
718 define float @test(float %a, float %b) {
819 entry:
None ; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2
1 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=NFP0
2 ; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=CORTEXA8
3 ; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s -check-prefix=CORTEXA9
0 ; RUN: llc -mtriple=arm-eabi -mattr=+vfp2 %s -o - | FileCheck %s -check-prefix=VFP2
1 ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s -check-prefix=NFP0
2 ; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 %s -o - | FileCheck %s -check-prefix=CORTEXA8
3 ; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a9 %s -o - | FileCheck %s -check-prefix=CORTEXA9
44
55 define float @test(float %a, float %b) {
66 entry:
None ; RUN: llc < %s -march=arm -mattr=+vfp2
1 ; RUN: llc < %s -march=arm -mattr=vfp2 | not grep vstr.64
0 ; RUN: llc -mtriple=arm-eabi -mattr=+vfp2 %s -o /dev/null
1 ; RUN: llc -mtriple=arm-eabi -mattr=vfp2 %s -o - | FileCheck %s
22
33 define hidden i64 @__fixunsdfdi(double %x) nounwind readnone {
44 entry:
2626 bb10: ; preds = %entry
2727 ret i64 0
2828 }
29
30 ; CHECK-NOT: vstr.64
31
None ; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2
1 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=NEON
2 ; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=A8
3 ; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s -check-prefix=A9
4 ; RUN: llc < %s -mtriple=arm-linux-gnueabi -mcpu=cortex-a9 -float-abi=hard | FileCheck %s -check-prefix=HARD
0 ; RUN: llc -mtriple=arm-eabi -mattr=+vfp2 %s -o - | FileCheck %s -check-prefix=VFP2
1 ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s -check-prefix=NEON
2 ; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 %s -o - | FileCheck %s -check-prefix=A8
3 ; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a9 %s -o - | FileCheck %s -check-prefix=A9
4 ; RUN: llc -mtriple=arm-linux-gnueabi -mcpu=cortex-a9 -float-abi=hard %s -o - | FileCheck %s -check-prefix=HARD
55
66 define float @t1(float %acc, float %a, float %b) {
77 entry:
None ; RUN: llc < %s -march=arm -mattr=vfp2 | not grep fmdrr
1 ; RUN: llc < %s -march=arm -mattr=vfp2 | not grep fmrrd
0 ; RUN: llc -mtriple=arm-eabi -mattr=vfp2 %s -o - | FileCheck %s
21
32 ; naive codegen for this is:
43 ; _i:
109 %Y = bitcast double %X to i64
1110 ret i64 %Y
1211 }
12
13 ; CHECK-LABEL: test:
14 ; CHECK-NOT: fmdrr
15 ; CHECK-NOT: fmrrd
16
None ; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2
1 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=NEON
2 ; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=A8
0 ; RUN: llc -mtriple=arm-eabi -mattr=+vfp2 %s -o - | FileCheck %s -check-prefix=VFP2
1 ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s -check-prefix=NEON
2 ; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 %s -o - | FileCheck %s -check-prefix=A8
33
44 define float @t1(float %acc, float %a, float %b) {
55 entry:
None ; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2
1 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=NFP0
2 ; RUN: llc < %s -mtriple=arm-eabi -mcpu=cortex-a8 | FileCheck %s -check-prefix=CORTEXA8
3 ; RUN: llc < %s -mtriple=arm-eabi -mcpu=cortex-a8 --enable-unsafe-fp-math | FileCheck %s -check-prefix=CORTEXA8U
4 ; RUN: llc < %s -mtriple=arm-darwin -mcpu=cortex-a8 | FileCheck %s -check-prefix=CORTEXA8U
5 ; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s -check-prefix=CORTEXA9
0 ; RUN: llc -mtriple=arm-eabi -mattr=+vfp2 %s -o - \
1 ; RUN: | FileCheck %s -check-prefix=VFP2
2
3 ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - \
4 ; RUN: | FileCheck %s -check-prefix=NFP0
5
6 ; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 %s -o - \
7 ; RUN: | FileCheck %s -check-prefix=CORTEXA8
8
9 ; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 --enable-unsafe-fp-math %s -o - \
10 ; RUN: | FileCheck %s -check-prefix=CORTEXA8U
11
12 ; RUN: llc -mtriple=arm-darwin -mcpu=cortex-a8 %s -o - \
13 ; RUN: | FileCheck %s -check-prefix=CORTEXA8U
14
15 ; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a9 %s -o - \
16 ; RUN: | FileCheck %s -check-prefix=CORTEXA9
617
718 define float @test(float %a, float %b) {
819 entry:
None ; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2
1 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=NFP0
2 ; RUN: llc < %s -mtriple=arm-eabi -mcpu=cortex-a8 | FileCheck %s -check-prefix=CORTEXA8
3 ; RUN: llc < %s -mtriple=arm-eabi -mcpu=cortex-a8 --enable-unsafe-fp-math | FileCheck %s -check-prefix=CORTEXA8U
4 ; RUN: llc < %s -mtriple=arm-darwin -mcpu=cortex-a8 | FileCheck %s -check-prefix=CORTEXA8U
5 ; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s -check-prefix=CORTEXA9
0 ; RUN: llc -mtriple=arm-eabi -mattr=+vfp2 %s -o - \
1 ; RUN: | FileCheck %s -check-prefix=VFP2
2
3 ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - \
4 ; RUN: | FileCheck %s -check-prefix=NFP0
5
6 ; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 %s -o - \
7 ; RUN: | FileCheck %s -check-prefix=CORTEXA8
8
9 ; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 --enable-unsafe-fp-math %s -o - \
10 ; RUN: | FileCheck %s -check-prefix=CORTEXA8U
11
12 ; RUN: llc -mtriple=arm-darwin -mcpu=cortex-a8 %s -o - \
13 ; RUN: | FileCheck %s -check-prefix=CORTEXA8U
14
15 ; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a9 %s -o - \
16 ; RUN: | FileCheck %s -check-prefix=CORTEXA9
617
718 define float @test1(float* %a) {
819 entry:
None ; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2
1 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=NEON
2 ; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=A8
0 ; RUN: llc -mtriple=arm-eabi -mattr=+vfp2 %s -o - | FileCheck %s -check-prefix=VFP2
1 ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s -check-prefix=NEON
2 ; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 %s -o - | FileCheck %s -check-prefix=A8
33
44 define float @t1(float %acc, float %a, float %b) {
55 entry:
None ; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2
1 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=NEON
2 ; RUN: llc < %s -mtriple=arm-eabi -mcpu=cortex-a8 | FileCheck %s -check-prefix=A8
3 ; RUN: llc < %s -mtriple=arm-eabi -mcpu=cortex-a8 -regalloc=basic | FileCheck %s -check-prefix=A8
4 ; RUN: llc < %s -mtriple=arm-eabi -mcpu=cortex-a8 --enable-unsafe-fp-math | FileCheck %s -check-prefix=A8U
5 ; RUN: llc < %s -mtriple=arm-darwin -mcpu=cortex-a8 | FileCheck %s -check-prefix=A8U
0 ; RUN: llc -mtriple=arm-eabi -mattr=+vfp2 %s -o - \
1 ; RUN: | FileCheck %s -check-prefix=VFP2
2
3 ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - \
4 ; RUN: | FileCheck %s -check-prefix=NEON
5
6 ; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 %s -o - \
7 ; RUN: | FileCheck %s -check-prefix=A8
8
9 ; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 -regalloc=basic %s -o - \
10 ; RUN: | FileCheck %s -check-prefix=A8
11
12 ; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 --enable-unsafe-fp-math %s -o - \
13 ; RUN: | FileCheck %s -check-prefix=A8U
14
15 ; RUN: llc -mtriple=arm-darwin -mcpu=cortex-a8 %s -o - \
16 ; RUN: | FileCheck %s -check-prefix=A8U
617
718 define float @t1(float %acc, float %a, float %b) nounwind {
819 entry:
None ; RUN: llc < %s -march=arm -mattr=+v6,+vfp2 | grep vnmul.f64
1 ; RUN: llc < %s -march=arm -mattr=+v6,+vfp2 -enable-sign-dependent-rounding-fp-math | grep vmul.f64
0 ; RUN: llc -mtriple=arm-eabi -mattr=+v6,+vfp2 %s -o - | FileCheck %s
1
2 ; RUN: llc -mtriple=arm-eabi -mattr=+v6,+vfp2 -enable-sign-dependent-rounding-fp-math %s -o - \
3 ; RUN: | FileCheck %s -check-prefix CHECK-ROUNDING
4
25
36
47 define double @t1(double %a, double %b) {
811 ret double %tmp4
912 }
1013
14 ; CHECK: vnmul.f64
15 ; CHECK-ROUNDING: vmul.f64
16
None ; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s
1 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
2 ; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s
3 ; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -mattr=+vfp2 %s -o - | FileCheck %s
1 ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
2 ; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 %s -o - | FileCheck %s
3 ; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a9 %s -o - | FileCheck %s
44
55 define arm_aapcs_vfpcc float @test1(float %a, float %b) nounwind {
66 ; CHECK: vnmul.f32 s0, s0, s1
None ; RUN: llc < %s -march=arm -mattr=+v7 | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -mattr=+v7 %s -o - | FileCheck %s
11
22 define i32 @f(i32 %a) nounwind readnone optsize ssp {
33 entry:
None ; RUN: llc < %s -march=arm -mattr=+vfp2
0 ; RUN: llc -mtriple=arm-eabi -mattr=+vfp2 %s -o /dev/null
11
22 declare void @bar(i64 %x, i64 %y)
33
None ; RUN: llc < %s -march=arm -mattr=+neon -float-abi=soft | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -mattr=+neon -float-abi=soft %s -o - | FileCheck %s
11
22 ; CHECK: function1
33 ; CHECK-NOT: vmov
None ; RUN: llc -march=arm -mcpu=cortex-a9 -mattr=+vfp4 -enable-unsafe-fp-math < %s | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a9 -mattr=+vfp4 -enable-unsafe-fp-math %s -o - \
1 ; RUN: | FileCheck %s
12
23 ; CHECK: test1
34 define float @test1(float %x) {
None ; RUN: llc < %s -march=arm -float-abi=soft -mattr=+vfp2 | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -float-abi=soft -mattr=+vfp2 %s -o - | FileCheck %s
11
22 define float @f(i32 %a) {
33 ;CHECK-LABEL: f:
None ; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2
1 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=VFP2
2 ; RUN: llc < %s -mtriple=arm-eabi -mcpu=cortex-a8 | FileCheck %s -check-prefix=VFP2
3 ; RUN: llc < %s -mtriple=arm-eabi -mcpu=cortex-a8 --enable-unsafe-fp-math | FileCheck %s -check-prefix=NEON
4 ; RUN: llc < %s -mtriple=arm-darwin -mcpu=cortex-a8 | FileCheck %s -check-prefix=NEON
5 ; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s -check-prefix=VFP2
0 ; RUN: llc -mtriple=arm-eabi -mattr=+vfp2 %s -o - \
1 ; RUN: | FileCheck %s -check-prefix=VFP2
2
3 ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - \
4 ; RUN: | FileCheck %s -check-prefix=VFP2
5
6 ; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 %s -o - \
7 ; RUN: | FileCheck %s -check-prefix=VFP2
8
9 ; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 --enable-unsafe-fp-math %s -o - \
10 ; RUN: | FileCheck %s -check-prefix=NEON
11
12 ; RUN: llc -mtriple=arm-darwin -mcpu=cortex-a8 %s -o - \
13 ; RUN: | FileCheck %s -check-prefix=NEON
14
15 ; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a9 %s -o - \
16 ; RUN: | FileCheck %s -check-prefix=VFP2
617
718 define i32 @test1(float %a, float %b) {
819 ; VFP2-LABEL: test1:
None ; RUN: llc < %s -march=arm -mcpu=cortex-a8 -mattr=+vfp2 -enable-unsafe-fp-math | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 -mattr=+vfp2 -enable-unsafe-fp-math %s -o - \
1 ; RUN: | FileCheck %s
2
13 ; rdar://7461510
24 ; rdar://10964603
35
None ; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -mattr=+vfp2 %s -o - | FileCheck %s
11
22 define i32 @f1(float %a) {
33 ;CHECK-LABEL: f1:
None ; RUN: llc < %s -march=arm -mattr=+vfp3 | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -mattr=+vfp3 %s -o - | FileCheck %s
11
22 define float @t1(float %x) nounwind readnone optsize {
33 entry:
None ; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s --check-prefix=CHECK-VFP
1 ; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -mattr=+vfp2 %s -o - | FileCheck %s --check-prefix=CHECK-VFP
1 ; RUN: llc -mtriple=arm-apple-darwin %s -o - | FileCheck %s
22
33 define float @f1(double %x) {
44 ;CHECK-VFP-LABEL: f1:
None ; RUN: llc < %s -march=arm -float-abi=soft -mattr=+vfp2 | FileCheck %s
0 ; RUN: llc -mtriple=arm -float-abi=soft -mattr=+vfp2 %s -o - | FileCheck %s
11
22 define float @f1(float %a) {
33 ; CHECK-LABEL: f1:
None ; RUN: llc < %s -march=arm
0 ; RUN: llc -mtriple=arm-eabi %s -o /dev/null
11
22 define double @t(double %x, double %y) nounwind optsize {
33 entry:
None ; RUN: llc < %s -march=arm -mattr=+v6,+vfp2 | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -mattr=+v6,+vfp2 %s -o - | FileCheck %s
11
22 @i = weak global i32 0 ; [#uses=2]
33 @u = weak global i32 0 ; [#uses=2]
None ; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2
1 ; RUN: llc < %s -mtriple=arm-eabi -mcpu=cortex-a8 | FileCheck %s -check-prefix=NFP1
2 ; RUN: llc < %s -mtriple=arm-eabi -mcpu=cortex-a8 --enable-unsafe-fp-math | FileCheck %s -check-prefix=NFP1U
3 ; RUN: llc < %s -mtriple=arm-darwin -mcpu=cortex-a8 | FileCheck %s -check-prefix=NFP1U
4 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=NFP0
0 ; RUN: llc -mtriple=arm-eabi -mattr=+vfp2 %s -o - \
1 ; RUN: | FileCheck %s -check-prefix=VFP2
2
3 ; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 %s -o - \
4 ; RUN: | FileCheck %s -check-prefix=NFP1
5
6 ; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 --enable-unsafe-fp-math %s -o - \
7 ; RUN: | FileCheck %s -check-prefix=NFP1U
8
9 ; RUN: llc -mtriple=arm-darwin -mcpu=cortex-a8 %s -o - \
10 ; RUN: | FileCheck %s -check-prefix=NFP1U
11
12 ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - \
13 ; RUN: | FileCheck %s -check-prefix=NFP0
514
615 define float @test(float %a, float %b) {
716 entry:
None ; RUN: llc < %s -march=arm
1 ; RUN: llc < %s -mtriple=armv6-linux-gnueabi | grep mov | count 1
2 ; RUN: llc < %s -mtriple=armv6-linux-gnu --disable-fp-elim | \
3 ; RUN: grep mov | count 2
4 ; RUN: llc < %s -mtriple=armv6-apple-ios | grep mov | count 2
0 ; RUN: llc -mtriple=arm-eabi %s -o /dev/null
1 ; RUN: llc -mtriple=armv6-linux-gnueabi %s -o - | FileCheck %s
2
3 ; RUN: llc -mtriple=armv6-linux-gnu --disable-fp-elim %s -o - \
4 ; RUN: | FileCheck %s -check-prefix CHECK-FP-ELIM
5
6 ; RUN: llc -mtriple=armv6-apple-ios %s -o - \
7 ; RUN: | FileCheck %s -check-prefix CHECK-FP-ELIM
58
69 @str = internal constant [12 x i8] c"Hello World\00"
710
1114 }
1215
1316 declare i32 @puts(i8*)
17
18 ; CHECK: mov
19 ; CHECK-NOT: mov
20
21 ; CHECK-FP-ELIM: mov
22 ; CHECK-FP-ELIM: mov
23 ; CHECK-FP-ELIM-NOT: mov
24
None ; RUN: llc < %s -march=arm -mattr=+v4t | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -mattr=+v4t %s -o - | FileCheck %s
11
22 ;; Integer absolute value, should produce something as good as: ARM:
33 ;; movs r0, r0
None ; RUN: llc < %s -march arm -mcpu swift -verify-machineinstrs
0 ; RUN: llc -mtriple arm-eabi -mcpu swift -verify-machineinstrs %s -o /dev/null
11
22 declare i32 @f(i32 %p0, i32 %p1)
33
None ; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=A8
1 ; RUN: llc < %s -march=arm -mcpu=swift | FileCheck %s -check-prefix=SWIFT
0 ; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 %s -o - | FileCheck %s -check-prefix=A8
1 ; RUN: llc -mtriple=arm-eabi -mcpu=swift %s -o - | FileCheck %s -check-prefix=SWIFT
22
33 define i32 @t1(i32 %a, i32 %b) {
44 ; A8-LABEL: t1:
None ; RUN: llc < %s -march=arm -mattr=+v4t | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -mattr=+v4t %s -o - | FileCheck %s
11
22 define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) {
33 ; CHECK-LABEL: t1:
None ; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s
1 ; RUN: llc < %s -march=arm -mattr=+v4t | grep cmpne | count 1
2 ; RUN: llc < %s -march=arm -mattr=+v4t | grep bx | count 2
0 ; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 %s -o - | FileCheck %s
1 ; RUN: llc -mtriple=arm-eabi -mattr=+v4t %s -o - | FileCheck %s -check-prefix CHECK-V4-CMP
2 ; RUN: llc -mtriple=arm-eabi -mattr=+v4t %s -o - | FileCheck %s -check-prefix CHECK-V4-BX
33
44 define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) {
55 ; CHECK-LABEL: t1:
2121 %tmp15 = add i32 %b, %a
2222 ret i32 %tmp15
2323 }
24
25 ; CHECK-V4-CMP: cmpne
26 ; CHECK-V4-CMP-NOT: cmpne
27
28 ; CHECK-V4-BX: bx
29 ; CHECK-V4-BX: bx
30 ; CHECK-V4-BX-NOT: bx
31
None ; RUN: llc < %s -march=arm | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s
11
22 ; Do not if-convert when branches go to the different loops.
33 ; CHECK-LABEL: t:
None ; RUN: llc < %s -march=arm
0 ; RUN: llc -mtriple=arm-eabi %s -o /dev/null
11
22 define fastcc void @t() nounwind {
33 entry:
None ; RUN: llc < %s -march=arm
1 ; RUN: llc < %s -mtriple=arm-linux
0 ; RUN: llc -mtriple=arm-eabi %s -o /dev/null
1 ; RUN: llc -mtriple=arm-linux %s -o /dev/null
22
33 define void @foo(<8 x float>* %f, <8 x float>* %g, <4 x i64>* %y)
44 {
None ; RUN: llc < %s -march=arm | not grep CPI
0 ; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s
11
22 define i32 @test1(i32 %A) {
33 %B = add i32 %A, -268435441 ; [#uses=1]
1313 ret i32 %B
1414 }
1515
16 ; CHECK-NOT: CPI
17
18
None ; RUN: not llc < %s -march=arm -mcpu=cortex-a8 2>&1 | FileCheck %s
0 ; RUN: not llc -mtriple=arm-eabi -mcpu=cortex-a8 %s -o - 2>&1 | FileCheck %s
11
22 ; Check for error message:
33 ; CHECK: error: inline asm not supported yet: don't know how to handle tied indirect register inputs
None ; RUN: llc < %s -march=arm -no-integrated-as
0 ; RUN: llc -mtriple=arm-eabi -no-integrated-as %s -o /dev/null
11
22 ; Test ARM-mode "I" constraint, for any Data Processing immediate.
33 define i32 @testI(i32 %x) {
None ; RUN: llc < %s -march=arm -mattr=+v6
0 ; RUN: llc -mtriple=arm-eabi -mattr=+v6 %s -o /dev/null
11
22 define i32 @test1(i32 %tmp54) {
33 %tmp56 = tail call i32 asm "uxtb16 $0,$1", "=r,r"( i32 %tmp54 ) ; [#uses=1]
None ; RUN: llc < %s -march=arm -mattr=+vfp2
0 ; RUN: llc -mtriple=arm-eabi -mattr=+vfp2 %s -o /dev/null
11
22 define double @__ieee754_sqrt(double %x) {
33 %tmp2 = tail call double asm "fsqrtd ${0:P}, ${1:P}", "=w,w"( double %x )
None ; RUN: llc < %s -march=arm -float-abi=soft -mattr=+neon,+v6t2 -no-integrated-as | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -float-abi=soft -mattr=+neon,+v6t2 -no-integrated-as %s -o - \
1 ; RUN: | FileCheck %s
12
23 ; Radar 7449043
34 %struct.int32x4_t = type { <4 x i32> }
None ; RUN: llc < %s -march=arm | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s
11
22 define double @f(double %x) {
33 entry:
None ; RUN: llc < %s -march=arm -mattr=+v6
1 ; RUN: llc < %s -mtriple=arm-apple-ios -mattr=+v6 |\
2 ; RUN: grep mov | count 3
0 ; RUN: llc -mtriple=arm-eabi -mattr=+v6 %s -o /dev/null
1 ; RUN: llc -mtriple=arm-apple-ios -mattr=+v6 %s -o - | FileCheck %s
32
43 define i32 @test(i32 %x) {
54 %tmp = trunc i32 %x to i16 ; [#uses=1]
87 }
98
109 declare i32 @f(i32, i16)
10
11 ; CHECK: mov
12 ; CHECK: mov
13 ; CHECK: mov
14 ; CHECK-NOT: mov
15
None ; RUN: llc %s -o - -march=arm -mattr=+neon | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
11
22 ; This test checks that when inserting one (integer) element into a vector,
33 ; the vector is not spuriously copied. "vorr dX, dY, dY" is the way of moving
None ; RUN: llc < %s -march=arm | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s
11
22 define i32 @test1(i32 %X) {
33 ; CHECK: lsr{{.*}}#31
None ; RUN: llc < %s -march=arm
0 ; RUN: llc -mtriple=arm-eabi %s -o /dev/null
11
22 define void @test1() {
33 %tmp = alloca [ 64 x i32 ] , align 4
None ; RUN: llc < %s -march=arm | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s
11
22 define i32 @f1(i32* %v) {
33 ; CHECK-LABEL: f1:
None ; RUN: llc < %s -march=arm | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s
11
22 define i32 @test1(i8* %t1) nounwind {
33 ; CHECK: ldrb
None ; RUN: llc < %s -march=arm -mattr=+v4t | not grep mov
0 ; RUN: llc -mtriple=arm-eabi -mattr=+v4t %s -o - | FileCheck %s
11
22 define i32 @f1() {
33 %buf = alloca [32 x i32], align 4
2828 %tmp2 = zext i8 %tmp1 to i32
2929 ret i32 %tmp2
3030 }
31
32 ; CHECK-NOT: mov
33
None ; RUN: llc < %s -march=arm | FileCheck %s
1 ; RUN: llc < %s -march=arm -mcpu=swift | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s
1 ; RUN: llc -mtriple=arm-eabi -mcpu=swift %s -o - | FileCheck %s
22
33 ; CHECK-LABEL: test1:
44 ; CHECK: ldr {{.*, \[.*]}}, -r2
None ; RUN: llc < %s -march=arm | FileCheck %s
1 ; RUN: llc < %s -march=arm -mcpu=swift | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s
1 ; RUN: llc -mtriple=arm-eabi -mcpu=swift %s -o - | FileCheck %s
22
33 ; CHECK-LABEL: test1:
44 ; CHECK: ldr {{.*!}}
None ; RUN: llc < %s -march=arm > %t
1 ; RUN: grep ldrsb %t
2 ; RUN: grep ldrb %t
3 ; RUN: grep ldrsh %t
4 ; RUN: grep ldrh %t
5
0 ; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s
61
72 define i32 @f1(i8* %p) {
83 entry:
3126 %tmp4 = zext i16 %tmp to i32 ; [#uses=1]
3227 ret i32 %tmp4
3328 }
29
30 ; CHECK: ldrsb
31 ; CHECK: ldrb
32 ; CHECK: ldrsh
33 ; CHECK: ldrh
34
None ; RUN: llc < %s -march=arm | grep cmp | count 1
1
0 ; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s
21
32 define i1 @t1(i64 %x) {
43 %B = icmp slt i64 %x, 0
1413 %tmp = icmp ugt i32 %x, -1
1514 ret i1 %tmp
1615 }
16
17 ; CHECK: cmp
18 ; CHECK-NOT: cmp
19
None ; RUN: llc < %s -march=arm | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s
11
22 define i64 @f1() {
33 ; CHECK-LABEL: f1:
None ; RUN: llc < %s -march=arm | FileCheck %s
1 ; RUN: llc < %s -mtriple=armv7 | FileCheck %s --check-prefix=CHECK-V7
0 ; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s
1 ; RUN: llc -mtriple=armv7-eabi %s -o - | FileCheck %s --check-prefix=CHECK-V7
22 ; Check generated signed and unsigned multiply accumulate long.
33
44 define i64 @MACLongTest1(i32 %a, i32 %b, i64 %c) {
None ; RUN: llc < %s -march=arm | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s
11
22 define i64 @f0(i64 %A, i64 %B) {
33 ; CHECK-LABEL: f0:
None ; RUN: llc < %s -march=arm | grep lsl | grep -F "lsl #2]"
0 ; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s
11 ; Should use scaled addressing mode.
22
33 define void @sintzero(i32* %a) nounwind {
1616 return: ; preds = %cond_next
1717 ret void
1818 }
19
20 ; CHECK: lsl{{.*}}#2]
21
None ; RUN: llc < %s -march=arm | grep strb
1 ; RUN: llc < %s -march=arm | grep strh
0 ; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s
21
32 define void @f1() {
43 entry:
65 ret void
76 }
87
8 ; CHECK: strb
9
910 define void @f2() {
1011 entry:
1112 store i16 0, i16* null
1213 ret void
1314 }
15
16 ; CHECK: strh
17
None ; RUN: llc < %s -march=arm -mattr=+v6t2 | FileCheck %s
1 ; RUN: llc < %s -march=arm -mattr=+v6t2 -arm-use-mulops=false | FileCheck %s -check-prefix=NO_MULOPS
0 ; RUN: llc -mtriple=arm-eabi -mattr=+v6t2 %s -o - | FileCheck %s
1 ; RUN: llc -mtriple=arm-eabi -mattr=+v6t2 -arm-use-mulops=false %s -o - \
2 ; RUN: | FileCheck %s -check-prefix=NO_MULOPS
23
34 define i32 @f1(i32 %a, i32 %b, i32 %c) {
45 %tmp1 = mul i32 %a, %b
None ; RUN: llc < %s -march=arm | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s
11
22 define i32 @t9(i32 %v) nounwind readnone {
33 entry:
None ; RUN: llc < %s -march=arm -mattr=+v6 | FileCheck %s -check-prefix=V6
1 ; RUN: llc < %s -march=arm | FileCheck %s -check-prefix=V4
2 ; RUN: llc < %s -march=thumb -mcpu=cortex-m3 | FileCheck %s -check-prefix=M3
0 ; RUN: llc -mtriple=arm-eabi -mattr=+v6 %s -o - | FileCheck %s -check-prefix=V6
1 ; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s -check-prefix=V4
2 ; RUN: llc -mtriple=thumb-eabi -mcpu=cortex-m3 %s -o - | FileCheck %s -check-prefix=M3
33
44 define i32 @smulhi(i32 %x, i32 %y) nounwind {
55 ; V6-LABEL: smulhi:
None ; RUN: llc < %s -march=arm | grep mvn | count 9
0 ; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s
11
22 define i32 @f1() {
33 entry:
7171 %tmp102 = icmp eq i32 -2, %a ; [#uses=1]
7272 ret i1 %tmp102
7373 }
74
75 ; CHECK-LABEL: f1
76 ; CHECK: mvn
77 ; CHECK: mvn
78 ; CHECK: mvn
79 ; CHECK: mvn
80 ; CHECK: mvn
81 ; CHECK: mvn
82 ; CHECK: mvn
83 ; CHECK: mvn
84 ; CHECK: mvn
85 ; CHECK-NOT: mvn
86
None ; RUN: llc < %s -march=arm -mattr=+neon | grep vadd
0 ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
11
22 define <8 x i8> @t_i8x8(<8 x i8> %a, <8 x i8> %b) nounwind {
33 entry:
44 %0 = add <8 x i8> %a, %b
55 ret <8 x i8> %0
66 }
7
8 ; CHECK: vadd
9
None ; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a9 %s -o - | FileCheck %s
1
12 ; bug 15283
23 ; radar://13191881
34 ; CHECK: vfcmp
None ; RUN: llc < %s -march=arm -mattr=+neon -pre-RA-sched=source -disable-post-ra | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -mattr=+neon -pre-RA-sched=source -disable-post-ra %s -o - \
1 ; RUN: | FileCheck %s
12
23 define <8 x i8> @sdivi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
34 ;CHECK: vrecpe.f32
None ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
11
22 ; PR12540: ARM backend lowering of FP_ROUND v2f64 to v2f32.
33 define <2 x float> @vtrunc(<2 x double> %a) {
None ; RUN: llc < %s -march=arm -float-abi=soft -mattr=+neon | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -float-abi=soft -mattr=+neon %s -o - | FileCheck %s
11
22 ; CHECK: t1
33 ; CHECK: vldr d
None ; RUN: llc < %s -march=arm -float-abi=soft -mattr=+neon | FileCheck %s
1 ; RUN: llc < %s -march=arm -float-abi=soft -mcpu=swift | FileCheck %s --check-prefix=SWIFT
0 ; RUN: llc -mtriple=arm-eabi -float-abi=soft -mattr=+neon %s -o - | FileCheck %s
1 ; RUN: llc -mtriple=arm-eabi -float-abi=soft -mcpu=swift %s -o - | FileCheck %s --check-prefix=SWIFT
22
33 ; CHECK: t1
44 ; CHECK: vld1.64
None ; RUN: llc < %s -march=arm -mcpu=swift | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -mcpu=swift %s -o - | FileCheck %s
11
22 define float @fmin_ole(float %x) nounwind {
33 ;CHECK-LABEL: fmin_ole:
None ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
11
22 ;
33 define <4 x i16> @t1(<4 x i32> %a) nounwind {
None ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
11
22 define <4 x i32> @test1(<4 x i32> %a) nounwind {
33 ; CHECK-LABEL: test1:
None ; RUN: llc < %s -march=arm -mcpu=swift -verify-machineinstrs
0 ; RUN: llc -mtriple=arm-eabi -mcpu=swift -verify-machineinstrs %s -o /dev/null
1
12 %union.opcode.0.2.5.8.15.28 = type { i32 }
23
34 @opcode = external global %union.opcode.0.2.5.8.15.28, align 4
None ; RUN: llc < %s -march=arm -mattr=+v6 | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -mattr=+v6 %s -o - | FileCheck %s
11
22 ; CHECK: test1
33 ; CHECK: pkhbt r0, r0, r1, lsl #16
None ; RUN: llc -march=arm -mattr=+v4t < %s | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -mattr=+v4t %s -o - | FileCheck %s
1
12 ;
23
34 define i32 @test1(i1 %a, i32* %b) {
None ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
11 ; Implement ctpop with vcnt
22
33 define <8 x i8> @vcnt8(<8 x i8>* %A) nounwind {
None ; RUN: llc < %s -march=thumb -mattr=-thumb2 | not grep pld
1 ; RUN: llc < %s -march=thumb -mattr=+v7 | FileCheck %s -check-prefix=THUMB2
2 ; RUN: llc < %s -march=arm -mattr=+v7 | FileCheck %s -check-prefix=ARM
3 ; RUN: llc < %s -march=arm -mcpu=cortex-a9-mp | FileCheck %s -check-prefix=ARM-MP
0 ; RUN: llc -mtriple=thumb-eabi -mattr=-thumb2 %s -o - | FileCheck %s -check-prefix CHECK-T1
1 ; RUN: llc -mtriple=thumb-eabi -mattr=+v7 %s -o - | FileCheck %s -check-prefix=THUMB2
2 ; RUN: llc -mtriple=arm-eabi -mattr=+v7 %s -o - | FileCheck %s -check-prefix=ARM
3 ; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a9-mp %s -o - | FileCheck %s -check-prefix=ARM-MP
44 ; rdar://8601536
5
6 ; CHECK-T1-NOT: pld
57
68 define void @t1(i8* %ptr) nounwind {
79 entry:
None ; RUN: llc < %s -march=arm
0 ; RUN: llc -mtriple=arm-eabi %s -o /dev/null
11
22 define i32 @test() {
33 ret i32 0
None ; RUN: llc < %s -march=arm
0 ; RUN: llc -mtriple=arm-eabi %s -o /dev/null
11
22 define i32 @test(i32 %a1) {
33 ret i32 %a1
None ; RUN: llc < %s -march=arm
0 ; RUN: llc -mtriple=arm-eabi %s -o /dev/null
11
22 define i32 @test(i32 %a1, i32 %a2) {
33 ret i32 %a2
None ; RUN: llc < %s -march=arm
0 ; RUN: llc -mtriple=arm-eabi %s -o /dev/null
1
12 define i32 @test(i32 %a1, i32 %a2, i32 %a3) {
23 ret i32 %a3
34 }
None ; RUN: llc < %s -march=arm
0 ; RUN: llc -mtriple=arm-eabi %s -o /dev/null
11
22 define i32 @test(i32 %a1, i32 %a2, i32 %a3, i32 %a4) {
33 ret i32 %a4
None ; RUN: llc < %s -march=arm
0 ; RUN: llc -mtriple=arm-eabi %s -o /dev/null
11
22 define i32 @test(i32 %a1, i32 %a2, i32 %a3, i32 %a4, i32 %a5) {
33 ret i32 %a5
None ; RUN: llc < %s -march=arm -mattr=+vfp2
0 ; RUN: llc -mtriple=arm-eabi -mattr=+vfp2 %s -o /dev/null
11
22 define float @test_f32(float %a1, float %a2) {
33 ret float %a2
None ; RUN: llc < %s -march=arm -mattr=+vfp2
0 ; RUN: llc -mtriple=arm-eabi -mattr=+vfp2 %s -o /dev/null
11
22 define float @test_f32_arg5(float %a1, float %a2, float %a3, float %a4, float %a5) {
33 ret float %a5
None ; RUN: llc < %s -march=arm -mattr=+vfp2
0 ; RUN: llc -mtriple=arm-eabi -mattr=+vfp2 %s -o /dev/null
11
22 define double @test_f64(double %a1, double %a2) {
33 ret double %a2
None ; RUN: llc < %s -march=arm -mcpu=arm8 -mattr=+vfp2
0 ; RUN: llc -mtriple=arm-eabi -mcpu=arm8 -mattr=+vfp2 %s -o /dev/null
11
22 define double @test_double_arg_reg_split(i32 %a1, double %a2) {
33 ret double %a2
None ; RUN: llc < %s -march=arm -mattr=+vfp2
0 ; RUN: llc -mtriple=arm-eabi -mattr=+vfp2 %s -o /dev/null
11
22 define double @test_double_arg_split(i64 %a1, i32 %a2, double %a3) {
33 ret double %a3
None ; RUN: llc < %s -march=arm -mattr=+vfp2
0 ; RUN: llc -mtriple=arm-eabi -mattr=+vfp2 %s -o /dev/null
11
22 define double @test_double_arg_stack(i64 %a1, i32 %a2, i32 %a3, double %a4) {
33 ret double %a4
None ; RUN: llc < %s -march=arm -mattr=+vfp2
0 ; RUN: llc -mtriple=arm-eabi -mattr=+vfp2 %s -o /dev/null
11
22 define i128 @test_i128(i128 %a1, i128 %a2, i128 %a3) {
33 ret i128 %a3
None ; RUN: llc < %s -march=arm -mattr=+vfp2
0 ; RUN: llc -march=arm -mattr=+vfp2 %s -o /dev/null
11
22 define i64 @test_i64(i64 %a1, i64 %a2) {
33 ret i64 %a2
None ; RUN: llc < %s -march=arm -mattr=+vfp2
0 ; RUN: llc -march=arm -mattr=+vfp2 %s -o /dev/null
11
22 define i64 @test_i64_arg3(i64 %a1, i64 %a2, i64 %a3) {
33 ret i64 %a3
None ; RUN: llc < %s -march=arm -mattr=+vfp2
0 ; RUN: llc -mtriple=arm-eabi -mattr=+vfp2 %s -o /dev/null
11
22 define i64 @test_i64_arg_split(i64 %a1, i32 %a2, i64 %a3) {
33 ret i64 %a3
None ; RUN: llc < %s -march=arm
0 ; RUN: llc -mtriple=arm-eabi %s -o /dev/null
11
22 define void @test() {
33 ret void
None ; RUN: llc < %s -march=arm -mattr=+v6 | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -mattr=+v6 %s -o - | FileCheck %s
11
22 define i32 @test1(i32 %X) nounwind {
33 ; CHECK: test1
None ; RUN: llc < %s -march=arm -mattr=+v6t2 | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -mattr=+v6t2 %s -o - | FileCheck %s
11
22 define i32 @f1(i32 %a) {
33 entry:
None ; RUN: llc < %s -march=arm | FileCheck %s --check-prefix=ARM
1 ; RUN: llc < %s -march=arm -mcpu=arm1156t2-s -mattr=+thumb2 | \
2 ; RUN: FileCheck %s --check-prefix=ARMT2
3 ; RUN: llc < %s -march=thumb -mcpu=arm1156t2-s -mattr=+thumb2 | \
4 ; RUN: FileCheck %s --check-prefix=THUMB2
0 ; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s --check-prefix=ARM
1
2 ; RUN: llc -mtriple=arm-eabi -mcpu=arm1156t2-s -mattr=+thumb2 %s -o - \
3 ; RUN: | FileCheck %s --check-prefix=ARMT2
4
5 ; RUN: llc -mtriple=thumb-eabi -mcpu=arm1156t2-s -mattr=+thumb2 %s -o - \
6 ; RUN: | FileCheck %s --check-prefix=THUMB2
57
68 define i32 @t1(i32 %c) nounwind readnone {
79 entry:
None ; RUN: llc < %s -march=arm -mcpu=swift -verify-machineinstrs
0 ; RUN: llc -mtriple=arm-eabi -mcpu=swift -verify-machineinstrs %s -o /dev/null
1
12 define i32 @func(i32 %arg0, i32 %arg1) {
23 entry:
34 %cmp = icmp slt i32 %arg0, 10
None ; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s
1 ; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s --check-prefix=CHECK-VFP
2 ; RUN: llc < %s -mattr=+neon,+thumb2 -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefix=CHECK-NEON
0 ; RUN: llc -mtriple=arm-apple-darwin %s -o - | FileCheck %s
1
2 ; RUN: llc -mtriple=arm-eabi -mattr=+vfp2 %s -o - \
3 ; RUN: | FileCheck %s --check-prefix=CHECK-VFP
4
5 ; RUN: llc -mtriple=thumbv7-apple-darwin -mattr=+neon,+thumb2 %s -o - \
6 ; RUN: | FileCheck %s --check-prefix=CHECK-NEON
37
48 define i32 @f1(i32 %a.s) {
59 ;CHECK-LABEL: f1:
None ; RUN: llc < %s -mcpu=cortex-a8 -march=arm -asm-verbose=false | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 -asm-verbose=false %s -o - | FileCheck %s
11
22 define zeroext i1 @test0(i32 %x) nounwind {
33 ; CHECK-LABEL: test0:
None ; RUN: llc < %s -march=arm -mcpu=generic
1 ; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -mcpu=generic %s -o /dev/null
1 ; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 %s -o - | FileCheck %s
22
33 @x = weak global i16 0 ; [#uses=1]
44 @y = weak global i16 0 ; [#uses=0]
None ; RUN: llc < %s -march=arm
1 ; RUN: llc < %s -march=arm | grep add | count 1
0 ; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s
21
32 define void @f1() {
43 %c = alloca i8, align 1
98 ret i32 1
109 }
1110
11 ; CHECK: add
12 ; CHECK-NOT: add
1213
None ; RUN: llc < %s -march=arm | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s
11
22 define i16 @test1(i32* %X, i16* %A) {
33 ; CHECK-LABEL: test1:
None ; RUN: llc < %s -march=arm | \
1 ; RUN: grep "str.*\!" | count 2
0 ; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s
21
32 define void @test1(i32* %X, i32* %A, i32** %dest) {
43 %B = load i32* %A ; [#uses=1]
1514 store i16 %tmp, i16* %Y
1615 ret i16* %Y
1716 }
17
18 ; CHECK: str{{.*}}!
19 ; CHECK: str{{.*}}!
20 ; CHECK-NOT: str{{.*}}!
21
None ; RUN: llc < %s -march=arm | \
1 ; RUN: grep strb | count 1
2 ; RUN: llc < %s -march=arm | \
3 ; RUN: grep strh | count 1
0 ; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s
41
52 define void @test1(i32 %v, i16* %ptr) {
63 %tmp = trunc i32 %v to i16 ; [#uses=1]
1310 store i8 %tmp, i8* %ptr
1411 ret void
1512 }
13
14 ; CHECK: strh
15 ; CHECK-NOT: strh
16
17 ; CHECK: strb
18 ; CHECK-NOT: strb
19
None ; RUN: llc -march=arm -mcpu=cortex-a8 < %s | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 %s -o - | FileCheck %s
11
22 ; 171 = 0x000000ab
33 define i64 @f1(i64 %a) {
None ; RUN: llc < %s -march=arm -mattr=+v6 | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -mattr=+v6 %s -o - | FileCheck %s
11
22 define i32 @test0(i8 %A) {
33 ; CHECK: test0
None ; RUN: llc < %s -march=arm -print-machineinstrs=tailduplication -tail-dup-size=100 -enable-tail-merge=false -disable-cgp -o /dev/null 2>&1 | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -print-machineinstrs=tailduplication -tail-dup-size=100 \
1 ; RUN: -enable-tail-merge=false -disable-cgp %s -o /dev/null 2>&1 \
2 ; RUN: | FileCheck %s
13
24 ; CHECK: Machine code for function test0:
35 ; CHECK: Successors according to CFG: BB#1(4) BB#2(124)
None ; RUN: llc < %s -march=arm | grep ldrb.*7 | count 1
1 ; RUN: llc < %s -march=arm | grep ldrsb.*7 | count 1
0 ; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s
21
32 %struct.A = type { i8, i8, i8, i8, i16, i8, i8, %struct.B** }
43 %struct.B = type { float, float, i32, i32, i32, [0 x i8] }
2120 %tmp57 = sext i8 %tmp56 to i32
2221 ret i32 %tmp57
2322 }
23
24 ; CHECK: ldrb{{.*}}7
25 ; CHECK-NOT: ldrb{{.*}}7
26
27 ; CHECK: ldrsb{{.*}}7
28 ; CHECK-NOT: ldrsb{{.*}}7
29
None ; RUN: llc < %s -march=arm -mattr=+v4t | not grep orr
1 ; RUN: llc < %s -march=arm -mattr=+v4t | not grep mov
0 ; RUN: llc -mtriple=arm-eabi -mattr=+v4t %s -o - | FileCheck %s
21
32 define void @bar(i8* %P, i16* %Q) {
43 entry:
1514 store i32 %tmp, i32* %P1, align 1
1615 ret void
1716 }
17
18 ; CHECK-NOT: orr
19 ; CHECK-NOT: mov
20
None ; RUN: llc < %s -march=arm | grep tst
1 ; RUN: llc < %s -march=arm | grep teq
0 ; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s
21
32 define i32 @f(i32 %a) {
43 entry:
1514 %retval = select i1 %0, i32 20, i32 10 ; [#uses=1]
1615 ret i32 %retval
1716 }
17
18 ; CHECK: tst
19 ; CHECK: teq
20
0 ; Tests for the two-address instruction pass.
1 ; RUN: llc -march=arm -mcpu=cortex-a9 < %s | FileCheck %s
1 ; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a9 %s -o - | FileCheck %s
22
33 define void @PR13378() nounwind {
44 ; This was orriginally a crasher trying to schedule the instructions.
None ; RUN: llc < %s -march=arm -pre-RA-sched=source | FileCheck %s -check-prefix=EXPANDED
1 ; RUN: llc < %s -mtriple=armv6-apple-darwin -mcpu=cortex-a8 -mattr=-neon -arm-strict-align -pre-RA-sched=source | FileCheck %s -check-prefix=EXPANDED
2 ; RUN: llc < %s -mtriple=armv6-apple-darwin -mcpu=cortex-a8 | FileCheck %s -check-prefix=UNALIGNED
0 ; RUN: llc -mtriple=arm-eabi -pre-RA-sched=source %s -o - \
1 ; RUN: | FileCheck %s -check-prefix=EXPANDED
2
3 ; RUN: llc -mtriple=armv6-apple-darwin -mcpu=cortex-a8 -mattr=-neon -arm-strict-align -pre-RA-sched=source %s -o - \
4 ; RUN: | FileCheck %s -check-prefix=EXPANDED
5
6 ; RUN: llc -mtriple=armv6-apple-darwin -mcpu=cortex-a8 %s -o - \
7 ; RUN: | FileCheck %s -check-prefix=UNALIGNED
38
49 ; rdar://7113725
510 ; rdar://12091029
None ;RUN: llc < %s -march=arm -mattr=+v7 -mattr=+neon | FileCheck %s
0 ;RUN: llc -mtriple=arm-eabi -mattr=+v7 -mattr=+neon %s -o - | FileCheck %s
11
22 ;ALIGN = 1
33 ;SIZE = 64
None ; RUN: llc < %s -march=arm | grep movne | count 1
1 ; RUN: llc < %s -march=arm | grep moveq | count 1
0 ; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s
21
32 define i32 @f1(float %X, float %Y) {
43 %tmp = fcmp uno float %X, %Y
1110 %retval = select i1 %tmp, i32 1, i32 -1
1211 ret i32 %retval
1312 }
13
14 ; CHECK: movne
15 ; CHECK-NOT: movne
16
17 ; CHECK: moveq
18 ; CHECK-NOT: moveq
19
None ; RUN: llc < %s -march=arm -mattr=+v6 | grep uxtb | count 1
1 ; RUN: llc < %s -march=arm -mattr=+v6 | grep uxtab | count 1
2 ; RUN: llc < %s -march=arm -mattr=+v6 | grep uxth | count 1
0 ; RUN: llc -mtriple=arm-eabi -mattr=+v6 %s -o - | FileCheck %s
31
42 define zeroext i8 @test1(i32 %A.u) {
53 %B.u = trunc i32 %A.u to i8
2119 %F.u = zext i16 %E.u to i32
2220 ret i32 %F.u
2321 }
22
23 ; CHECK: uxtb
24 ; CHECK-NOT: uxtb
25
26 ; CHECK: uxtab
27 ; CHECK-NOT: uxtab
28
29 ; CHECK: uxth
30 ; CHECK-NOT: uxth
31
None ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
11
22 define <8 x i8> @vabas8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
33 ;CHECK-LABEL: vabas8:
None ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
11
22 define <8 x i8> @vabds8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
33 ;CHECK-LABEL: vabds8:
None ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
11
22 define <8 x i8> @vabss8(<8 x i8>* %A) nounwind {
33 ;CHECK-LABEL: vabss8:
None ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
11
22 define <8 x i8> @vaddi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
33 ;CHECK-LABEL: vaddi8:
None ; RUN: llc < %s -march=arm
0 ; RUN: llc -mtriple=arm-eabi %s -o /dev/null
1
12 @str = internal constant [43 x i8] c"Hello World %d %d %d %d %d %d %d %d %d %d\0A\00" ; <[43 x i8]*> [#uses=1]
23
34 define i32 @main() {
None ; RUN: llc < %s -march=arm -mattr=+neon -mcpu=cortex-a8 | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -mattr=+neon -mcpu=cortex-a8 %s -o - | FileCheck %s
11
22 define <8 x i8> @v_andi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
33 ;CHECK-LABEL: v_andi8:
None ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
11
22 ; rdar://12471808
33
None ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
11
22 define <8 x i8> @vceqi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
33 ;CHECK-LABEL: vceqi8:
None ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
11
22 define <8 x i8> @vcges8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
33 ;CHECK-LABEL: vcges8:
None ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
1 ; RUN: llc < %s -march=arm -mattr=+neon -regalloc=basic | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
1 ; RUN: llc -mtriple=arm-eabi -mattr=+neon -regalloc=basic %s -o - | FileCheck %s
22
33 define <8 x i8> @vcgts8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
44 ;CHECK-LABEL: vcgts8:
None ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
11 ; NB: this tests vcnt, vclz, and vcls
22
33 define <8 x i8> @vcnt8(<8 x i8>* %A) nounwind {
None ; RUN: llc < %s -march=arm -float-abi=soft -mattr=+neon | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -float-abi=soft -mattr=+neon %s -o - | FileCheck %s
11
22 define <16 x i8> @vcombine8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
33 ; CHECK: vcombine8
None ; RUN: llc < %s -march=arm -mattr=+neon,+fp16 | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -mattr=+neon,+fp16 %s -o - | FileCheck %s
11
22 define <2 x i32> @vcvt_f32tos32(<2 x float>* %A) nounwind {
33 ;CHECK-LABEL: vcvt_f32tos32:
None ; RUN: llc < %s -march=arm -float-abi=soft -mattr=+neon -verify-machineinstrs | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -float-abi=soft -mattr=+neon -verify-machineinstrs %s -o - \
1 ; RUN: | FileCheck %s
12
23 define <8 x i8> @v_dup8(i8 %A) nounwind {
34 ;CHECK-LABEL: v_dup8:
None ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
11
22 define <8 x i8> @test_vextd(<8 x i8>* %A, <8 x i8>* %B) nounwind {
33 ;CHECK-LABEL: test_vextd:
None ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
11
22 ; This tests fcmp operations that do not map directly to NEON instructions.
33
None ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
11
22 define <8 x i8> @vhadds8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
33 ;CHECK-LABEL: vhadds8:
None ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
11
22 define <8 x i8> @vhsubs8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
33 ;CHECK-LABEL: vhsubs8:
None ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
0 ; RUN: llc -mtriple=arm -mattr=+neon %s -o - | FileCheck %s
11
22 ; This tests icmp operations that do not map directly to NEON instructions.
33 ; Not-equal (ne) operations are implemented by VCEQ/VMVN. Less-than (lt/ult)
None ; RUN: llc < %s -march=arm -float-abi=soft -mattr=+neon | FileCheck %s
1 ; RUN: llc < %s -march=arm -float-abi=soft -mattr=+neon -regalloc=basic | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -float-abi=soft -mattr=+neon %s -o - | FileCheck %s
1
2 ; RUN: llc -mtriple=arm-eabi -float-abi=soft -mattr=+neon -regalloc=basic %s -o - \
3 ; RUN: | FileCheck %s
24
35 define <8 x i8> @vld1i8(i8* %A) nounwind {
46 ;CHECK-LABEL: vld1i8:
None ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
11
22 %struct.__neon_int8x8x2_t = type { <8 x i8>, <8 x i8> }
33 %struct.__neon_int16x4x2_t = type { <4 x i16>, <4 x i16> }
None ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
1 ; RUN: llc < %s -march=arm -mattr=+neon -regalloc=basic | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o -| FileCheck %s
1 ; RUN: llc -mtriple=arm-eabi -mattr=+neon -regalloc=basic %s -o - | FileCheck %s
22
33 %struct.__neon_int8x8x3_t = type { <8 x i8>, <8 x i8>, <8 x i8> }
44 %struct.__neon_int16x4x3_t = type { <4 x i16>, <4 x i16>, <4 x i16> }
None ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
11
22 %struct.__neon_int8x8x4_t = type { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> }
33 %struct.__neon_int16x4x4_t = type { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> }
None ; RUN: llc < %s -march=arm -float-abi=soft -mattr=+neon | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -float-abi=soft -mattr=+neon %s -o - | FileCheck %s
11
22 define <8 x i8> @vld1dupi8(i8* %A) nounwind {
33 ;CHECK-LABEL: vld1dupi8:
None ; RUN: llc < %s -march=arm -float-abi=soft -mattr=+neon | FileCheck %s
1 ; RUN: llc < %s -march=arm -float-abi=soft -mattr=+neon -regalloc=basic | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -float-abi=soft -mattr=+neon %s -o - | FileCheck %s
1
2 ; RUN: llc -mtriple=arm-eabi -float-abi=soft -mattr=+neon -regalloc=basic %s -o - \
3 ; RUN: | FileCheck %s
24
35 define <8 x i8> @vld1lanei8(i8* %A, <8 x i8>* %B) nounwind {
46 ;CHECK-LABEL: vld1lanei8:
None ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
11
22 define <8 x i8> @vmins8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
33 ;CHECK-LABEL: vmins8:
None ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
11
22 define <8 x i8> @vmlai8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8> * %C) nounwind {
33 ;CHECK-LABEL: vmlai8:
None ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
11
22 define <8 x i8> @vmlsi8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8> * %C) nounwind {
33 ;CHECK-LABEL: vmlsi8:
None ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
11
22 define <8 x i8> @v_movi8() nounwind {
33 ;CHECK-LABEL: v_movi8:
None ; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 %s -o - | FileCheck %s
11
22 define <8 x i8> @vmuli8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
33 ;CHECK-LABEL: vmuli8:
None ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
11
22 define <8 x i8> @vnegs8(<8 x i8>* %A) nounwind {
33 ;CHECK-LABEL: vnegs8:
None ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
11
22 define <4 x i16> @vpadals8(<4 x i16>* %A, <8 x i8>* %B) nounwind {
33 ;CHECK-LABEL: vpadals8:
None ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
11
22 define <8 x i8> @vpaddi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
33 ;CHECK-LABEL: vpaddi8:
None ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
11
22 define <8 x i8> @vpmins8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
33 ;CHECK-LABEL: vpmins8:
None ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
11
22 define <8 x i8> @vqadds8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
33 ;CHECK-LABEL: vqadds8:
None ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
11
22 define <8 x i8> @vqshls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
33 ;CHECK-LABEL: vqshls8:
None ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
11
22 define <8 x i8> @vqshrns8(<8 x i16>* %A) nounwind {
33 ;CHECK-LABEL: vqshrns8:
None ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
11
22 define <8 x i8> @vqsubs8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
33 ;CHECK-LABEL: vqsubs8:
None ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
11
22 define <2 x i32> @vrecpei32(<2 x i32>* %A) nounwind {
33 ;CHECK-LABEL: vrecpei32:
None ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
11
22 define <8 x i8> @test_vrev64D8(<8 x i8>* %A) nounwind {
33 ;CHECK-LABEL: test_vrev64D8:
0 ; RUN: opt < %s -cost-model -analyze -mtriple=thumbv7-apple-ios6.0.0 -march=arm -mcpu=cortex-a8 | FileCheck %s --check-prefix=COST
1 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
1 ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
22 ; Make sure that ARM backend with NEON handles vselect.
33
44 define void @vmax_v4i32(<4 x i32>* %m, <4 x i32> %a, <4 x i32> %b) {
None ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
11
22 define <8 x i8> @vshls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
33 ;CHECK-LABEL: vshls8:
None ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
11
22 define <8 x i8> @vsli8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
33 ;CHECK-LABEL: vsli8:
None ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
11
22 define <8 x i8> @vshls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
33 ;CHECK-LABEL: vshls8:
None ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
11
22 define <8 x i16> @vshlls8(<8 x i8>* %A) nounwind {
33 ;CHECK-LABEL: vshlls8:
None ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
11
22 define <8 x i8> @vshrns8(<8 x i16>* %A) nounwind {
33 ;CHECK-LABEL: vshrns8:
None ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
11
22 define <8 x i8> @vsras8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
33 ;CHECK-LABEL: vsras8:
None ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
11
22 define void @vst1i8(i8* %A, <8 x i8>* %B) nounwind {
33 ;CHECK-LABEL: vst1i8:
None ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
11
22 define void @vst2i8(i8* %A, <8 x i8>* %B) nounwind {
33 ;CHECK-LABEL: vst2i8:
None ; RUN: llc < %s -march=arm -mattr=+neon -fast-isel=0 -O0 | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -mattr=+neon -fast-isel=0 -O0 %s -o - | FileCheck %s
11
22 define void @vst3i8(i8* %A, <8 x i8>* %B) nounwind {
33 ;CHECK-LABEL: vst3i8:
None ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
11
22 define void @vst4i8(i8* %A, <8 x i8>* %B) nounwind {
33 ;CHECK-LABEL: vst4i8:
None ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
0 ; RUN: llc -mtriple=arm -mattr=+neon %s -o - | FileCheck %s
11
22 define void @vst1lanei8(i8* %A, <8 x i8>* %B) nounwind {
33 ;CHECK-LABEL: vst1lanei8:
None ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
11
22 define <8 x i8> @vsubi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
33 ;CHECK-LABEL: vsubi8:
None ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
11
22 %struct.__neon_int8x8x2_t = type { <8 x i8>, <8 x i8> }
33 %struct.__neon_int8x8x3_t = type { <8 x i8>, <8 x i8>, <8 x i8> }
None ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
11
22 define <8 x i8> @vtrni8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
33 ;CHECK-LABEL: vtrni8:
None ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
11
22 define <8 x i8> @vuzpi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
33 ;CHECK-LABEL: vuzpi8:
None ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
0 ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
11
22 define <8 x i8> @vzipi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
33 ;CHECK-LABEL: vzipi8:
None ; RUN: llc < %s -march=arm | grep .weak.*f
1 ; RUN: llc < %s -march=arm | grep .weak.*h
0 ; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s
21
32 define weak i32 @f() {
43 entry:
1312
1413 declare extern_weak void @h()
1514
15 ; CHECK: {{.}}weak{{.*}}f
16 ; CHECK: {{.}}weak{{.*}}h
17
None ; RUN: llc < %s -march=arm | grep .weak
0 ; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s
11
22 define i32 @f(i32 %a) {
33 entry:
1515 }
1616
1717 declare extern_weak i32 @test_weak(...)
18
19 ; CHECK: {{.}}weak
20
None @ RUN: llvm-mc -arch arm %s
0 @ RUN: llvm-mc -triple arm-eabi %s -o - | FileCheck %s
1
12 @ CHECK: test:
2 @ CHECK: br r1
3 @ CHECK: bl r1
34 test:
45 bl r1
None // RUN: not llvm-mc -arch arm -mattr=+v5te %s 2>&1 | FileCheck %s
0 // RUN: not llvm-mc -triple arm-eabi -mattr=+v5te %s -o /dev/null 2>&1 | FileCheck %s
11 //
22 // rdar://14479793
33
None // RUN: not llvm-mc -arch thumb -mattr=+thumb2 \
1 // RUN: < %s >/dev/null 2> %t
2 // RUN: grep "error: destination operands can't be identical" %t | count 4
3 // rdar://14479780
0 @ RUN: not llvm-mc -triple thumb-eabi -mattr=+thumb2 %s -o /dev/null 2>&1 \
1 @ RUN: | FileCheck %s
2
3 @ rdar://14479780
44
55 ldrd r0, r0, [pc, #0]
66 ldrd r0, r0, [r1, #4]
77 ldrd r0, r0, [r1], #4
88 ldrd r0, r0, [r1, #4]!
9
10 @ CHECK: error: destination operands can't be identical
11 @ CHECK: error: destination operands can't be identical
12 @ CHECK: error: destination operands can't be identical
13 @ CHECK: error: destination operands can't be identical
14 @ CHECK-NOT: error: destination operands can't be identical
15