llvm.org GIT mirror llvm / 27ad7c2
LivePhysRegs/IfConversion: Change some types from unsigned to MCPhysReg; NFC Change the type in a couple of lists and sets that only store physical registers from unsigned to MCPhysRegs. The later is only 16bits and saves us a bit of memory. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346254 91177308-0d34-0410-b5e6-96231b3b80d8 Matthias Braun 11 months ago
7 changed file(s) with 31 addition(s) and 30 deletion(s). Raw diff Collapse all Expand all
4747 /// when walking backward/forward through a basic block.
4848 class LivePhysRegs {
4949 const TargetRegisterInfo *TRI = nullptr;
50 SparseSet LiveRegs;
50 using RegisterSet = SparseSet>;
51 RegisterSet LiveRegs;
5152
5253 public:
5354 /// Constructs an unitialized set. init() needs to be called to initialize it.
7576 bool empty() const { return LiveRegs.empty(); }
7677
7778 /// Adds a physical register and all its sub-registers to the set.
78 void addReg(unsigned Reg) {
79 void addReg(MCPhysReg Reg) {
7980 assert(TRI && "LivePhysRegs is not initialized.");
8081 assert(Reg <= TRI->getNumRegs() && "Expected a physical register.");
8182 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
8586
8687 /// Removes a physical register, all its sub-registers, and all its
8788 /// super-registers from the set.
88 void removeReg(unsigned Reg) {
89 void removeReg(MCPhysReg Reg) {
8990 assert(TRI && "LivePhysRegs is not initialized.");
9091 assert(Reg <= TRI->getNumRegs() && "Expected a physical register.");
9192 for (MCRegAliasIterator R(Reg, TRI, true); R.isValid(); ++R)
9495
9596 /// Removes physical registers clobbered by the regmask operand \p MO.
9697 void removeRegsInMask(const MachineOperand &MO,
97 SmallVectorImplunsigned, const MachineOperand*>> *Clobbers =
98 SmallVectorImplMCPhysReg, const MachineOperand*>> *Clobbers =
9899 nullptr);
99100
100101 /// Returns true if register \p Reg is contained in the set. This also
102103 /// addReg() always adds all sub-registers to the set as well.
103104 /// Note: Returns false if just some sub registers are live, use available()
104105 /// when searching a free register.
105 bool contains(unsigned Reg) const { return LiveRegs.count(Reg); }
106 bool contains(MCPhysReg Reg) const { return LiveRegs.count(Reg); }
106107
107108 /// Returns true if register \p Reg and no aliasing register is in the set.
108 bool available(const MachineRegisterInfo &MRI, unsigned Reg) const;
109 bool available(const MachineRegisterInfo &MRI, MCPhysReg Reg) const;
109110
110111 /// Remove defined registers and regmask kills from the set.
111112 void removeDefs(const MachineInstr &MI);
125126 /// defined or clobbered by a regmask. The operand will identify whether this
126127 /// is a regmask or register operand.
127128 void stepForward(const MachineInstr &MI,
128 SmallVectorImplunsigned, const MachineOperand*>> &Clobbers);
129 SmallVectorImplMCPhysReg, const MachineOperand*>> &Clobbers);
129130
130131 /// Adds all live-in registers of basic block \p MBB.
131132 /// Live in registers are the registers in the blocks live-in list and the
142143 /// registers.
143144 void addLiveOutsNoPristines(const MachineBasicBlock &MBB);
144145
145 using const_iterator = SparseSet::const_iterator;
146 using const_iterator = RegisterSet::const_iterator;
146147
147148 const_iterator begin() const { return LiveRegs.begin(); }
148149 const_iterator end() const { return LiveRegs.end(); }
8484 bool empty() const { return Units.none(); }
8585
8686 /// Adds register units covered by physical register \p Reg.
87 void addReg(unsigned Reg) {
87 void addReg(MCPhysReg Reg) {
8888 for (MCRegUnitIterator Unit(Reg, TRI); Unit.isValid(); ++Unit)
8989 Units.set(*Unit);
9090 }
9191
9292 /// Adds register units covered by physical register \p Reg that are
9393 /// part of the lanemask \p Mask.
94 void addRegMasked(unsigned Reg, LaneBitmask Mask) {
94 void addRegMasked(MCPhysReg Reg, LaneBitmask Mask) {
9595 for (MCRegUnitMaskIterator Unit(Reg, TRI); Unit.isValid(); ++Unit) {
9696 LaneBitmask UnitMask = (*Unit).second;
9797 if (UnitMask.none() || (UnitMask & Mask).any())
100100 }
101101
102102 /// Removes all register units covered by physical register \p Reg.
103 void removeReg(unsigned Reg) {
103 void removeReg(MCPhysReg Reg) {
104104 for (MCRegUnitIterator Unit(Reg, TRI); Unit.isValid(); ++Unit)
105105 Units.reset(*Unit);
106106 }
114114 void addRegsInMask(const uint32_t *RegMask);
115115
116116 /// Returns true if no part of physical register \p Reg is live.
117 bool available(unsigned Reg) const {
117 bool available(MCPhysReg Reg) const {
118118 for (MCRegUnitIterator Unit(Reg, TRI); Unit.isValid(); ++Unit) {
119119 if (Units.test(*Unit))
120120 return false;
272272 void PredicateBlock(BBInfo &BBI,
273273 MachineBasicBlock::iterator E,
274274 SmallVectorImpl &Cond,
275 SmallSet<unsigned, 4> *LaterRedefs = nullptr);
275 SmallSet<MCPhysReg, 4> *LaterRedefs = nullptr);
276276 void CopyAndPredicateBlock(BBInfo &ToBBI, BBInfo &FromBBI,
277277 SmallVectorImpl &Cond,
278278 bool IgnoreBr = false);
13651365 // Before stepping forward past MI, remember which regs were live
13661366 // before MI. This is needed to set the Undef flag only when reg is
13671367 // dead.
1368 SparseSet<unsigned> LiveBeforeMI;
1368 SparseSet<MCPhysReg, identity> LiveBeforeMI;
13691369 LiveBeforeMI.setUniverse(TRI->getNumRegs());
13701370 for (unsigned Reg : Redefs)
13711371 LiveBeforeMI.insert(Reg);
13721372
1373 SmallVectorunsigned, const MachineOperand*>, 4> Clobbers;
1373 SmallVectorMCPhysReg, const MachineOperand*>, 4> Clobbers;
13741374 Redefs.stepForward(MI, Clobbers);
13751375
13761376 // Now add the implicit uses for each of the clobbered values.
17391739
17401740 if (MRI->tracksLiveness()) {
17411741 for (const MachineInstr &MI : make_range(MBB1.begin(), DI1)) {
1742 SmallVectorunsigned, const MachineOperand*>, 4> Dummy;
1742 SmallVectorMCPhysReg, const MachineOperand*>, 4> Dummy;
17431743 Redefs.stepForward(MI, Dummy);
17441744 }
17451745 }
18051805 // generate:
18061806 // sub r0, r1, #1
18071807 // addne r0, r1, #1
1808 SmallSet RedefsByFalse;
1809 SmallSet<unsigned, 4> ExtUses;
1808 SmallSet<MCPhysReg, 4> RedefsByFalse;
1809 SmallSet ExtUses;
18101810 if (TII->isProfitableToUnpredicate(MBB1, MBB2)) {
18111811 for (const MachineInstr &FI : make_range(MBB2.begin(), DI2)) {
18121812 if (FI.isDebugInstr())
18131813 continue;
1814 SmallVector<unsigned, 4> Defs;
1814 SmallVector<MCPhysReg, 4> Defs;
18151815 for (const MachineOperand &MO : FI.operands()) {
18161816 if (!MO.isReg())
18171817 continue;
18291829 }
18301830 }
18311831
1832 for (unsigned Reg : Defs) {
1832 for (MCPhysReg Reg : Defs) {
18331833 if (!ExtUses.count(Reg)) {
18341834 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
18351835 SubRegs.isValid(); ++SubRegs)
19751975 }
19761976
19771977 static bool MaySpeculate(const MachineInstr &MI,
1978 SmallSet<unsigned, 4> &LaterRedefs) {
1978 SmallSet<MCPhysReg, 4> &LaterRedefs) {
19791979 bool SawStore = true;
19801980 if (!MI.isSafeToMove(nullptr, SawStore))
19811981 return false;
19981998 void IfConverter::PredicateBlock(BBInfo &BBI,
19991999 MachineBasicBlock::iterator E,
20002000 SmallVectorImpl &Cond,
2001 SmallSet<unsigned, 4> *LaterRedefs) {
2001 SmallSet<MCPhysReg, 4> *LaterRedefs) {
20022002 bool AnyUnpred = false;
20032003 bool MaySpec = LaterRedefs != nullptr;
20042004 for (MachineInstr &I : make_range(BBI.BB->begin(), E)) {
2828 /// The clobbers set will be the list of live registers clobbered
2929 /// by the regmask.
3030 void LivePhysRegs::removeRegsInMask(const MachineOperand &MO,
31 SmallVectorImpl> *Clobbers) {
32 SparseSet::iterator LRI = LiveRegs.begin();
31 SmallVectorImpl> *Clobbers) {
32 RegisterSet::iterator LRI = LiveRegs.begin();
3333 while (LRI != LiveRegs.end()) {
3434 if (MO.clobbersPhysReg(*LRI)) {
3535 if (Clobbers)
8282 /// on accurate kill flags. If possible use stepBackward() instead of this
8383 /// function.
8484 void LivePhysRegs::stepForward(const MachineInstr &MI,
85 SmallVectorImpl, const MachineOperand*>> &Clobbers) {
85 SmallVectorImpl, const MachineOperand*>> &Clobbers) {
8686 // Remove killed registers from the set.
8787 for (ConstMIBundleOperands O(MI); O.isValid(); ++O) {
8888 if (O->isReg() && !O->isDebug()) {
141141 #endif
142142
143143 bool LivePhysRegs::available(const MachineRegisterInfo &MRI,
144 unsigned Reg) const {
144 MCPhysReg Reg) const {
145145 if (LiveRegs.count(Reg))
146146 return false;
147147 if (MRI.isReserved(Reg))
156156 /// Add live-in registers of basic block \p MBB to \p LiveRegs.
157157 void LivePhysRegs::addBlockLiveIns(const MachineBasicBlock &MBB) {
158158 for (const auto &LI : MBB.liveins()) {
159 unsigned Reg = LI.PhysReg;
159 MCPhysReg Reg = LI.PhysReg;
160160 LaneBitmask Mask = LI.LaneMask;
161161 MCSubRegIndexIterator S(Reg, TRI);
162162 assert(Mask.any() && "Invalid livein mask");
17071707 // register that is entirely undefined.
17081708 LivePhysRegs LPR(HRI);
17091709 LPR.addLiveIns(B);
1710 SmallVectorunsigned, const MachineOperand*>,2> Clobbers;
1710 SmallVectorMCPhysReg, const MachineOperand*>,2> Clobbers;
17111711 for (auto R = B.begin(); R != It; ++R) {
17121712 Clobbers.clear();
17131713 LPR.stepForward(*R, Clobbers);
391391 // liveness state at the end of MBB (liveOut of MBB) as the liveIn for
392392 // NewSuccessor. Otherwise, will cause cyclic dependence.
393393 LivePhysRegs LPR(*MF->getSubtarget().getRegisterInfo());
394 SmallVectorunsigned, const MachineOperand *>, 2> Clobbers;
394 SmallVectorMCPhysReg, const MachineOperand *>, 2> Clobbers;
395395 for (MachineInstr &MI : *MBB)
396396 LPR.stepForward(MI, Clobbers);
397397 for (auto &LI : LPR)
25492549 // call. This way they still appear live across the call.
25502550 LivePhysRegs LiveRegs(getRegisterInfo());
25512551 LiveRegs.addLiveOuts(MBB);
2552 SmallVectorunsigned, const MachineOperand *>, 8> Clobbers;
2552 SmallVectorMCPhysReg, const MachineOperand *>, 8> Clobbers;
25532553 LiveRegs.stepForward(*MIB, Clobbers);
25542554 for (const auto &C : Clobbers) {
25552555 MIB.addReg(C.first, RegState::Implicit);