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[X86] Add a test for a 128-bit vector load feeding a cvtph2ps intrinsic. The instruction only loads 64-bits, but we should be able to fold a wider load and let it be narrowed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317546 91177308-0d34-0410-b5e6-96231b3b80d8 Craig Topper 3 years ago
1 changed file(s) with 26 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
2828 }
2929 declare <4 x float> @llvm.x86.vcvtph2ps.128(<8 x i16>) nounwind readonly
3030
31 define <4 x float> @test_x86_vcvtph2ps_128_m(<8 x i16>* nocapture %a) {
32 ; X32-LABEL: test_x86_vcvtph2ps_128_m:
33 ; X32: # BB#0:
34 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax # encoding: [0x8b,0x44,0x24,0x04]
35 ; X32-NEXT: vcvtph2ps (%eax), %xmm0 # encoding: [0xc4,0xe2,0x79,0x13,0x00]
36 ; X32-NEXT: retl # encoding: [0xc3]
37 ;
38 ; X64-LABEL: test_x86_vcvtph2ps_128_m:
39 ; X64: # BB#0:
40 ; X64-NEXT: vcvtph2ps (%rdi), %xmm0 # encoding: [0xc4,0xe2,0x79,0x13,0x07]
41 ; X64-NEXT: retq # encoding: [0xc3]
42 ;
43 ; X32-AVX512VL-LABEL: test_x86_vcvtph2ps_128_m:
44 ; X32-AVX512VL: # BB#0:
45 ; X32-AVX512VL-NEXT: movl {{[0-9]+}}(%esp), %eax # encoding: [0x8b,0x44,0x24,0x04]
46 ; X32-AVX512VL-NEXT: vcvtph2ps (%eax), %xmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x13,0x00]
47 ; X32-AVX512VL-NEXT: retl # encoding: [0xc3]
48 ;
49 ; X64-AVX512VL-LABEL: test_x86_vcvtph2ps_128_m:
50 ; X64-AVX512VL: # BB#0:
51 ; X64-AVX512VL-NEXT: vcvtph2ps (%rdi), %xmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x13,0x07]
52 ; X64-AVX512VL-NEXT: retq # encoding: [0xc3]
53 %load = load <8 x i16>, <8 x i16>* %a
54 %res = call <4 x float> @llvm.x86.vcvtph2ps.128(<8 x i16> %load) ; <<4 x float>> [#uses=1]
55 ret <4 x float> %res
56 }
3157
3258 define <8 x float> @test_x86_vcvtph2ps_256(<8 x i16> %a0) {
3359 ; X32-LABEL: test_x86_vcvtph2ps_256: