llvm.org GIT mirror llvm / 2718519
add floating point registers implement SINT_TO_FP git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30673 91177308-0d34-0410-b5e6-96231b3b80d8 Rafael Espindola 13 years ago
4 changed file(s) with 148 addition(s) and 24 deletion(s). Raw diff Collapse all Expand all
4444 ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
4545 : TargetLowering(TM) {
4646 addRegisterClass(MVT::i32, ARM::IntRegsRegisterClass);
47
48 //LLVM requires that a register class supports MVT::f64!
49 addRegisterClass(MVT::f64, ARM::IntRegsRegisterClass);
47 addRegisterClass(MVT::f32, ARM::FPRegsRegisterClass);
48 addRegisterClass(MVT::f64, ARM::DFPRegsRegisterClass);
49
50 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
5051
5152 setOperationAction(ISD::RET, MVT::Other, Custom);
5253 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
7879
7980 SELECT,
8081
81 BR
82 BR,
83
84 FSITOS
8285 };
8386 }
8487 }
110113 case ARMISD::SELECT: return "ARMISD::SELECT";
111114 case ARMISD::CMP: return "ARMISD::CMP";
112115 case ARMISD::BR: return "ARMISD::BR";
116 case ARMISD::FSITOS: return "ARMISD::FSITOS";
113117 }
114118 }
115119
240244 SDOperand LR = DAG.getRegister(ARM::R14, MVT::i32);
241245 return DAG.getNode(ARMISD::RET_FLAG, MVT::Other, Chain);
242246 }
243 case 3:
244 Copy = DAG.getCopyToReg(Chain, ARM::R0, Op.getOperand(1), SDOperand());
247 case 3: {
248 SDOperand Val = Op.getOperand(1);
249 assert(Val.getValueType() == MVT::i32 ||
250 Val.getValueType() == MVT::f32);
251
252 if (Val.getValueType() == MVT::f32)
253 Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Val);
254 Copy = DAG.getCopyToReg(Chain, ARM::R0, Val, SDOperand());
245255 if (DAG.getMachineFunction().liveout_empty())
246256 DAG.getMachineFunction().addLiveOut(ARM::R0);
247257 break;
258 }
248259 case 5:
249260 Copy = DAG.getCopyToReg(Chain, ARM::R1, Op.getOperand(3), SDOperand());
250261 Copy = DAG.getCopyToReg(Copy, ARM::R0, Op.getOperand(1), Copy.getValue(1));
408419 return DAG.getNode(ARMISD::BR, MVT::Other, Chain, Dest, ARMCC, Cmp);
409420 }
410421
422 static SDOperand LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
423 SDOperand IntVal = Op.getOperand(0);
424 assert(IntVal.getValueType() == MVT::i32);
425 assert(Op.getValueType() == MVT::f32);
426
427 SDOperand Tmp = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, IntVal);
428 return DAG.getNode(ARMISD::FSITOS, MVT::f32, Tmp);
429 }
430
411431 SDOperand ARMTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
412432 switch (Op.getOpcode()) {
413433 default:
417437 return LowerConstantPool(Op, DAG);
418438 case ISD::GlobalAddress:
419439 return LowerGlobalAddress(Op, DAG);
440 case ISD::SINT_TO_FP:
441 return LowerSINT_TO_FP(Op, DAG);
420442 case ISD::FORMAL_ARGUMENTS:
421443 return LowerFORMAL_ARGUMENTS(Op, DAG, VarArgsFrameIndex);
422444 case ISD::CALL:
7272
7373 def SDTVoidBinOp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
7474 def armcmp : SDNode<"ARMISD::CMP", SDTVoidBinOp, [SDNPOutFlag]>;
75
76 def armfsitos : SDNode<"ARMISD::FSITOS", SDTUnaryOp>;
7577
7678 def ADJCALLSTACKUP : InstARM<(ops i32imm:$amt),
7779 "!ADJCALLSTACKUP $amt",
149151 def cmp : InstARM<(ops IntRegs:$a, op_addr_mode1:$b),
150152 "cmp $a, $b",
151153 [(armcmp IntRegs:$a, addr_mode1:$b)]>;
154
155
156 // Floating Point Conversion
157 // We use bitconvert for moving the data between the register classes.
158 // The format conversion is done with ARM specific nodes
159
160 def FMSR : InstARM<(ops FPRegs:$dst, IntRegs:$src),
161 "fmsr $dst, $src", [(set FPRegs:$dst, (bitconvert IntRegs:$src))]>;
162
163 def FMRS : InstARM<(ops IntRegs:$dst, FPRegs:$src),
164 "fmrs $dst, $src", [(set IntRegs:$dst, (bitconvert FPRegs:$src))]>;
165
166 def FSITOS : InstARM<(ops FPRegs:$dst, FPRegs:$src),
167 "fsitos $dst, $src", [(set FPRegs:$dst, (armfsitos FPRegs:$src))]>;
1212 //===----------------------------------------------------------------------===//
1313
1414 // Registers are identified with 4-bit ID numbers.
15 class ARMReg num, string n> : Register {
16 field bits<4> Num;
15 class ARMReg : Register {
1716 let Namespace = "ARM";
1817 }
1918
19 // Ri - 32-bit integer registers
20 class Ri num, string n> : ARMReg {
21 field bits<4> Num;
22 let Num = num;
23 }
24 // Rf - 32-bit floating-point registers
25 class Rf num, string n> : ARMReg {
26 field bits<5> Num;
27 let Num = num;
28 }
29 // Rd - Slots in the FP register file for 64-bit floating-point values.
30 class Rd num, string n, list aliases> : ARMReg {
31 field bits<5> Num;
32 let Num = num;
33 let Aliases = aliases;
34 }
35
2036 // Integer registers
21 def R0 : ARMReg< 0, "R0">, DwarfRegNum<0>;
22 def R1 : ARMReg< 1, "R1">, DwarfRegNum<1>;
23 def R2 : ARMReg< 2, "R2">, DwarfRegNum<2>;
24 def R3 : ARMReg< 3, "R3">, DwarfRegNum<3>;
25 def R4 : ARMReg< 4, "R4">, DwarfRegNum<4>;
26 def R5 : ARMReg< 5, "R5">, DwarfRegNum<5>;
27 def R6 : ARMReg< 6, "R6">, DwarfRegNum<6>;
28 def R7 : ARMReg< 7, "R7">, DwarfRegNum<7>;
29 def R8 : ARMReg< 8, "R8">, DwarfRegNum<8>;
30 def R9 : ARMReg< 9, "R9">, DwarfRegNum<9>;
31 def R10 : ARMReg<10, "R10">, DwarfRegNum<10>;
32 def R11 : ARMReg<11, "R11">, DwarfRegNum<11>;
33 def R12 : ARMReg<12, "R12">, DwarfRegNum<12>;
34 def R13 : ARMReg<13, "R13">, DwarfRegNum<13>;
35 def R14 : ARMReg<14, "R14">, DwarfRegNum<14>;
36 def R15 : ARMReg<15, "R15">, DwarfRegNum<15>;
37 def R0 : Ri< 0, "R0">, DwarfRegNum<0>;
38 def R1 : Ri< 1, "R1">, DwarfRegNum<1>;
39 def R2 : Ri< 2, "R2">, DwarfRegNum<2>;
40 def R3 : Ri< 3, "R3">, DwarfRegNum<3>;
41 def R4 : Ri< 4, "R4">, DwarfRegNum<4>;
42 def R5 : Ri< 5, "R5">, DwarfRegNum<5>;
43 def R6 : Ri< 6, "R6">, DwarfRegNum<6>;
44 def R7 : Ri< 7, "R7">, DwarfRegNum<7>;
45 def R8 : Ri< 8, "R8">, DwarfRegNum<8>;
46 def R9 : Ri< 9, "R9">, DwarfRegNum<9>;
47 def R10 : Ri<10, "R10">, DwarfRegNum<10>;
48 def R11 : Ri<11, "R11">, DwarfRegNum<11>;
49 def R12 : Ri<12, "R12">, DwarfRegNum<12>;
50 def R13 : Ri<13, "R13">, DwarfRegNum<13>;
51 def R14 : Ri<14, "R14">, DwarfRegNum<14>;
52 def R15 : Ri<15, "R15">, DwarfRegNum<15>;
53
54 // TODO: update to VFP-v3
55 // Floating-point registers
56 def S0 : Rf< 0, "S0">, DwarfRegNum<64>;
57 def S1 : Rf< 1, "S1">, DwarfRegNum<65>;
58 def S2 : Rf< 2, "S2">, DwarfRegNum<66>;
59 def S3 : Rf< 3, "S3">, DwarfRegNum<67>;
60 def S4 : Rf< 4, "S4">, DwarfRegNum<68>;
61 def S5 : Rf< 5, "S5">, DwarfRegNum<69>;
62 def S6 : Rf< 6, "S6">, DwarfRegNum<70>;
63 def S7 : Rf< 7, "S7">, DwarfRegNum<71>;
64 def S8 : Rf< 8, "S8">, DwarfRegNum<72>;
65 def S9 : Rf< 9, "S9">, DwarfRegNum<73>;
66 def S10 : Rf<10, "S10">, DwarfRegNum<74>;
67 def S11 : Rf<11, "S11">, DwarfRegNum<75>;
68 def S12 : Rf<12, "S12">, DwarfRegNum<76>;
69 def S13 : Rf<13, "S13">, DwarfRegNum<77>;
70 def S14 : Rf<14, "S14">, DwarfRegNum<78>;
71 def S15 : Rf<15, "S15">, DwarfRegNum<79>;
72 def S16 : Rf<16, "S16">, DwarfRegNum<80>;
73 def S17 : Rf<17, "S17">, DwarfRegNum<81>;
74 def S18 : Rf<18, "S18">, DwarfRegNum<82>;
75 def S19 : Rf<19, "S19">, DwarfRegNum<83>;
76 def S20 : Rf<20, "S20">, DwarfRegNum<84>;
77 def S21 : Rf<21, "S21">, DwarfRegNum<85>;
78 def S22 : Rf<22, "S22">, DwarfRegNum<86>;
79 def S23 : Rf<23, "S23">, DwarfRegNum<87>;
80 def S24 : Rf<24, "S24">, DwarfRegNum<88>;
81 def S25 : Rf<25, "S25">, DwarfRegNum<89>;
82 def S26 : Rf<26, "S26">, DwarfRegNum<90>;
83 def S27 : Rf<27, "S27">, DwarfRegNum<91>;
84 def S28 : Rf<28, "S28">, DwarfRegNum<92>;
85 def S29 : Rf<29, "S29">, DwarfRegNum<93>;
86 def S30 : Rf<30, "S30">, DwarfRegNum<94>;
87 def S31 : Rf<31, "S31">, DwarfRegNum<95>;
88
89 // Aliases of the S* registers used to hold 64-bit fp values (doubles)
90 def D0 : Rd< 0, "S0", [S0, S1]>, DwarfRegNum<64>;
91 def D1 : Rd< 2, "S2", [S2, S3]>, DwarfRegNum<66>;
92 def D2 : Rd< 4, "S4", [S4, S5]>, DwarfRegNum<68>;
93 def D3 : Rd< 6, "S6", [S6, S7]>, DwarfRegNum<70>;
94 def D4 : Rd< 8, "S8", [S8, S9]>, DwarfRegNum<72>;
95 def D5 : Rd<10, "S10", [S10, S11]>, DwarfRegNum<74>;
96 def D6 : Rd<12, "S12", [S12, S13]>, DwarfRegNum<76>;
97 def D7 : Rd<14, "S14", [S14, S15]>, DwarfRegNum<78>;
98 def D8 : Rd<16, "S16", [S16, S17]>, DwarfRegNum<80>;
99 def D9 : Rd<18, "S18", [S18, S19]>, DwarfRegNum<82>;
100 def D10 : Rd<20, "S20", [S20, S21]>, DwarfRegNum<84>;
101 def D11 : Rd<22, "S22", [S22, S23]>, DwarfRegNum<86>;
102 def D12 : Rd<24, "S24", [S24, S25]>, DwarfRegNum<88>;
103 def D13 : Rd<26, "S26", [S26, S27]>, DwarfRegNum<90>;
104 def D14 : Rd<28, "S28", [S28, S29]>, DwarfRegNum<92>;
105 def D15 : Rd<30, "S30", [S30, S31]>, DwarfRegNum<94>;
37106
38107 // Register classes.
39108 //
59128 }
60129 }];
61130 }
131
132 def FPRegs : RegisterClass<"ARM", [f32], 32, [S0, S1, S2, S3, S4, S5, S6, S7, S8,
133 S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22,
134 S23, S24, S25, S26, S27, S28, S29, S30, S31]>;
135
136 def DFPRegs : RegisterClass<"ARM", [f64], 64, [D0, D1, D2, D3, D4, D5, D6, D7,
137 D8, D9, D10, D11, D12, D13, D14, D15]>;
0 ; RUN: llvm-as < %s | llc -march=arm &&
1 ; RUN: llvm-as < %s | llc -march=arm | grep fmsr &&
2 ; RUN: llvm-as < %s | llc -march=arm | grep fsitos &&
3 ; RUN: llvm-as < %s | llc -march=arm | grep fmrs
4
5 float %f(int %a) {
6 entry:
7 %tmp = cast int %a to float ; [#uses=1]
8 ret float %tmp
9 }