llvm.org GIT mirror llvm / 26db53e
TableGen: Streamline the semantics of NAME Summary: The new rules are straightforward. The main rules to keep in mind are: 1. NAME is an implicit template argument of class and multiclass, and will be substituted by the name of the instantiating def/defm. 2. The name of a def/defm in a multiclass must contain a reference to NAME. If such a reference is not present, it is automatically prepended. And for some additional subtleties, consider these: 3. defm with no name generates a unique name but has no special behavior otherwise. 4. def with no name generates an anonymous record, whose name is unique but undefined. In particular, the name won't contain a reference to NAME. Keeping rules 1&2 in mind should allow a predictable behavior of name resolution that is simple to follow. The old "rules" were rather surprising: sometimes (but not always), NAME would correspond to the name of the toplevel defm. They were also plain bonkers when you pushed them to their limits, as the old version of the TableGen test case shows. Having NAME correspond to the name of the toplevel defm introduces "spooky action at a distance" and breaks composability: refactoring the upper layers of a hierarchy of nested multiclass instantiations can cause unexpected breakage by changing the value of NAME at a lower level of the hierarchy. The new rules don't suffer from this problem. Some existing .td files have to be adjusted because they ended up depending on the details of the old implementation. Change-Id: I694095231565b30f563e6fd0417b41ee01a12589 Reviewers: tra, simon_tatham, craig.topper, MartinO, arsenm, javed.absar Subscribers: wdng, llvm-commits Differential Revision: https://reviews.llvm.org/D47430 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333900 91177308-0d34-0410-b5e6-96231b3b80d8 Nicolai Haehnle 1 year, 4 months ago
16 changed file(s) with 569 addition(s) and 563 deletion(s). Raw diff Collapse all Expand all
124124
125125 .. productionlist::
126126 Class: "class" `TokIdentifier` [`TemplateArgList`] `ObjectBody`
127 TemplateArgList: "<" `Declaration` ("," `Declaration`)* ">"
127128
128129 A ``class`` declaration creates a record which other records can inherit
129130 from. A class can be parametrized by a list of "template arguments", whose
144145 class will inherit no fields from it since the record expansion is done
145146 when the record is parsed.
146147
147 .. productionlist::
148 TemplateArgList: "<" `Declaration` ("," `Declaration`)* ">"
148 Every class has an implicit template argument called ``NAME``, which is set
149 to the name of the instantiating ``def`` or ``defm``. The result is undefined
150 if the class is instantiated by an anonymous record.
149151
150152 Declarations
151153 ------------
245247 int Baz = Bar;
246248 }
247249
250 * the implicit template argument ``NAME`` in a ``class`` or ``multiclass``
251
248252 .. productionlist::
249253 SimpleValue: `TokInteger`
250254
331335 ``def``
332336 -------
333337
334 .. TODO::
335 There can be pastes in the names here, like ``#NAME#``. Look into that
336 and document it (it boils down to ParseIDValue with IDParseMode ==
337 ParseNameMode). ParseObjectName calls into the general ParseValue, with
338 the only different from "arbitrary expression parsing" being IDParseMode
339 == Mode.
340
341 .. productionlist::
342 Def: "def" `TokIdentifier` `ObjectBody`
343
344 Defines a record whose name is given by the :token:`TokIdentifier`. The
345 fields of the record are inherited from the base classes and defined in the
346 body.
338 .. productionlist::
339 Def: "def" [`Value`] `ObjectBody`
340
341 Defines a record whose name is given by the optional :token:`Value`. The value
342 is parsed in a special mode where global identifiers (records and variables
343 defined by ``defset``) are not recognized, and all unrecognized identifiers
344 are interpreted as strings.
345
346 If no name is given, the record is anonymous. The final name of anonymous
347 records is undefined, but globally unique.
347348
348349 Special handling occurs if this ``def`` appears inside a ``multiclass`` or
349350 a ``foreach``.
350351
352 When a non-anonymous record is defined in a multiclass and the given name
353 does not contain a reference to the implicit template argument ``NAME``, such
354 a reference will automatically be prepended. That is, the following are
355 equivalent inside a multiclass::
356
357 def Foo;
358 def NAME#Foo;
359
351360 ``defm``
352361 --------
353362
354363 .. productionlist::
355 Defm: "defm" [`TokIdentifier`] ":" `BaseClassListNE` ";"
356
357 Note that in the :token:`BaseClassList`, all of the ``multiclass``'s must
358 precede any ``class``'s that appear.
364 Defm: "defm" [`Value`] ":" `BaseClassListNE` ";"
365
366 The :token:`BaseClassList` is a list of at least one ``multiclass`` and any
367 number of ``class``'s. The ``multiclass``'s must occur before any ``class``'s.
368
369 Instantiates all records defined in all given ``multiclass``'s and adds the
370 given ``class``'s as superclasses.
371
372 The name is parsed in the same special mode used by ``def``. If the name is
373 missing, a globally unique string is used instead (but instantiated records
374 are not considered to be anonymous, unless they were originally defined by an
375 anonymous ``def``) That is, the following have different semantics::
376
377 defm : SomeMultiClass<...>; // some globally unique name
378 defm "" : SomeMultiClass<...>; // empty name string
379
380 When it occurs inside a multiclass, the second variant is equivalent to
381 ``defm NAME : ...``. More generally, when ``defm`` occurs in a multiclass and
382 its name does not contain a reference to the implicit template argument
383 ``NAME``, such a reference will automatically be prepended. That is, the
384 following are equivalent inside a multiclass::
385
386 defm Foo : SomeMultiClass<...>;
387 defm NAME#Foo : SomeMultiClass<...>;
359388
360389 ``defset``
361390 ----------
170170 feature of TableGen is that it allows the end-user to define the abstractions
171171 they prefer to use when describing their information.
172172
173 Each ``def`` record has a special entry called "NAME". This is the name of the
174 record ("``ADD32rr``" above). In the general case ``def`` names can be formed
175 from various kinds of string processing expressions and ``NAME`` resolves to the
176 final value obtained after resolving all of those expressions. The user may
177 refer to ``NAME`` anywhere she desires to use the ultimate name of the ``def``.
178 ``NAME`` should not be defined anywhere else in user code to avoid conflicts.
179
180173 Syntax
181174 ======
182175
13561356 unsigned ID;
13571357
13581358 bool IsAnonymous;
1359
1360 void init();
1359 bool IsClass;
1360
13611361 void checkName();
13621362
13631363 public:
13641364 // Constructs a record.
13651365 explicit Record(Init *N, ArrayRef locs, RecordKeeper &records,
1366 bool Anonymous = false) :
1367 Name(N), Locs(locs.begin(), locs.end()), TrackedRecords(records),
1368 ID(LastID++), IsAnonymous(Anonymous) {
1369 init();
1370 }
1371
1372 explicit Record(StringRef N, ArrayRef locs, RecordKeeper &records)
1373 : Record(StringInit::get(N), locs, records) {}
1366 bool Anonymous = false, bool Class = false)
1367 : Name(N), Locs(locs.begin(), locs.end()), TrackedRecords(records),
1368 ID(LastID++), IsAnonymous(Anonymous), IsClass(Class) {
1369 checkName();
1370 }
1371
1372 explicit Record(StringRef N, ArrayRef locs, RecordKeeper &records,
1373 bool Class = false)
1374 : Record(StringInit::get(N), locs, records, false, Class) {}
13741375
13751376 // When copy-constructing a Record, we must still guarantee a globally unique
13761377 // ID number. Don't copy TheInit either since it's owned by the original
13771378 // record. All other fields can be copied normally.
1378 Record(const Record &O) :
1379 Name(O.Name), Locs(O.Locs), TemplateArgs(O.TemplateArgs),
1380 Values(O.Values), SuperClasses(O.SuperClasses),
1381 TrackedRecords(O.TrackedRecords), ID(LastID++),
1382 IsAnonymous(O.IsAnonymous) { }
1379 Record(const Record &O)
1380 : Name(O.Name), Locs(O.Locs), TemplateArgs(O.TemplateArgs),
1381 Values(O.Values), SuperClasses(O.SuperClasses),
1382 TrackedRecords(O.TrackedRecords), ID(LastID++),
1383 IsAnonymous(O.IsAnonymous), IsClass(O.IsClass) { }
13831384
13841385 static unsigned getNewUID() { return LastID++; }
13851386
14051406
14061407 /// get the corresponding DefInit.
14071408 DefInit *getDefInit();
1409
1410 bool isClass() const { return IsClass; }
14081411
14091412 ArrayRef getTemplateArgs() const {
14101413 return TemplateArgs;
14511454 void addValue(const RecordVal &RV) {
14521455 assert(getValue(RV.getNameInit()) == nullptr && "Value already added!");
14531456 Values.push_back(RV);
1454 if (Values.size() > 1)
1455 // Keep NAME at the end of the list. It makes record dumps a
1456 // bit prettier and allows TableGen tests to be written more
1457 // naturally. Tests can use CHECK-NEXT to look for Record
1458 // fields they expect to see after a def. They can't do that if
1459 // NAME is the first Record field.
1460 std::swap(Values[Values.size() - 2], Values[Values.size() - 1]);
14611457 }
14621458
14631459 void removeValue(Init *Name) {
19041900 Init *resolve(Init *VarName) override;
19051901 };
19061902
1903 /// Do not resolve anything, but keep track of whether a given variable was
1904 /// referenced.
1905 class HasReferenceResolver final : public Resolver {
1906 Init *VarNameToTrack;
1907 bool Found = false;
1908
1909 public:
1910 explicit HasReferenceResolver(Init *VarNameToTrack)
1911 : Resolver(nullptr), VarNameToTrack(VarNameToTrack) {}
1912
1913 bool found() const { return Found; }
1914
1915 Init *resolve(Init *VarName) override;
1916 };
1917
19071918 } // end namespace llvm
19081919
19091920 #endif // LLVM_TABLEGEN_RECORD_H
15711571 Record *NewRec = NewRecOwner.get();
15721572
15731573 // Copy values from class to instance
1574 for (const RecordVal &Val : Class->getValues()) {
1575 if (Val.getName() != "NAME")
1576 NewRec->addValue(Val);
1577 }
1574 for (const RecordVal &Val : Class->getValues())
1575 NewRec->addValue(Val);
15781576
15791577 // Substitute and resolve template arguments
15801578 ArrayRef TArgs = Class->getTemplateArgs();
18431841 }
18441842
18451843 unsigned Record::LastID = 0;
1846
1847 void Record::init() {
1848 checkName();
1849
1850 // Every record potentially has a def at the top. This value is
1851 // replaced with the top-level def name at instantiation time.
1852 addValue(RecordVal(StringInit::get("NAME"), StringRecTy::get(), false));
1853 }
18541844
18551845 void Record::checkName() {
18561846 // Ensure the record name has string type.
22592249 FoundUnresolved = true;
22602250 return I;
22612251 }
2252
2253 Init *HasReferenceResolver::resolve(Init *VarName)
2254 {
2255 if (VarName == VarNameToTrack)
2256 Found = true;
2257 return nullptr;
2258 }
109109 }
110110 }
111111
112 /// Return the qualified version of the implicit 'NAME' template argument.
113 static Init *QualifiedNameOfImplicitName(Record &Rec,
114 MultiClass *MC = nullptr) {
115 return QualifyName(Rec, MC, StringInit::get("NAME"), MC ? "::" : ":");
116 }
117
118 static Init *QualifiedNameOfImplicitName(MultiClass *MC) {
119 return QualifiedNameOfImplicitName(MC->Rec, MC);
120 }
121
112122 bool TGParser::AddValue(Record *CurRec, SMLoc Loc, const RecordVal &RV) {
113123 if (!CurRec)
114124 CurRec = &CurMultiClass->Rec;
233243 CurRec->removeValue(TArgs[i]);
234244 }
235245
246 Init *Name;
247 if (CurRec->isClass())
248 Name =
249 VarInit::get(QualifiedNameOfImplicitName(*CurRec), StringRecTy::get());
250 else
251 Name = CurRec->getNameInit();
252 R.set(QualifiedNameOfImplicitName(*SC), Name);
253
236254 CurRec->resolveReferences(R);
237255
238256 // Since everything went well, we can now set the "superclass" list for the
258276 bool TGParser::AddSubMultiClass(MultiClass *CurMC,
259277 SubMultiClassReference &SubMultiClass) {
260278 MultiClass *SMC = SubMultiClass.MC;
261 Record *CurRec = &CurMC->Rec;
262
263 // Add all of the values in the subclass into the current class.
264 for (const auto &SMCVal : SMC->Rec.getValues())
265 if (AddValue(CurRec, SubMultiClass.RefRange.Start, SMCVal))
266 return true;
267
268 unsigned newDefStart = CurMC->DefPrototypes.size();
269
270 // Add all of the defs in the subclass into the current multiclass.
271 for (const std::unique_ptr &R : SMC->DefPrototypes) {
272 // Clone the def and add it to the current multiclass
273 auto NewDef = make_unique(*R);
274
275 // Add all of the values in the superclass into the current def.
276 for (const auto &MCVal : CurRec->getValues())
277 if (AddValue(NewDef.get(), SubMultiClass.RefRange.Start, MCVal))
278 return true;
279
280 CurMC->DefPrototypes.push_back(std::move(NewDef));
281 }
282279
283280 ArrayRef SMCTArgs = SMC->Rec.getTemplateArgs();
284
285 // Ensure that an appropriate number of template arguments are
286 // specified.
287281 if (SMCTArgs.size() < SubMultiClass.TemplateArgs.size())
288282 return Error(SubMultiClass.RefRange.Start,
289283 "More template args specified than expected");
290284
291 // Loop over all of the template arguments, setting them to the specified
292 // value or leaving them as the default if necessary.
293 MapResolver CurRecResolver(CurRec);
294
285 // Prepare the mapping of template argument name to value, filling in default
286 // values if necessary.
287 SmallVector, 8> TemplateArgs;
295288 for (unsigned i = 0, e = SMCTArgs.size(); i != e; ++i) {
296289 if (i < SubMultiClass.TemplateArgs.size()) {
297 // If a value is specified for this template arg, set it in the
298 // superclass now.
299 if (SetValue(CurRec, SubMultiClass.RefRange.Start, SMCTArgs[i],
300 None, SubMultiClass.TemplateArgs[i]))
301 return true;
302
303 // If a value is specified for this template arg, set it in the
304 // new defs now.
305 for (const auto &Def :
306 makeArrayRef(CurMC->DefPrototypes).slice(newDefStart)) {
307 if (SetValue(Def.get(), SubMultiClass.RefRange.Start, SMCTArgs[i],
308 None, SubMultiClass.TemplateArgs[i]))
309 return true;
310 }
311 } else if (!CurRec->getValue(SMCTArgs[i])->getValue()->isComplete()) {
312 return Error(SubMultiClass.RefRange.Start,
313 "Value not specified for template argument #" +
314 Twine(i) + " (" + SMCTArgs[i]->getAsUnquotedString() +
315 ") of subclass '" + SMC->Rec.getNameInitAsString() + "'!");
316 }
317
318 CurRecResolver.set(SMCTArgs[i], CurRec->getValue(SMCTArgs[i])->getValue());
319
320 CurRec->removeValue(SMCTArgs[i]);
321 }
322
323 CurRec->resolveReferences(CurRecResolver);
324
325 for (const auto &Def :
326 makeArrayRef(CurMC->DefPrototypes).slice(newDefStart)) {
327 MapResolver R(Def.get());
328
329 for (Init *SMCTArg : SMCTArgs) {
330 R.set(SMCTArg, Def->getValue(SMCTArg)->getValue());
331 Def->removeValue(SMCTArg);
332 }
333
334 Def->resolveReferences(R);
290 TemplateArgs.emplace_back(SMCTArgs[i], SubMultiClass.TemplateArgs[i]);
291 } else {
292 Init *Default = SMC->Rec.getValue(SMCTArgs[i])->getValue();
293 if (!Default->isComplete()) {
294 return Error(SubMultiClass.RefRange.Start,
295 "value not specified for template argument #" + Twine(i) +
296 " (" + SMCTArgs[i]->getAsUnquotedString() +
297 ") of multiclass '" + SMC->Rec.getNameInitAsString() +
298 "'");
299 }
300 TemplateArgs.emplace_back(SMCTArgs[i], Default);
301 }
302 }
303
304 TemplateArgs.emplace_back(
305 QualifiedNameOfImplicitName(SMC),
306 VarInit::get(QualifiedNameOfImplicitName(CurMC), StringRecTy::get()));
307
308 // Add all of the defs in the subclass into the current multiclass.
309 for (const std::unique_ptr &Rec : SMC->DefPrototypes) {
310 auto NewDef = make_unique(*Rec);
311
312 MapResolver R(NewDef.get());
313 for (const auto &TArg : TemplateArgs)
314 R.set(TArg.first, TArg.second);
315 NewDef->resolveReferences(R);
316
317 CurMC->DefPrototypes.push_back(std::move(NewDef));
335318 }
336319
337320 return false;
342325 ///
343326 /// Apply foreach loops, resolve internal variable references, and add to the
344327 /// current multi class or the global record keeper as appropriate.
345 bool TGParser::addDef(std::unique_ptr Rec, Init *DefmName) {
328 bool TGParser::addDef(std::unique_ptr Rec) {
346329 IterSet IterVals;
347330
348331 if (Loops.empty())
349 return addDefOne(std::move(Rec), DefmName, IterVals);
350
351 return addDefForeach(Rec.get(), DefmName, IterVals);
332 return addDefOne(std::move(Rec), IterVals);
333
334 return addDefForeach(Rec.get(), IterVals);
352335 }
353336
354337 /// Recursive helper function for addDef/addDefOne to resolve references to
355338 /// foreach variables.
356 bool TGParser::addDefForeach(Record *Rec, Init *DefmName, IterSet &IterVals) {
339 bool TGParser::addDefForeach(Record *Rec, IterSet &IterVals) {
357340 if (IterVals.size() != Loops.size()) {
358341 assert(IterVals.size() < Loops.size());
359342 ForeachLoop &CurLoop = Loops[IterVals.size()];
362345 // Process each value.
363346 for (unsigned i = 0; i < List->size(); ++i) {
364347 IterVals.push_back(IterRecord(CurLoop.IterVar, List->getElement(i)));
365 if (addDefForeach(Rec, DefmName, IterVals))
348 if (addDefForeach(Rec, IterVals))
366349 return true;
367350 IterVals.pop_back();
368351 }
373356 // for this point in the iteration space. Instantiate a new record to
374357 // reflect this combination of values.
375358 auto IterRec = make_unique(*Rec);
376 return addDefOne(std::move(IterRec), DefmName, IterVals);
359 return addDefOne(std::move(IterRec), IterVals);
377360 }
378361
379362 /// After resolving foreach loops, add the record as a prototype to the
380363 /// current multiclass, or resolve fully and add to the record keeper.
381 bool TGParser::addDefOne(std::unique_ptr Rec, Init *DefmName,
382 IterSet &IterVals) {
364 bool TGParser::addDefOne(std::unique_ptr Rec, IterSet &IterVals) {
383365 MapResolver R(Rec.get());
384366
385367 for (IterRecord &IR : IterVals)
388370 Rec->resolveReferences(R);
389371
390372 if (CurMultiClass) {
391 for (const auto &Proto : CurMultiClass->DefPrototypes) {
392 if (Proto->getNameInit() == Rec->getNameInit()) {
393 if (!Rec->isAnonymous()) {
373 if (!Rec->isAnonymous()) {
374 for (const auto &Proto : CurMultiClass->DefPrototypes) {
375 if (Proto->getNameInit() == Rec->getNameInit()) {
394376 PrintError(Rec->getLoc(),
395377 Twine("def '") + Rec->getNameInitAsString() +
396378 "' already defined in this multiclass!");
397379 PrintNote(Proto->getLoc(), "location of previous definition");
398380 return true;
399381 }
400 Rec->setName(Records.getNewAnonymousName());
401 break;
402382 }
403383 }
404384 CurMultiClass->DefPrototypes.emplace_back(std::move(Rec));
405385 return false;
406 }
407
408 // Name construction is an incoherent mess. Unfortunately, existing .td
409 // files rely on pretty much all the quirks and implementation details of
410 // this.
411 if (DefmName) {
412 MapResolver R(Rec.get());
413 R.set(StringInit::get("NAME"), DefmName);
414 Rec->resolveReferences(R);
415386 }
416387
417388 if (Record *Prev = Records.getDef(Rec->getNameInitAsString())) {
487458 if (CurMultiClass)
488459 CurRec = &CurMultiClass->Rec;
489460
490 return ParseValue(CurRec, StringRecTy::get(), ParseNameMode);
461 Init *Name = ParseValue(CurRec, StringRecTy::get(), ParseNameMode);
462 if (!Name)
463 return nullptr;
464
465 if (CurMultiClass) {
466 Init *NameStr = QualifiedNameOfImplicitName(CurMultiClass);
467 HasReferenceResolver R(NameStr);
468 Name->resolveReferences(R);
469 if (!R.found())
470 Name = BinOpInit::getStrConcat(VarInit::get(NameStr, StringRecTy::get()),
471 Name);
472 }
473
474 return Name;
491475 }
492476
493477 /// ParseClassID - Parse and resolve a reference to a class name. This returns
797781 if (CurRec) {
798782 if (const RecordVal *RV = CurRec->getValue(Name))
799783 return VarInit::get(Name, RV->getType());
800
801 Init *TemplateArgName = QualifyName(*CurRec, CurMultiClass, Name, ":");
802
803 if (CurMultiClass)
804 TemplateArgName = QualifyName(CurMultiClass->Rec, CurMultiClass, Name,
805 "::");
806
807 if (CurRec->isTemplateArg(TemplateArgName)) {
808 const RecordVal *RV = CurRec->getValue(TemplateArgName);
784 }
785
786 if ((CurRec && CurRec->isClass()) || CurMultiClass) {
787 Init *TemplateArgName;
788 if (CurMultiClass) {
789 TemplateArgName =
790 QualifyName(CurMultiClass->Rec, CurMultiClass, Name, "::");
791 } else
792 TemplateArgName = QualifyName(*CurRec, CurMultiClass, Name, ":");
793
794 Record *TemplateRec = CurMultiClass ? &CurMultiClass->Rec : CurRec;
795 if (TemplateRec->isTemplateArg(TemplateArgName)) {
796 const RecordVal *RV = TemplateRec->getValue(TemplateArgName);
809797 assert(RV && "Template arg doesn't exist??");
810798 return VarInit::get(TemplateArgName, RV->getType());
811 }
812 }
813
814 if (CurMultiClass) {
815 if (Name->getValue() == "NAME")
816 return VarInit::get(Name, StringRecTy::get());
817
818 Init *MCName = QualifyName(CurMultiClass->Rec, CurMultiClass, Name, "::");
819
820 if (CurMultiClass->Rec.isTemplateArg(MCName)) {
821 const RecordVal *RV = CurMultiClass->Rec.getValue(MCName);
822 assert(RV && "Template arg doesn't exist??");
823 return VarInit::get(MCName, RV->getType());
799 } else if (Name->getValue() == "NAME") {
800 return VarInit::get(TemplateArgName, StringRecTy::get());
824801 }
825802 }
826803
839816
840817 // Allow self-references of concrete defs, but delay the lookup so that we
841818 // get the correct type.
842 if (CurRec && !CurMultiClass && CurRec->getNameInit() == Name)
819 if (CurRec && !CurRec->isClass() && !CurMultiClass &&
820 CurRec->getNameInit() == Name)
843821 return UnOpInit::get(UnOpInit::CAST, Name, CurRec->getType());
844822
845 if (Mode == ParseValueMode) {
846 Error(NameLoc, "Variable not defined: '" + Name->getValue() + "'");
847 return nullptr;
848 }
849
850 return Name;
823 Error(NameLoc, "Variable not defined: '" + Name->getValue() + "'");
824 return nullptr;
851825 }
852826
853827 /// ParseOperation - Parse an operator. This returns null on error.
21682142 return nullptr;
21692143 }
21702144
2145 std::string Str = Lex.getCurStrVal();
2146 if (Str == "NAME") {
2147 TokError("'" + Str + "' is a reserved variable name");
2148 return nullptr;
2149 }
2150
21712151 SMLoc IdLoc = Lex.getLoc();
2172 Init *DeclName = StringInit::get(Lex.getCurStrVal());
2152 Init *DeclName = StringInit::get(Str);
21732153 Lex.Lex();
21742154
21752155 if (ParsingTemplateArgs) {
24702450 if (ParseObjectBody(CurRec.get()))
24712451 return true;
24722452
2473 return addDef(std::move(CurRec), nullptr);
2453 return addDef(std::move(CurRec));
24742454 }
24752455
24762456 /// ParseDefset - Parse a defset statement.
25842564 Record *CurRec = Records.getClass(Lex.getCurStrVal());
25852565 if (CurRec) {
25862566 // If the body was previously defined, this is an error.
2587 if (CurRec->getValues().size() > 1 || // Account for NAME.
2567 if (!CurRec->getValues().empty() ||
25882568 !CurRec->getSuperClasses().empty() ||
25892569 !CurRec->getTemplateArgs().empty())
25902570 return TokError("Class '" + CurRec->getNameInitAsString() +
25922572 } else {
25932573 // If this is the first reference to this class, create and add it.
25942574 auto NewRec =
2595 llvm::make_unique(Lex.getCurStrVal(), Lex.getLoc(), Records);
2575 llvm::make_unique(Lex.getCurStrVal(), Lex.getLoc(), Records,
2576 /*Class=*/true);
25962577 CurRec = NewRec.get();
25972578 Records.addClass(std::move(NewRec));
25982579 }
26032584 if (ParseTemplateArgList(CurRec))
26042585 return true;
26052586
2606 // Finally, parse the object body.
26072587 return ParseObjectBody(CurRec);
26082588 }
26092589
28012781 Init *DefmName = ParseObjectName(CurMultiClass);
28022782 if (!DefmName)
28032783 return true;
2804 if (isa(DefmName))
2784 if (isa(DefmName)) {
28052785 DefmName = Records.getNewAnonymousName();
2786 if (CurMultiClass)
2787 DefmName = BinOpInit::getStrConcat(
2788 VarInit::get(QualifiedNameOfImplicitName(CurMultiClass),
2789 StringRecTy::get()),
2790 DefmName);
2791 }
28062792
28072793 if (Lex.getCode() != tgtok::colon)
28082794 return TokError("expected ':' after defm identifier");
28352821 return Error(SubClassLoc,
28362822 "more template args specified than multiclass expects");
28372823
2838 DenseMap> TemplateArgs;
2824 SmallVector, 8> TemplateArgs;
28392825 for (unsigned i = 0, e = TArgs.size(); i != e; ++i) {
28402826 if (i < TemplateVals.size()) {
2841 TemplateArgs.insert({TArgs[i], TemplateVals[i]});
2827 TemplateArgs.emplace_back(TArgs[i], TemplateVals[i]);
28422828 } else {
28432829 Init *Default = MC->Rec.getValue(TArgs[i])->getValue();
28442830 if (!Default->isComplete()) {
28482834 ") of multiclass '" + MC->Rec.getNameInitAsString() +
28492835 "'");
28502836 }
2851 TemplateArgs.insert({TArgs[i], Default});
2852 }
2853 }
2837 TemplateArgs.emplace_back(TArgs[i], Default);
2838 }
2839 }
2840
2841 TemplateArgs.emplace_back(QualifiedNameOfImplicitName(MC), DefmName);
28542842
28552843 // Loop over all the def's in the multiclass, instantiating each one.
28562844 for (const std::unique_ptr &DefProto : MC->DefPrototypes) {
2857 bool ResolveName = true;
28582845 auto CurRec = make_unique(*DefProto);
28592846 CurRec->appendLoc(SubClassLoc);
28602847
2861 if (StringInit *NameString =
2862 dyn_cast(CurRec->getNameInit())) {
2863 // We have a fully expanded string so there are no operators to
2864 // resolve. We should concatenate the given prefix and name.
2865 //
2866 // TODO: This MUST happen before template argument resolution. This
2867 // does not make sense and should be changed, but at the time of
2868 // writing, there are existing .td files which rely on this
2869 // implementation detail. It's a bad idea and should be fixed.
2870 // See test/TableGen/name-resolution-consistency.td for some
2871 // examples.
2872 CurRec->setName(BinOpInit::getStrConcat(DefmName, NameString));
2873 ResolveName = false;
2874 }
2875
28762848 MapResolver R(CurRec.get());
2877
2878 if (ResolveName) {
2879 // If the proto's name wasn't resolved, we probably have a reference to
2880 // NAME and need to replace it.
2881 //
2882 // TODO: Whether the name is resolved is basically determined by magic.
2883 // Unfortunately, existing .td files depend on it.
2884 R.set(StringInit::get("NAME"), DefmName);
2885 }
2886
28872849 for (const auto &TArg : TemplateArgs)
28882850 R.set(TArg.first, TArg.second);
2889
28902851 CurRec->resolveReferences(R);
28912852
28922853 NewRecDefs.emplace_back(std::move(CurRec));
29362897 if (ApplyLetStack(CurRec.get()))
29372898 return true;
29382899
2939 addDef(std::move(CurRec), DefmName);
2900 addDef(std::move(CurRec));
29402901 }
29412902
29422903 if (Lex.getCode() != tgtok::semi)
125125 // iteration space.
126126 typedef std::vector IterSet;
127127
128 bool addDefOne(std::unique_ptr Rec, Init *DefmName,
129 IterSet &IterVals);
130 bool addDefForeach(Record *Rec, Init *DefmName, IterSet &IterVals);
131 bool addDef(std::unique_ptr Rec, Init *DefmName);
128 bool addDefOne(std::unique_ptr Rec, IterSet &IterVals);
129 bool addDefForeach(Record *Rec, IterSet &IterVals);
130 bool addDef(std::unique_ptr Rec);
132131
133132 private: // Parser methods.
134133 bool ParseObjectList(MultiClass *MC = nullptr);
86548654
86558655 // The immediate form of AdvSIMD post-indexed addressing is encoded with
86568656 // register post-index addressing from the zero register.
8657 multiclass SIMDLdStAliasesasm, string layout, string Count,
8657 multiclass SIMDLdStAliasesBaseName, string asm, string layout, string Count,
86588658 int Offset, int Size> {
86598659 // E.g. "ld1 { v0.8b, v1.8b }, [x1], #16"
86608660 // "ld1\t$Vt, [$Rn], #16"
86618661 // may get mapped to
86628662 // (LD1Twov8b_POST VecListTwo8b:$Vt, GPR64sp:$Rn, XZR)
86638663 def : InstAlias
8664 (!cast(NAME # Count # "v" # layout # "_POST")
8664 (!cast(BaseName # Count # "v" # layout # "_POST")
86658665 GPR64sp:$Rn,
86668666 !cast("VecList" # Count # layout):$Vt,
86678667 XZR), 1>;
86718671 // may get mapped to
86728672 // (LD1Twov8b_POST VecListTwo64:$Vt, GPR64sp:$Rn, XZR)
86738673 def : InstAlias
8674 (!cast(NAME # Count # "v" # layout # "_POST")
8674 (!cast(BaseName # Count # "v" # layout # "_POST")
86758675 GPR64sp:$Rn,
86768676 !cast("VecList" # Count # Size):$Vt,
86778677 XZR), 0>;
86818681 // may get mapped to
86828682 // (LD1Twov8b VecListTwo64:$Vt, GPR64sp:$Rn)
86838683 def : InstAlias
8684 (!cast(NAME # Count # "v" # layout)
8684 (!cast(BaseName # Count # "v" # layout)
86858685 !cast("VecList" # Count # Size):$Vt,
86868686 GPR64sp:$Rn), 0>;
86878687
86908690 // may get mapped to
86918691 // (LD1Twov8b_POST VecListTwo64:$Vt, GPR64sp:$Rn, GPR64pi8:$Xm)
86928692 def : InstAlias
8693 (!cast(NAME # Count # "v" # layout # "_POST")
8693 (!cast(BaseName # Count # "v" # layout # "_POST")
86948694 GPR64sp:$Rn,
86958695 !cast("VecList" # Count # Size):$Vt,
86968696 !cast("GPR64pi" # Offset):$Xm), 0>;
86978697 }
86988698
8699 multiclass BaseSIMDLdN
8700 int Offset64, bits<4> opcode> {
8699 multiclass BaseSIMDLdN
8700 int Offset128, int Offset64, bits<4> opcode> {
87018701 let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
87028702 def v16b: BaseSIMDLdSt<1, 1, opcode, 0b00, asm,
87038703 (outs !cast(veclist # "16b"):$Vt),
87598759 !cast("GPR64pi" # Offset64):$Xm)>;
87608760 }
87618761
8762 defm : SIMDLdStAliases;
8763 defm : SIMDLdStAliases;
8764 defm : SIMDLdStAliases;
8765 defm : SIMDLdStAliases;
8766 defm : SIMDLdStAliases;
8767 defm : SIMDLdStAliases;
8768 defm : SIMDLdStAliases<asm, "2s", Count, Offset64, 64>;
8762 defm : SIMDLdStAliases<BaseName, asm, "16b", Count, Offset128, 128>;
8763 defm : SIMDLdStAliases;
8764 defm : SIMDLdStAliases;
8765 defm : SIMDLdStAliases;
8766 defm : SIMDLdStAliases;
8767 defm : SIMDLdStAliases;
8768 defm : SIMDLdStAliases;
87698769 }
87708770
87718771 // Only ld1/st1 has a v1d version.
8772 multiclass BaseSIMDStN
8773 int Offset64, bits<4> opcode> {
8772 multiclass BaseSIMDStN
8773 int Offset128, int Offset64, bits<4> opcode> {
87748774 let hasSideEffects = 0, mayStore = 1, mayLoad = 0 in {
87758775 def v16b : BaseSIMDLdSt<1, 0, opcode, 0b00, asm, (outs),
87768776 (ins !cast(veclist # "16b"):$Vt,
88318831 !cast("GPR64pi" # Offset64):$Xm)>;
88328832 }
88338833
8834 defm : SIMDLdStAliases;
8835 defm : SIMDLdStAliases;
8836 defm : SIMDLdStAliases;
8837 defm : SIMDLdStAliases;
8838 defm : SIMDLdStAliases;
8839 defm : SIMDLdStAliases;
8840 defm : SIMDLdStAliases;
8841 }
8842
8843 multiclass BaseSIMDLd1
8834 defm : SIMDLdStAliases;
8835 defm : SIMDLdStAliases;
8836 defm : SIMDLdStAliases;
8837 defm : SIMDLdStAliases;
8838 defm : SIMDLdStAliases;
8839 defm : SIMDLdStAliases;
8840 defm : SIMDLdStAliases;
8841 }
8842
8843 multiclass BaseSIMDLd1
88448844 int Offset128, int Offset64, bits<4> opcode>
8845 : BaseSIMDLdN<Count, asm, veclist, Offset128, Offset64, opcode> {
8845 : BaseSIMDLdN<BaseName, Count, asm, veclist, Offset128, Offset64, opcode> {
88468846
88478847 // LD1 instructions have extra "1d" variants.
88488848 let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
88578857 !cast("GPR64pi" # Offset64):$Xm)>;
88588858 }
88598859
8860 defm : SIMDLdStAliases;
8861 }
8862
8863 multiclass BaseSIMDSt1
8860 defm : SIMDLdStAliases;
8861 }
8862
8863 multiclass BaseSIMDSt1
88648864 int Offset128, int Offset64, bits<4> opcode>
8865 : BaseSIMDStN<Count, asm, veclist, Offset128, Offset64, opcode> {
8865 : BaseSIMDStN<BaseName, Count, asm, veclist, Offset128, Offset64, opcode> {
88668866
88678867 // ST1 instructions have extra "1d" variants.
88688868 let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
88778877 !cast("GPR64pi" # Offset64):$Xm)>;
88788878 }
88798879
8880 defm : SIMDLdStAliases<asm, "1d", Count, Offset64, 64>;
8880 defm : SIMDLdStAliases<BaseName, asm, "1d", Count, Offset64, 64>;
88818881 }
88828882
88838883 multiclass SIMDLd1Multiple {
8884 defm One : BaseSIMDLd1<"One", asm, "VecListOne", 16, 8, 0b0111>;
8885 defm Two : BaseSIMDLd1<"Two", asm, "VecListTwo", 32, 16, 0b1010>;
8886 defm Three : BaseSIMDLd1<"Three", asm, "VecListThree", 48, 24, 0b0110>;
8887 defm Four : BaseSIMDLd1<"Four", asm, "VecListFour", 64, 32, 0b0010>;
8884 defm One : BaseSIMDLd1>;
8885 defm Two : BaseSIMDLd1;
8886 defm Three : BaseSIMDLd1;
8887 defm Four : BaseSIMDLd1;
88888888 }
88898889
88908890 multiclass SIMDSt1Multiple {
8891 defm One : BaseSIMDSt1<"One", asm, "VecListOne", 16, 8, 0b0111>;
8892 defm Two : BaseSIMDSt1<"Two", asm, "VecListTwo", 32, 16, 0b1010>;
8893 defm Three : BaseSIMDSt1<"Three", asm, "VecListThree", 48, 24, 0b0110>;
8894 defm Four : BaseSIMDSt1<"Four", asm, "VecListFour", 64, 32, 0b0010>;
8891 defm One : BaseSIMDSt1>;
8892 defm Two : BaseSIMDSt1;
8893 defm Three : BaseSIMDSt1;
8894 defm Four : BaseSIMDSt1;
88958895 }
88968896
88978897 multiclass SIMDLd2Multiple {
8898 defm Two : BaseSIMDLdN<"Two", asm, "VecListTwo", 32, 16, 0b1000>;
8898 defm Two : BaseSIMDLdN<NAME, "Two", asm, "VecListTwo", 32, 16, 0b1000>;
88998899 }
89008900
89018901 multiclass SIMDSt2Multiple {
8902 defm Two : BaseSIMDStN<"Two", asm, "VecListTwo", 32, 16, 0b1000>;
8902 defm Two : BaseSIMDStN<NAME, "Two", asm, "VecListTwo", 32, 16, 0b1000>;
89038903 }
89048904
89058905 multiclass SIMDLd3Multiple {
8906 defm Three : BaseSIMDLdN<"Three", asm, "VecListThree", 48, 24, 0b0100>;
8906 defm Three : BaseSIMDLdN<NAME, "Three", asm, "VecListThree", 48, 24, 0b0100>;
89078907 }
89088908
89098909 multiclass SIMDSt3Multiple {
8910 defm Three : BaseSIMDStN<"Three", asm, "VecListThree", 48, 24, 0b0100>;
8910 defm Three : BaseSIMDStN<NAME, "Three", asm, "VecListThree", 48, 24, 0b0100>;
89118911 }
89128912
89138913 multiclass SIMDLd4Multiple {
8914 defm Four : BaseSIMDLdN<"Four", asm, "VecListFour", 64, 32, 0b0000>;
8914 defm Four : BaseSIMDLdN<NAME, "Four", asm, "VecListFour", 64, 32, 0b0000>;
89158915 }
89168916
89178917 multiclass SIMDSt4Multiple {
8918 defm Four : BaseSIMDStN<"Four", asm, "VecListFour", 64, 32, 0b0000>;
8918 defm Four : BaseSIMDStN<NAME, "Four", asm, "VecListFour", 64, 32, 0b0000>;
89198919 }
89208920
89218921 //---
89808980 let Inst{11-10} = size;
89818981 }
89828982
8983 multiclass SIMDLdrAliasesasm, string layout, string Count,
8983 multiclass SIMDLdrAliasesBaseName, string asm, string layout, string Count,
89848984 int Offset, int Size> {
89858985 // E.g. "ld1r { v0.8b }, [x1], #1"
89868986 // "ld1r.8b\t$Vt, [$Rn], #1"
89878987 // may get mapped to
89888988 // (LD1Rv8b_POST VecListOne8b:$Vt, GPR64sp:$Rn, XZR)
89898989 def : InstAlias
8990 (!cast(NAME # "v" # layout # "_POST")
8990 (!cast(BaseName # "v" # layout # "_POST")
89918991 GPR64sp:$Rn,
89928992 !cast("VecList" # Count # layout):$Vt,
89938993 XZR), 1>;
89978997 // may get mapped to
89988998 // (LD1Rv8b_POST VecListOne64:$Vt, GPR64sp:$Rn, XZR)
89998999 def : InstAlias
9000 (!cast(NAME # "v" # layout # "_POST")
9000 (!cast(BaseName # "v" # layout # "_POST")
90019001 GPR64sp:$Rn,
90029002 !cast("VecList" # Count # Size):$Vt,
90039003 XZR), 0>;
90079007 // may get mapped to
90089008 // (LD1Rv8b VecListOne64:$Vt, GPR64sp:$Rn)
90099009 def : InstAlias
9010 (!cast(NAME # "v" # layout)
9010 (!cast(BaseName # "v" # layout)
90119011 !cast("VecList" # Count # Size):$Vt,
90129012 GPR64sp:$Rn), 0>;
90139013
90169016 // may get mapped to
90179017 // (LD1Rv8b_POST VecListOne64:$Vt, GPR64sp:$Rn, GPR64pi1:$Xm)
90189018 def : InstAlias
9019 (!cast(NAME # "v" # layout # "_POST")
9019 (!cast(BaseName # "v" # layout # "_POST")
90209020 GPR64sp:$Rn,
90219021 !cast("VecList" # Count # Size):$Vt,
90229022 !cast("GPR64pi" # Offset):$Xm), 0>;
90669066 !cast("VecList" # Count # "2d"),
90679067 !cast("GPR64pi" # Offset8)>;
90689068
9069 defm : SIMDLdrAliases;
9070 defm : SIMDLdrAliases;
9071 defm : SIMDLdrAliases;
9072 defm : SIMDLdrAliases;
9073 defm : SIMDLdrAliases;
9074 defm : SIMDLdrAliases;
9075 defm : SIMDLdrAliases;
9076 defm : SIMDLdrAliases<asm, "2d", Count, Offset8, 128>;
9069 defm : SIMDLdrAliases<NAME, asm, "8b", Count, Offset1, 64>;
9070 defm : SIMDLdrAliases;
9071 defm : SIMDLdrAliases;
9072 defm : SIMDLdrAliases;
9073 defm : SIMDLdrAliases;
9074 defm : SIMDLdrAliases;
9075 defm : SIMDLdrAliases;
9076 defm : SIMDLdrAliases;
90779077 }
90789078
90799079 class SIMDLdStSingleB opcode, string asm,
94319431 }
94329432
94339433 multiclass SIMDLdSt1SingleAliases {
9434 defm : SIMDLdStSingleAliases;
9435 defm : SIMDLdStSingleAliases;
9436 defm : SIMDLdStSingleAliases;
9437 defm : SIMDLdStSingleAliases>;
9434 defm "" : SIMDLdStSingleAliases>;
9435 defm "" : SIMDLdStSingleAliases;
9436 defm "" : SIMDLdStSingleAliases;
9437 defm "" : SIMDLdStSingleAliases;
94389438 }
94399439
94409440 multiclass SIMDLdSt2SingleAliases {
9441 defm : SIMDLdStSingleAliases;
9442 defm : SIMDLdStSingleAliases;
9443 defm : SIMDLdStSingleAliases;
9444 defm : SIMDLdStSingleAliases>;
9441 defm "" : SIMDLdStSingleAliases>;
9442 defm "" : SIMDLdStSingleAliases;
9443 defm "" : SIMDLdStSingleAliases;
9444 defm "" : SIMDLdStSingleAliases;
94459445 }
94469446
94479447 multiclass SIMDLdSt3SingleAliases {
9448 defm : SIMDLdStSingleAliases;
9449 defm : SIMDLdStSingleAliases;
9450 defm : SIMDLdStSingleAliases;
9451 defm : SIMDLdStSingleAliases>;
9448 defm "" : SIMDLdStSingleAliases>;
9449 defm "" : SIMDLdStSingleAliases;
9450 defm "" : SIMDLdStSingleAliases;
9451 defm "" : SIMDLdStSingleAliases;
94529452 }
94539453
94549454 multiclass SIMDLdSt4SingleAliases {
9455 defm : SIMDLdStSingleAliases;
9456 defm : SIMDLdStSingleAliases;
9457 defm : SIMDLdStSingleAliases;
9458 defm : SIMDLdStSingleAliases>;
9455 defm "" : SIMDLdStSingleAliases>;
9456 defm "" : SIMDLdStSingleAliases;
9457 defm "" : SIMDLdStSingleAliases;
9458 defm "" : SIMDLdStSingleAliases;
94599459 }
94609460 } // end of 'let Predicates = [HasNEON]'
94619461
5151 "")))));
5252 }
5353
54 class MUBUFAddr64Table suffix = ""> {
54 class MUBUFAddr64Table Name> {
5555 bit IsAddr64 = is_addr64;
56 string OpName = NAME # suffix;
57 }
58
59 class MUBUFLdsTable {
56 string OpName = Name;
57 }
58
59 class MUBUFLdsTable {
6060 bit IsLds = is_lds;
61 string OpName = NAME # suffix;
62 }
63
64 class MTBUFAddr64Table {
61 string OpName = Name;
62 }
63
64 class MTBUFAddr64Table {
6565 bit IsAddr64 = is_addr64;
66 string OpName = NAME # suffix;
66 string OpName = Name;
6767 }
6868
6969 //===----------------------------------------------------------------------===//
218218 [(set load_vt:$vdata,
219219 (ld (MUBUFOffset v4i32:$srsrc, i32:$soffset, i16:$offset, i8:$dfmt,
220220 i8:$nfmt, i1:$glc, i1:$slc, i1:$tfe)))]>,
221 MTBUFAddr64Table<0>;
221 MTBUFAddr64Table<0, NAME>;
222222
223223 def _ADDR64 : MTBUF_Load_Pseudo
224224 [(set load_vt:$vdata,
225225 (ld (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i32:$soffset, i16:$offset,
226226 i8:$dfmt, i8:$nfmt, i1:$glc, i1:$slc, i1:$tfe)))]>,
227 MTBUFAddr64Table<1>;
227 MTBUFAddr64Table<1, NAME>;
228228
229229 def _OFFEN : MTBUF_Load_Pseudo ;
230230 def _IDXEN : MTBUF_Load_Pseudo ;
264264 [(st store_vt:$vdata, (MUBUFOffset v4i32:$srsrc, i32:$soffset,
265265 i16:$offset, i8:$dfmt, i8:$nfmt, i1:$glc,
266266 i1:$slc, i1:$tfe))]>,
267 MTBUFAddr64Table<0>;
267 MTBUFAddr64Table<0, NAME>;
268268
269269 def _ADDR64 : MTBUF_Store_Pseudo
270270 [(st store_vt:$vdata, (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i32:$soffset,
271271 i16:$offset, i8:$dfmt, i8:$nfmt, i1:$glc,
272272 i1:$slc, i1:$tfe))]>,
273 MTBUFAddr64Table<1>;
273 MTBUFAddr64Table<1, NAME>;
274274
275275 def _OFFEN : MTBUF_Store_Pseudo ;
276276 def _IDXEN : MTBUF_Store_Pseudo ;
473473 [],
474474 [(set load_vt:$vdata,
475475 (ld (MUBUFOffset v4i32:$srsrc, i32:$soffset, i16:$offset, i1:$glc, i1:$slc, i1:$tfe)))])>,
476 MUBUFAddr64Table<0, !if(isLds, "_LDS", "")>;
476 MUBUFAddr64Table<0, NAME # !if(isLds, "_LDS", "")>;
477477
478478 def _ADDR64 : MUBUF_Load_Pseudo
479479 TiedDest, isLds,
481481 [],
482482 [(set load_vt:$vdata,
483483 (ld (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i32:$soffset, i16:$offset, i1:$glc, i1:$slc, i1:$tfe)))])>,
484 MUBUFAddr64Table<1, !if(isLds, "_LDS", "")>;
484 MUBUFAddr64Table<1, NAME # !if(isLds, "_LDS", "")>;
485485
486486 def _OFFEN : MUBUF_Load_Pseudo ;
487487 def _IDXEN : MUBUF_Load_Pseudo ;
529529 def _OFFSET : MUBUF_Store_Pseudo
530530 [(st store_vt:$vdata, (MUBUFOffset v4i32:$srsrc, i32:$soffset,
531531 i16:$offset, i1:$glc, i1:$slc, i1:$tfe))]>,
532 MUBUFAddr64Table<0>;
532 MUBUFAddr64Table<0, NAME>;
533533
534534 def _ADDR64 : MUBUF_Store_Pseudo
535535 [(st store_vt:$vdata, (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i32:$soffset,
536536 i16:$offset, i1:$glc, i1:$slc, i1:$tfe))]>,
537 MUBUFAddr64Table<1>;
537 MUBUFAddr64Table<1, NAME>;
538538
539539 def _OFFEN : MUBUF_Store_Pseudo ;
540540 def _IDXEN : MUBUF_Store_Pseudo ;
665665 SDPatternOperator atomic> {
666666
667667 def _OFFSET : MUBUF_AtomicNoRet_Pseudo ,
668 MUBUFAddr64Table <0>;
668 MUBUFAddr64Table <0, NAME>;
669669 def _ADDR64 : MUBUF_AtomicNoRet_Pseudo ,
670 MUBUFAddr64Table <1>;
670 MUBUFAddr64Table <1, NAME>;
671671 def _OFFEN : MUBUF_AtomicNoRet_Pseudo ;
672672 def _IDXEN : MUBUF_AtomicNoRet_Pseudo ;
673673 def _BOTHEN : MUBUF_AtomicNoRet_Pseudo ;
676676 [(set vdataType:$vdata,
677677 (atomic (MUBUFOffsetAtomic v4i32:$srsrc, i32:$soffset, i16:$offset, i1:$slc),
678678 vdataType:$vdata_in))]>,
679 MUBUFAddr64Table <0, "_RTN">;
679 MUBUFAddr64Table <0, NAME # "_RTN">;
680680
681681 def _ADDR64_RTN : MUBUF_AtomicRet_Pseudo
682682 [(set vdataType:$vdata,
683683 (atomic (MUBUFAddr64Atomic v4i32:$srsrc, i64:$vaddr, i32:$soffset, i16:$offset, i1:$slc),
684684 vdataType:$vdata_in))]>,
685 MUBUFAddr64Table <1, "_RTN">;
685 MUBUFAddr64Table <1, NAME # "_RTN">;
686686
687687 def _OFFEN_RTN : MUBUF_AtomicRet_Pseudo ;
688688 def _IDXEN_RTN : MUBUF_AtomicRet_Pseudo ;
16621662 multiclass MUBUF_Real_AllAddr_Lds_si op> {
16631663
16641664 def _OFFSET_si : MUBUF_Real_si (NAME#"_OFFSET")>,
1665 MUBUFLdsTable<0, "_OFFSET_si">;
1665 MUBUFLdsTable<0, NAME # "_OFFSET_si">;
16661666 def _ADDR64_si : MUBUF_Real_si (NAME#"_ADDR64")>,
1667 MUBUFLdsTable<0, "_ADDR64_si">;
1667 MUBUFLdsTable<0, NAME # "_ADDR64_si">;
16681668 def _OFFEN_si : MUBUF_Real_si (NAME#"_OFFEN")>,
1669 MUBUFLdsTable<0, "_OFFEN_si">;
1669 MUBUFLdsTable<0, NAME # "_OFFEN_si">;
16701670 def _IDXEN_si : MUBUF_Real_si (NAME#"_IDXEN")>,
1671 MUBUFLdsTable<0, "_IDXEN_si">;
1671 MUBUFLdsTable<0, NAME # "_IDXEN_si">;
16721672 def _BOTHEN_si : MUBUF_Real_si (NAME#"_BOTHEN")>,
1673 MUBUFLdsTable<0, "_BOTHEN_si">;
1673 MUBUFLdsTable<0, NAME # "_BOTHEN_si">;
16741674
16751675 def _LDS_OFFSET_si : MUBUF_Real_si (NAME#"_LDS_OFFSET")>,
1676 MUBUFLdsTable<1, "_OFFSET_si">;
1676 MUBUFLdsTable<1, NAME # "_OFFSET_si">;
16771677 def _LDS_ADDR64_si : MUBUF_Real_si (NAME#"_LDS_ADDR64")>,
1678 MUBUFLdsTable<1, "_ADDR64_si">;
1678 MUBUFLdsTable<1, NAME # "_ADDR64_si">;
16791679 def _LDS_OFFEN_si : MUBUF_Real_si (NAME#"_LDS_OFFEN")>,
1680 MUBUFLdsTable<1, "_OFFEN_si">;
1680 MUBUFLdsTable<1, NAME # "_OFFEN_si">;
16811681 def _LDS_IDXEN_si : MUBUF_Real_si (NAME#"_LDS_IDXEN")>,
1682 MUBUFLdsTable<1, "_IDXEN_si">;
1682 MUBUFLdsTable<1, NAME # "_IDXEN_si">;
16831683 def _LDS_BOTHEN_si : MUBUF_Real_si (NAME#"_LDS_BOTHEN")>,
1684 MUBUFLdsTable<1, "_BOTHEN_si">;
1684 MUBUFLdsTable<1, NAME # "_BOTHEN_si">;
16851685 }
16861686
16871687 multiclass MUBUF_Real_Atomic_si op> : MUBUF_Real_AllAddr_si {
18451845 multiclass MUBUF_Real_AllAddr_Lds_vi op> {
18461846
18471847 def _OFFSET_vi : MUBUF_Real_vi (NAME#"_OFFSET")>,
1848 MUBUFLdsTable<0, "_OFFSET_vi">;
1848 MUBUFLdsTable<0, NAME # "_OFFSET_vi">;
18491849 def _OFFEN_vi : MUBUF_Real_vi (NAME#"_OFFEN")>,
1850 MUBUFLdsTable<0, "_OFFEN_vi">;
1850 MUBUFLdsTable<0, NAME # "_OFFEN_vi">;
18511851 def _IDXEN_vi : MUBUF_Real_vi (NAME#"_IDXEN")>,
1852 MUBUFLdsTable<0, "_IDXEN_vi">;
1852 MUBUFLdsTable<0, NAME # "_IDXEN_vi">;
18531853 def _BOTHEN_vi : MUBUF_Real_vi (NAME#"_BOTHEN")>,
1854 MUBUFLdsTable<0, "_BOTHEN_vi">;
1854 MUBUFLdsTable<0, NAME # "_BOTHEN_vi">;
18551855
18561856 def _LDS_OFFSET_vi : MUBUF_Real_vi (NAME#"_LDS_OFFSET")>,
1857 MUBUFLdsTable<1, "_OFFSET_vi">;
1857 MUBUFLdsTable<1, NAME # "_OFFSET_vi">;
18581858 def _LDS_OFFEN_vi : MUBUF_Real_vi (NAME#"_LDS_OFFEN")>,
1859 MUBUFLdsTable<1, "_OFFEN_vi">;
1859 MUBUFLdsTable<1, NAME # "_OFFEN_vi">;
18601860 def _LDS_IDXEN_vi : MUBUF_Real_vi (NAME#"_LDS_IDXEN")>,
1861 MUBUFLdsTable<1, "_IDXEN_vi">;
1861 MUBUFLdsTable<1, NAME # "_IDXEN_vi">;
18621862 def _LDS_BOTHEN_vi : MUBUF_Real_vi (NAME#"_LDS_BOTHEN")>,
1863 MUBUFLdsTable<1, "_BOTHEN_vi">;
1863 MUBUFLdsTable<1, NAME # "_BOTHEN_vi">;
18641864 }
18651865
18661866 class MUBUF_Real_gfx80 op, MUBUF_Pseudo ps> :
279279 multiclass MIMG_Sampler_Src_Helper op, string asm,
280280 RegisterClass dst_rc,
281281 int channels, bit wqm> {
282 defm : MIMG_Sampler_Src_Helper_Helper ;
282 defm "" : MIMG_Sampler_Src_Helper_Helper ;
283283
284284 let d16 = 1 in {
285285 let SubtargetPredicate = HasPackedD16VMem in {
286 defm : MIMG_Sampler_Src_Helper_Helper ;
286 defm "" : MIMG_Sampler_Src_Helper_Helper ;
287287 } // End HasPackedD16VMem.
288288
289289 let SubtargetPredicate = HasUnpackedD16VMem, DecoderNamespace = "GFX80_UNPACKED" in {
290 defm : MIMG_Sampler_Src_Helper_Helper ;
290 defm "" : MIMG_Sampler_Src_Helper_Helper ;
291291 } // End HasUnpackedD16VMem.
292292 } // End d16 = 1.
293293 }
347347 }
348348
349349 multiclass MIMG_Gather op, string asm, bit wqm=0> {
350 defm : MIMG_Gather_Src_Helper;
350 defm "" : MIMG_Gather_Src_Helper;
351351
352352 let d16 = 1 in {
353353 let AssemblerPredicate = HasPackedD16VMem in {
354 defm : MIMG_Gather_Src_Helper;
354 defm "" : MIMG_Gather_Src_Helper;
355355 } // End HasPackedD16VMem.
356356
357357 let AssemblerPredicate = HasUnpackedD16VMem, DecoderNamespace = "GFX80_UNPACKED" in {
358 defm : MIMG_Gather_Src_Helper;
358 defm "" : MIMG_Gather_Src_Helper;
359359 } // End HasUnpackedD16VMem.
360360 } // End d16 = 1.
361361 }
11291129 //---
11301130 // broadcast with a scalar argument.
11311131 multiclass avx512_broadcast_scalar opc, string OpcodeStr,
1132 string Name,
11321133 X86VectorVTInfo DestInfo, X86VectorVTInfo SrcInfo> {
11331134 def : Pat<(DestInfo.VT (X86VBroadcast SrcInfo.FRC:$src)),
1134 (!cast(NAME#DestInfo.ZSuffix#r)
1135 (!cast(Name#DestInfo.ZSuffix#r)
11351136 (COPY_TO_REGCLASS SrcInfo.FRC:$src, SrcInfo.RC))>;
11361137 def : Pat<(DestInfo.VT (vselect DestInfo.KRCWM:$mask,
11371138 (X86VBroadcast SrcInfo.FRC:$src),
11381139 DestInfo.RC:$src0)),
1139 (!cast(NAME#DestInfo.ZSuffix#rk)
1140 (!cast(Name#DestInfo.ZSuffix#rk)
11401141 DestInfo.RC:$src0, DestInfo.KRCWM:$mask,
11411142 (COPY_TO_REGCLASS SrcInfo.FRC:$src, SrcInfo.RC))>;
11421143 def : Pat<(DestInfo.VT (vselect DestInfo.KRCWM:$mask,
11431144 (X86VBroadcast SrcInfo.FRC:$src),
11441145 DestInfo.ImmAllZerosV)),
1145 (!cast(NAME#DestInfo.ZSuffix#rkz)
1146 (!cast(Name#DestInfo.ZSuffix#rkz)
11461147 DestInfo.KRCWM:$mask, (COPY_TO_REGCLASS SrcInfo.FRC:$src, SrcInfo.RC))>;
11471148 }
11481149
11491150 // Split version to allow mask and broadcast node to be different types. This
11501151 // helps support the 32x2 broadcasts.
11511152 multiclass avx512_broadcast_rm_split opc, string OpcodeStr,
1153 string Name,
11521154 SchedWrite SchedRR, SchedWrite SchedRM,
11531155 X86VectorVTInfo MaskInfo,
11541156 X86VectorVTInfo DestInfo,
11881190 (DestInfo.VT (UnmaskedOp
11891191 (SrcInfo.VT (scalar_to_vector
11901192 (SrcInfo.ScalarLdFrag addr:$src))))))),
1191 (!cast(NAME#MaskInfo.ZSuffix#m) addr:$src)>;
1193 (!cast(Name#MaskInfo.ZSuffix#m) addr:$src)>;
11921194 def : Pat<(MaskInfo.VT (vselect MaskInfo.KRCWM:$mask,
11931195 (bitconvert
11941196 (DestInfo.VT
11961198 (SrcInfo.VT (scalar_to_vector
11971199 (SrcInfo.ScalarLdFrag addr:$src)))))),
11981200 MaskInfo.RC:$src0)),
1199 (!cast(NAME#DestInfo.ZSuffix#mk)
1201 (!cast(Name#DestInfo.ZSuffix#mk)
12001202 MaskInfo.RC:$src0, MaskInfo.KRCWM:$mask, addr:$src)>;
12011203 def : Pat<(MaskInfo.VT (vselect MaskInfo.KRCWM:$mask,
12021204 (bitconvert
12051207 (SrcInfo.VT (scalar_to_vector
12061208 (SrcInfo.ScalarLdFrag addr:$src)))))),
12071209 MaskInfo.ImmAllZerosV)),
1208 (!cast(NAME#MaskInfo.ZSuffix#mkz)
1210 (!cast(Name#MaskInfo.ZSuffix#mkz)
12091211 MaskInfo.KRCWM:$mask, addr:$src)>;
12101212 }
12111213
12121214 // Helper class to force mask and broadcast result to same type.
1213 multiclass avx512_broadcast_rm opc, string OpcodeStr,
1215 multiclass avx512_broadcast_rm opc, string OpcodeStr, string Name,
12141216 SchedWrite SchedRR, SchedWrite SchedRM,
12151217 X86VectorVTInfo DestInfo,
12161218 X86VectorVTInfo SrcInfo> :
1217 avx512_broadcast_rm_splitSchedRR, SchedRM,
1219 avx512_broadcast_rm_splitName, SchedRR, SchedRM,
12181220 DestInfo, DestInfo, SrcInfo>;
12191221
12201222 multiclass avx512_fp_broadcast_sd opc, string OpcodeStr,
12211223 AVX512VLVectorVTInfo _> {
12221224 let Predicates = [HasAVX512] in {
1223 defm Z : avx512_broadcast_rmWriteFShuffle256,
1225 defm Z : avx512_broadcast_rmNAME, WriteFShuffle256,
12241226 WriteFShuffle256Ld, _.info512, _.info128>,
1225 avx512_broadcast_scalar,
1226 EVEX_V512;
1227 avx512_broadcast_scalar
1228 _.info128>,
1229 EVEX_V512;
12271230 }
12281231
12291232 let Predicates = [HasVLX] in {
1230 defm Z256 : avx512_broadcast_rmWriteFShuffle256,
1233 defm Z256 : avx512_broadcast_rmNAME, WriteFShuffle256,
12311234 WriteFShuffle256Ld, _.info256, _.info128>,
1232 avx512_broadcast_scalar,
1233 EVEX_V256;
1235 avx512_broadcast_scalar
1236 _.info128>,
1237 EVEX_V256;
12341238 }
12351239 }
12361240
12371241 multiclass avx512_fp_broadcast_ss opc, string OpcodeStr,
12381242 AVX512VLVectorVTInfo _> {
12391243 let Predicates = [HasAVX512] in {
1240 defm Z : avx512_broadcast_rmWriteFShuffle256,
1244 defm Z : avx512_broadcast_rmNAME, WriteFShuffle256,
12411245 WriteFShuffle256Ld, _.info512, _.info128>,
1242 avx512_broadcast_scalar,
1243 EVEX_V512;
1246 avx512_broadcast_scalar
1247 _.info128>,
1248 EVEX_V512;
12441249 }
12451250
12461251 let Predicates = [HasVLX] in {
1247 defm Z256 : avx512_broadcast_rmWriteFShuffle256,
1252 defm Z256 : avx512_broadcast_rmNAME, WriteFShuffle256,
12481253 WriteFShuffle256Ld, _.info256, _.info128>,
1249 avx512_broadcast_scalar,
1250 EVEX_V256;
1251 defm Z128 : avx512_broadcast_rm256,
1254 avx512_broadcast_scalar256,
1255 _.info128>,
1256 EVEX_V256;
1257 defm Z128 : avx512_broadcast_rm
12521258 WriteFShuffle256Ld, _.info128, _.info128>,
1253 avx512_broadcast_scalar,
1254 EVEX_V128;
1259 avx512_broadcast_scalar
1260 _.info128>,
1261 EVEX_V128;
12551262 }
12561263 }
12571264 defm VBROADCASTSS : avx512_fp_broadcast_ss<0x18, "vbroadcastss",
13341341
13351342 // Provide aliases for broadcast from the same register class that
13361343 // automatically does the extract.
1337 multiclass avx512_int_broadcast_rm_lowering<X86VectorVTInfo DestInfo,
1344 multiclass avx512_int_broadcast_rm_lowering<string Name,
1345 X86VectorVTInfo DestInfo,
13381346 X86VectorVTInfo SrcInfo> {
13391347 def : Pat<(DestInfo.VT (X86VBroadcast (SrcInfo.VT SrcInfo.RC:$src))),
1340 (!cast(NAME#DestInfo.ZSuffix#"r")
1348 (!cast(Name#DestInfo.ZSuffix#"r")
13411349 (EXTRACT_SUBREG (SrcInfo.VT SrcInfo.RC:$src), sub_xmm))>;
13421350 }
13431351
13441352 multiclass avx512_int_broadcast_rm_vl opc, string OpcodeStr,
13451353 AVX512VLVectorVTInfo _, Predicate prd> {
13461354 let Predicates = [prd] in {
1347 defm Z : avx512_broadcast_rmWriteShuffle256,
1355 defm Z : avx512_broadcast_rmNAME, WriteShuffle256,
13481356 WriteShuffle256Ld, _.info512, _.info128>,
1349 avx512_int_broadcast_rm_lowering<_.info512, _.info256>,
1357 avx512_int_broadcast_rm_lowering<NAME, _.info512, _.info256>,
13501358 EVEX_V512;
13511359 // Defined separately to avoid redefinition.
1352 defm Z_Alt : avx512_int_broadcast_rm_lowering<_.info512, _.info512>;
1360 defm Z_Alt : avx512_int_broadcast_rm_lowering<NAME, _.info512, _.info512>;
13531361 }
13541362 let Predicates = [prd, HasVLX] in {
1355 defm Z256 : avx512_broadcast_rmWriteShuffle256,
1363 defm Z256 : avx512_broadcast_rmNAME, WriteShuffle256,
13561364 WriteShuffle256Ld, _.info256, _.info128>,
1357 avx512_int_broadcast_rm_lowering<_.info256, _.info256>,
1365 avx512_int_broadcast_rm_lowering<NAME, _.info256, _.info256>,
13581366 EVEX_V256;
1359 defm Z128 : avx512_broadcast_rmWriteShuffle,
1367 defm Z128 : avx512_broadcast_rmNAME, WriteShuffle,
13601368 WriteShuffleXLd, _.info128, _.info128>,
13611369 EVEX_V128;
13621370 }
16551663 multiclass avx512_common_broadcast_32x2 opc, string OpcodeStr,
16561664 AVX512VLVectorVTInfo _Dst, AVX512VLVectorVTInfo _Src> {
16571665 let Predicates = [HasDQI] in
1658 defm Z : avx512_broadcast_rm_splitWriteShuffle256,
1666 defm Z : avx512_broadcast_rm_splitNAME, WriteShuffle256,
16591667 WriteShuffle256Ld, _Dst.info512,
16601668 _Src.info512, _Src.info128, null_frag>,
16611669 EVEX_V512;
16621670 let Predicates = [HasDQI, HasVLX] in
1663 defm Z256 : avx512_broadcast_rm_splitWriteShuffle256,
1671 defm Z256 : avx512_broadcast_rm_splitNAME, WriteShuffle256,
16641672 WriteShuffle256Ld, _Dst.info256,
16651673 _Src.info256, _Src.info128, null_frag>,
16661674 EVEX_V256;
16711679 avx512_common_broadcast_32x2 {
16721680
16731681 let Predicates = [HasDQI, HasVLX] in
1674 defm Z128 : avx512_broadcast_rm_splitWriteShuffle,
1682 defm Z128 : avx512_broadcast_rm_splitNAME, WriteShuffle,
16751683 WriteShuffleXLd, _Dst.info128,
16761684 _Src.info128, _Src.info128, null_frag>,
16771685 EVEX_V128;
22782286 }]>;
22792287
22802288 multiclass avx512_icmp_cc opc, string Suffix, SDNode OpNode,
2281 X86FoldableSchedWrite sched, X86VectorVTInfo _> {
2289 X86FoldableSchedWrite sched, X86VectorVTInfo _,
2290 string Name> {
22822291 let isCommutable = 1 in
22832292 def rri : AVX512AIi8
22842293 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, AVX512ICC:$cc),
23502359
23512360 def : Pat<(OpNode (bitconvert (_.LdFrag addr:$src2)),
23522361 (_.VT _.RC:$src1), imm:$cc),
2353 (!cast(NAME#_.ZSuffix#"rmi") _.RC:$src1, addr:$src2,
2362 (!cast(Name#_.ZSuffix#"rmi") _.RC:$src1, addr:$src2,
23542363 (CommutePCMPCC imm:$cc))>;
23552364
23562365 def : Pat<(and _.KRCWM:$mask, (OpNode (bitconvert (_.LdFrag addr:$src2)),
23572366 (_.VT _.RC:$src1), imm:$cc)),
2358 (!cast(NAME#_.ZSuffix#"rmik") _.KRCWM:$mask,
2367 (!cast(Name#_.ZSuffix#"rmik") _.KRCWM:$mask,
23592368 _.RC:$src1, addr:$src2,
23602369 (CommutePCMPCC imm:$cc))>;
23612370 }
23622371
23632372 multiclass avx512_icmp_cc_rmb opc, string Suffix, SDNode OpNode,
2364 X86FoldableSchedWrite sched, X86VectorVTInfo _> :
2365 avx512_icmp_cc {
2373 X86FoldableSchedWrite sched, X86VectorVTInfo _,
2374 string Name> :
2375 avx512_icmp_cc {
23662376 def rmib : AVX512AIi8
23672377 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
23682378 AVX512ICC:$cc),
24052415
24062416 def : Pat<(OpNode (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
24072417 (_.VT _.RC:$src1), imm:$cc),
2408 (!cast(NAME#_.ZSuffix#"rmib") _.RC:$src1, addr:$src2,
2418 (!cast(Name#_.ZSuffix#"rmib") _.RC:$src1, addr:$src2,
24092419 (CommutePCMPCC imm:$cc))>;
24102420
24112421 def : Pat<(and _.KRCWM:$mask, (OpNode (X86VBroadcast
24122422 (_.ScalarLdFrag addr:$src2)),
24132423 (_.VT _.RC:$src1), imm:$cc)),
2414 (!cast(NAME#_.ZSuffix#"rmibk") _.KRCWM:$mask,
2424 (!cast(Name#_.ZSuffix#"rmibk") _.KRCWM:$mask,
24152425 _.RC:$src1, addr:$src2,
24162426 (CommutePCMPCC imm:$cc))>;
24172427 }
24202430 X86SchedWriteWidths sched,
24212431 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
24222432 let Predicates = [prd] in
2423 defm Z : avx512_icmp_cc,
2424 EVEX_V512;
2433 defm Z : avx512_icmp_cc,
2434 EVEX_V512;
24252435
24262436 let Predicates = [prd, HasVLX] in {
2427 defm Z256 : avx512_icmp_cc,
2428 EVEX_V256;
2429 defm Z128 : avx512_icmp_cc,
2430 EVEX_V128;
2437 defm Z256 : avx512_icmp_cc
2438 NAME>,
2439 EVEX_V256;
2440 defm Z128 : avx512_icmp_cc
2441 NAME>,
2442 EVEX_V128;
24312443 }
24322444 }
24332445
24362448 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
24372449 let Predicates = [prd] in
24382450 defm Z : avx512_icmp_cc_rmb
2439 VTInfo.info512>, EVEX_V512;
2451 VTInfo.info512, NAME>, EVEX_V512;
24402452
24412453 let Predicates = [prd, HasVLX] in {
24422454 defm Z256 : avx512_icmp_cc_rmb
2443 VTInfo.info256>, EVEX_V256;
2455 VTInfo.info256, NAME>, EVEX_V256;
24442456 defm Z128 : avx512_icmp_cc_rmb
2445 VTInfo.info128>, EVEX_V128;
2457 VTInfo.info128, NAME>, EVEX_V128;
24462458 }
24472459 }
24482460
24732485 avx512vl_i64_info, HasAVX512>,
24742486 VEX_W, EVEX_CD8<64, CD8VF>;
24752487
2476 multiclass avx512_vcmp_common> {
2488 multiclass avx512_vcmp_common,
2489 string Name> {
24772490 defm rri : AVX512_maskable_cmp<0xC2, MRMSrcReg, _,
24782491 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2,AVXCC:$cc),
24792492 "vcmp${cc}"#_.Suffix,
25322545 // Patterns for selecting with loads in other operand.
25332546 def : Pat<(X86cmpm (_.LdFrag addr:$src2), (_.VT _.RC:$src1),
25342547 CommutableCMPCC:$cc),
2535 (!cast(NAME#_.ZSuffix#"rmi") _.RC:$src1, addr:$src2,
2548 (!cast(Name#_.ZSuffix#"rmi") _.RC:$src1, addr:$src2,
25362549 imm:$cc)>;
25372550
25382551 def : Pat<(and _.KRCWM:$mask, (X86cmpm (_.LdFrag addr:$src2),
25392552 (_.VT _.RC:$src1),
25402553 CommutableCMPCC:$cc)),
2541 (!cast(NAME#_.ZSuffix#"rmik") _.KRCWM:$mask,
2554 (!cast(Name#_.ZSuffix#"rmik") _.KRCWM:$mask,
25422555 _.RC:$src1, addr:$src2,
25432556 imm:$cc)>;
25442557
25452558 def : Pat<(X86cmpm (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
25462559 (_.VT _.RC:$src1), CommutableCMPCC:$cc),
2547 (!cast(NAME#_.ZSuffix#"rmbi") _.RC:$src1, addr:$src2,
2560 (!cast(Name#_.ZSuffix#"rmbi") _.RC:$src1, addr:$src2,
25482561 imm:$cc)>;
25492562
25502563 def : Pat<(and _.KRCWM:$mask, (X86cmpm (X86VBroadcast
25512564 (_.ScalarLdFrag addr:$src2)),
25522565 (_.VT _.RC:$src1),
25532566 CommutableCMPCC:$cc)),
2554 (!cast(NAME#_.ZSuffix#"rmbik") _.KRCWM:$mask,
2567 (!cast(Name#_.ZSuffix#"rmbik") _.KRCWM:$mask,
25552568 _.RC:$src1, addr:$src2,
25562569 imm:$cc)>;
25572570 }
25812594
25822595 multiclass avx512_vcmp {
25832596 let Predicates = [HasAVX512] in {
2584 defm Z : avx512_vcmp_common>,
2597 defm Z : avx512_vcmp_common, NAME>,
25852598 avx512_vcmp_sae, EVEX_V512;
25862599
25872600 }
25882601 let Predicates = [HasAVX512,HasVLX] in {
2589 defm Z128 : avx512_vcmp_common, EVEX_V128;
2590 defm Z256 : avx512_vcmp_common, EVEX_V256;
2602 defm Z128 : avx512_vcmp_common, EVEX_V128;
2603 defm Z256 : avx512_vcmp_common, EVEX_V256;
25912604 }
25922605 }
25932606
32353248 // AVX-512 - Aligned and unaligned load and store
32363249 //
32373250
3238 multiclass avx512_load opc, string OpcodeStr,
3251 multiclass avx512_load opc, string OpcodeStr, string Name,
32393252 X86VectorVTInfo _, PatFrag ld_frag, PatFrag mload,
32403253 X86SchedWriteMoveLS Sched, bit NoRMPattern = 0,
32413254 SDPatternOperator SelectOprr = vselect> {
32893302 _.ExeDomain>, EVEX, EVEX_KZ, Sched<[Sched.RM]>;
32903303 }
32913304 def : Pat<(_.VT (mload addr:$ptr, _.KRCWM:$mask, undef)),
3292 (!cast(NAME#_.ZSuffix##rmkz) _.KRCWM:$mask, addr:$ptr)>;
3305 (!cast(Name#_.ZSuffix##rmkz) _.KRCWM:$mask, addr:$ptr)>;
32933306
32943307 def : Pat<(_.VT (mload addr:$ptr, _.KRCWM:$mask, _.ImmAllZerosV)),
3295 (!cast(NAME#_.ZSuffix##rmkz) _.KRCWM:$mask, addr:$ptr)>;
3308 (!cast(Name#_.ZSuffix##rmkz) _.KRCWM:$mask, addr:$ptr)>;
32963309
32973310 def : Pat<(_.VT (mload addr:$ptr, _.KRCWM:$mask, (_.VT _.RC:$src0))),
3298 (!cast(NAME#_.ZSuffix##rmk) _.RC:$src0,
3311 (!cast(Name#_.ZSuffix##rmk) _.RC:$src0,
32993312 _.KRCWM:$mask, addr:$ptr)>;
33003313 }
33013314
33043317 X86SchedWriteMoveLSWidths Sched,
33053318 bit NoRMPattern = 0> {
33063319 let Predicates = [prd] in
3307 defm Z : avx512_load_.info512,
3320 defm Z : avx512_loadNAME, _.info512,
33083321 _.info512.AlignedLdFrag, masked_load_aligned512,
33093322 Sched.ZMM, NoRMPattern>, EVEX_V512;
33103323
33113324 let Predicates = [prd, HasVLX] in {
3312 defm Z256 : avx512_load_.info256,
3325 defm Z256 : avx512_loadNAME, _.info256,
33133326 _.info256.AlignedLdFrag, masked_load_aligned256,
33143327 Sched.YMM, NoRMPattern>, EVEX_V256;
3315 defm Z128 : avx512_load_.info128,
3328 defm Z128 : avx512_loadNAME, _.info128,
33163329 _.info128.AlignedLdFrag, masked_load_aligned128,
33173330 Sched.XMM, NoRMPattern>, EVEX_V128;
33183331 }
33243337 bit NoRMPattern = 0,
33253338 SDPatternOperator SelectOprr = vselect> {
33263339 let Predicates = [prd] in
3327 defm Z : avx512_load_.info512, _.info512.LdFrag,
3340 defm Z : avx512_loadNAME, _.info512, _.info512.LdFrag,
33283341 masked_load_unaligned, Sched.ZMM, NoRMPattern,
33293342 SelectOprr>, EVEX_V512;
33303343
33313344 let Predicates = [prd, HasVLX] in {
3332 defm Z256 : avx512_load_.info256, _.info256.LdFrag,
3345 defm Z256 : avx512_loadNAME, _.info256, _.info256.LdFrag,
33333346 masked_load_unaligned, Sched.YMM, NoRMPattern,
33343347 SelectOprr>, EVEX_V256;
3335 defm Z128 : avx512_load_.info128, _.info128.LdFrag,
3348 defm Z128 : avx512_loadNAME, _.info128, _.info128.LdFrag,
33363349 masked_load_unaligned, Sched.XMM, NoRMPattern,
33373350 SelectOprr>, EVEX_V128;
33383351 }
33393352 }
33403353
3341 multiclass avx512_store opc, string OpcodeStr,
3354 multiclass avx512_store opc, string OpcodeStr, string BaseName,
33423355 X86VectorVTInfo _, PatFrag st_frag, PatFrag mstore,
33433356 string Name, X86SchedWriteMoveLS Sched,
33443357 bit NoMRPattern = 0> {
33743387 [], _.ExeDomain>, EVEX, EVEX_K, Sched<[Sched.MR]>;
33753388
33763389 def: Pat<(mstore addr:$ptr, _.KRCWM:$mask, (_.VT _.RC:$src)),
3377 (!cast(NAME#_.ZSuffix##mrk) addr:$ptr,
3378 _.KRCWM:$mask, _.RC:$src)>;
3390 (!cast(BaseName#_.ZSuffix##mrk) addr:$ptr,
3391 _.KRCWM:$mask, _.RC:$src)>;
33793392 }
33803393
33813394 multiclass avx512_store_vl< bits<8> opc, string OpcodeStr,
33833396 string Name, X86SchedWriteMoveLSWidths Sched,
33843397 bit NoMRPattern = 0> {
33853398 let Predicates = [prd] in
3386 defm Z : avx512_store_.info512, store,
3399 defm Z : avx512_storeNAME, _.info512, store,
33873400 masked_store_unaligned, Name#Z, Sched.ZMM,
33883401 NoMRPattern>, EVEX_V512;
33893402 let Predicates = [prd, HasVLX] in {
3390 defm Z256 : avx512_store_.info256, store,
3403 defm Z256 : avx512_storeNAME, _.info256, store,
33913404 masked_store_unaligned, Name#Z256, Sched.YMM,
33923405 NoMRPattern>, EVEX_V256;
3393 defm Z128 : avx512_store_.info128, store,
3406 defm Z128 : avx512_storeNAME, _.info128, store,
33943407 masked_store_unaligned, Name#Z128, Sched.XMM,
33953408 NoMRPattern>, EVEX_V128;
33963409 }
34013414 string Name, X86SchedWriteMoveLSWidths Sched,
34023415 bit NoMRPattern = 0> {
34033416 let Predicates = [prd] in
3404 defm Z : avx512_store_.info512, alignedstore,
3417 defm Z : avx512_storeNAME, _.info512, alignedstore,
34053418 masked_store_aligned512, Name#Z, Sched.ZMM,
34063419 NoMRPattern>, EVEX_V512;
34073420
34083421 let Predicates = [prd, HasVLX] in {
3409 defm Z256 : avx512_store_.info256, alignedstore,
3422 defm Z256 : avx512_storeNAME, _.info256, alignedstore,
34103423 masked_store_aligned256, Name#Z256, Sched.YMM,
34113424 NoMRPattern>, EVEX_V256;
3412 defm Z128 : avx512_store_.info128, alignedstore,
3425 defm Z128 : avx512_storeNAME, _.info128, alignedstore,
34133426 masked_store_aligned128, Name#Z128, Sched.XMM,
34143427 NoMRPattern>, EVEX_V128;
34153428 }
54785491
54795492 multiclass avx512_vptest opc, string OpcodeStr, PatFrag OpNode,
54805493 X86FoldableSchedWrite sched, X86VectorVTInfo _,
5481 string Suffix> {
5494 string Name> {
54825495 let ExeDomain = _.ExeDomain in {
54835496 let isCommutable = 1 in
54845497 defm rr : AVX512_maskable_cmp
55005513
55015514 // Patterns for compare with 0 that just use the same source twice.
55025515 def : Pat<(_.KVT (OpNode _.RC:$src, _.ImmAllZerosV)),
5503 (_.KVT (!cast(NAME # Suffix # _.ZSuffix # "rr")
5516 (_.KVT (!cast(Name # _.ZSuffix # "rr")
55045517 _.RC:$src, _.RC:$src))>;
55055518
55065519 def : Pat<(_.KVT (and _.KRC:$mask, (OpNode _.RC:$src, _.ImmAllZerosV))),
5507 (_.KVT (!cast(NAME # Suffix # _.ZSuffix # "rrk")
5520 (_.KVT (!cast(Name # _.ZSuffix # "rrk")
55085521 _.KRC:$mask, _.RC:$src, _.RC:$src))>;
55095522 }
55105523
55255538
55265539 // Use 512bit version to implement 128/256 bit in case NoVLX.
55275540 multiclass avx512_vptest_lowering
5528 X86VectorVTInfo _, string Suffix> {
5541 X86VectorVTInfo _, string Name> {
55295542 def : Pat<(_.KVT (OpNode (bitconvert (_.i64VT (and _.RC:$src1, _.RC:$src2))),
55305543 _.ImmAllZerosV)),
55315544 (_.KVT (COPY_TO_REGCLASS
5532 (!cast(NAME # Suffix # "Zrr")
5545 (!cast(Name # "Zrr")
55335546 (INSERT_SUBREG (ExtendInfo.VT (IMPLICIT_DEF)),
55345547 _.RC:$src1, _.SubRegIdx),
55355548 (INSERT_SUBREG (ExtendInfo.VT (IMPLICIT_DEF)),
55405553 (OpNode (bitconvert (_.i64VT (and _.RC:$src1, _.RC:$src2))),
55415554 _.ImmAllZerosV))),
55425555 (COPY_TO_REGCLASS
5543 (!cast(NAME # Suffix # "Zrrk")
5556 (!cast(Name # "Zrrk")
55445557 (COPY_TO_REGCLASS _.KRC:$mask, ExtendInfo.KRC),
55455558 (INSERT_SUBREG (ExtendInfo.VT (IMPLICIT_DEF)),
55465559 _.RC:$src1, _.SubRegIdx),
55505563
55515564 def : Pat<(_.KVT (OpNode _.RC:$src, _.ImmAllZerosV)),
55525565 (_.KVT (COPY_TO_REGCLASS
5553 (!cast(NAME # Suffix # "Zrr")
5566 (!cast(Name # "Zrr")
55545567 (INSERT_SUBREG (ExtendInfo.VT (IMPLICIT_DEF)),
55555568 _.RC:$src, _.SubRegIdx),
55565569 (INSERT_SUBREG (ExtendInfo.VT (IMPLICIT_DEF)),
55595572
55605573 def : Pat<(_.KVT (and _.KRC:$mask, (OpNode _.RC:$src, _.ImmAllZerosV))),
55615574 (COPY_TO_REGCLASS
5562 (!cast(NAME # Suffix # "Zrrk")
5575 (!cast(Name # "Zrrk")
55635576 (COPY_TO_REGCLASS _.KRC:$mask, ExtendInfo.KRC),
55645577 (INSERT_SUBREG (ExtendInfo.VT (IMPLICIT_DEF)),
55655578 _.RC:$src, _.SubRegIdx),
55695582 }
55705583
55715584 multiclass avx512_vptest_dq_sizes opc, string OpcodeStr, PatFrag OpNode,
5572 X86SchedWriteWidths sched, AVX512VLVectorVTInfo _,
5573 string Suffix> {
5585 X86SchedWriteWidths sched, AVX512VLVectorVTInfo _> {
55745586 let Predicates = [HasAVX512] in
5575 defm Z : avx512_vptestSuffix>,
5587 defm Z : avx512_vptestNAME>,
55765588 avx512_vptest_mb, EVEX_V512;
55775589
55785590 let Predicates = [HasAVX512, HasVLX] in {
5579 defm Z256 : avx512_vptestSuffix>,
5591 defm Z256 : avx512_vptestNAME>,
55805592 avx512_vptest_mb, EVEX_V256;
5581 defm Z128 : avx512_vptestSuffix>,
5593 defm Z128 : avx512_vptestNAME>,
55825594 avx512_vptest_mb, EVEX_V128;
55835595 }
55845596 let Predicates = [HasAVX512, NoVLX] in {
5585 defm Z256_Alt : avx512_vptest_lowering< OpNode, _.info512, _.info256, Suffix>;
5586 defm Z128_Alt : avx512_vptest_lowering< OpNode, _.info512, _.info128, Suffix>;
5597 defm Z256_Alt : avx512_vptest_lowering< OpNode, _.info512, _.info256, NAME>;
5598 defm Z128_Alt : avx512_vptest_lowering< OpNode, _.info512, _.info128, NAME>;
55875599 }
55885600 }
55895601
55905602 multiclass avx512_vptest_dq opc, string OpcodeStr, PatFrag OpNode,
55915603 X86SchedWriteWidths sched> {
55925604 defm D : avx512_vptest_dq_sizes
5593 avx512vl_i32_info, "D">;
5605 avx512vl_i32_info>;
55945606 defm Q : avx512_vptest_dq_sizes
5595 avx512vl_i64_info, "Q">, VEX_W;
5607 avx512vl_i64_info>, VEX_W;
55965608 }
55975609
55985610 multiclass avx512_vptest_wb opc, string OpcodeStr,
55995611 PatFrag OpNode, X86SchedWriteWidths sched> {
56005612 let Predicates = [HasBWI] in {
56015613 defm WZ: avx512_vptest
5602 v32i16_info, "W">, EVEX_V512, VEX_W;
5614 v32i16_info, NAME#"W">, EVEX_V512, VEX_W;
56035615 defm BZ: avx512_vptest
5604 v64i8_info, "B">, EVEX_V512;
5616 v64i8_info, NAME#"B">, EVEX_V512;
56055617 }
56065618 let Predicates = [HasVLX, HasBWI] in {
56075619
56085620 defm WZ256: avx512_vptest
5609 v16i16x_info, "W">, EVEX_V256, VEX_W;
5621 v16i16x_info, NAME#"W">, EVEX_V256, VEX_W;
56105622 defm WZ128: avx512_vptest
5611 v8i16x_info, "W">, EVEX_V128, VEX_W;
5623 v8i16x_info, NAME#"W">, EVEX_V128, VEX_W;
56125624 defm BZ256: avx512_vptest
5613 v32i8x_info, "B">, EVEX_V256;
5625 v32i8x_info, NAME#"B">, EVEX_V256;
56145626 defm BZ128: avx512_vptest
5615 v16i8x_info, "B">, EVEX_V128;
5627 v16i8x_info, NAME#"B">, EVEX_V128;
56165628 }
56175629
56185630 let Predicates = [HasAVX512, NoVLX] in {
5619 defm BZ256_Alt : avx512_vptest_lowering;
5620 defm BZ128_Alt : avx512_vptest_lowering;
5621 defm WZ256_Alt : avx512_vptest_lowering;
5622 defm WZ128_Alt : avx512_vptest_lowering">;
5631 defm BZ256_Alt : avx512_vptest_lowering">;
5632 defm BZ128_Alt : avx512_vptest_lowering;
5633 defm WZ256_Alt : avx512_vptest_lowering;
5634 defm WZ128_Alt : avx512_vptest_lowering;
56235635 }
56245636 }
56255637
84138425 }
84148426
84158427 multiclass avx512_sqrt_scalar opc, string OpcodeStr, X86FoldableSchedWrite sched,
8416 X86VectorVTInfo _, string SUFF, Intrinsic Intr> {
8428 X86VectorVTInfo _, string Name, Intrinsic Intr> {
84178429 let ExeDomain = _.ExeDomain in {
84188430 defm r_Int : AVX512_maskable_scalar
84198431 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
84528464
84538465 let Predicates = [HasAVX512] in {
84548466 def : Pat<(_.EltVT (fsqrt _.FRC:$src)),
8455 (!cast(NAME#SUFF#Zr)
8467 (!cast(Name#Zr)
84568468 (_.EltVT (IMPLICIT_DEF)), _.FRC:$src)>;
84578469
84588470 def : Pat<(Intr VR128X:$src),
8459 (!cast(NAME#SUFF#Zr_Int) VR128X:$src,
8471 (!cast(Name#Zr_Int) VR128X:$src,
84608472 VR128X:$src)>;
84618473 }
84628474
84638475 let Predicates = [HasAVX512, OptForSize] in {
84648476 def : Pat<(_.EltVT (fsqrt (load addr:$src))),
8465 (!cast(NAME#SUFF#Zm)
8477 (!cast(Name#Zm)
84668478 (_.EltVT (IMPLICIT_DEF)), addr:$src)>;
84678479
84688480 def : Pat<(Intr _.ScalarIntMemCPat:$src2),
8469 (!cast(NAME#SUFF#Zm_Int)
8481 (!cast(Name#Zm_Int)
84708482 (_.VT (IMPLICIT_DEF)), addr:$src2)>;
84718483 }
84728484 }
84738485
84748486 multiclass avx512_sqrt_scalar_all opc, string OpcodeStr,
84758487 X86SchedWriteSizes sched> {
8476 defm SSZ : avx512_sqrt_scalar"SS",
8488 defm SSZ : avx512_sqrt_scalarNAME#"SS",
84778489 int_x86_sse_sqrt_ss>,
84788490 EVEX_CD8<32, CD8VT1>, EVEX_4V, XS, NotMemoryFoldable;
8479 defm SDZ : avx512_sqrt_scalar"SD",
8491 defm SDZ : avx512_sqrt_scalarNAME#"SD",
84808492 int_x86_sse2_sqrt_sd>,
84818493 EVEX_CD8<64, CD8VT1>, EVEX_4V, XD, VEX_W,
84828494 NotMemoryFoldable;
86388650
86398651 multiclass avx512_trunc_mr_lowering
86408652 X86VectorVTInfo DestInfo,
8641 PatFrag truncFrag, PatFrag mtruncFrag > {
8653 PatFrag truncFrag, PatFrag mtruncFrag,
8654 string Name> {
86428655
86438656 def : Pat<(truncFrag (SrcInfo.VT SrcInfo.RC:$src), addr:$dst),
8644 (!cast(NAME#SrcInfo.ZSuffix##mr)
8657 (!cast(Name#SrcInfo.ZSuffix##mr)
86458658 addr:$dst, SrcInfo.RC:$src)>;
86468659
86478660 def : Pat<(mtruncFrag addr:$dst, SrcInfo.KRCWM:$mask,
86488661 (SrcInfo.VT SrcInfo.RC:$src)),
8649 (!cast(NAME#SrcInfo.ZSuffix##mrk)
8662 (!cast(Name#SrcInfo.ZSuffix##mrk)
86508663 addr:$dst, SrcInfo.KRCWM:$mask, SrcInfo.RC:$src)>;
86518664 }
86528665
86638676 defm Z128: avx512_trunc_common
86648677 VTSrcInfo.info128, DestInfoZ128, x86memopZ128>,
86658678 avx512_trunc_mr_lowering
8666 truncFrag, mtruncFrag>, EVEX_V128;
8679 truncFrag, mtruncFrag, NAME>, EVEX_V128;
86678680
86688681 defm Z256: avx512_trunc_common
86698682 VTSrcInfo.info256, DestInfoZ256, x86memopZ256>,
86708683 avx512_trunc_mr_lowering
8671 truncFrag, mtruncFrag>, EVEX_V256;
8684 truncFrag, mtruncFrag, NAME>, EVEX_V256;
86728685 }
86738686 let Predicates = [prd] in
86748687 defm Z: avx512_trunc_common
86758688 VTSrcInfo.info512, DestInfoZ, x86memopZ>,
86768689 avx512_trunc_mr_lowering
8677 truncFrag, mtruncFrag>, EVEX_V512;
8690 truncFrag, mtruncFrag, NAME>, EVEX_V512;
86788691 }
86798692
86808693 multiclass avx512_trunc_qb opc, string OpcodeStr, SDNode OpNode,
92919304
92929305 // Use 512bit version to implement 128/256 bit in case NoVLX.
92939306 multiclass convert_vector_to_mask_lowering
9294 X86VectorVTInfo _> {
9307 X86VectorVTInfo _,
9308 string Name> {
92959309
92969310 def : Pat<(_.KVT (X86pcmpgtm _.ImmAllZerosV, (_.VT _.RC:$src))),
92979311 (_.KVT (COPY_TO_REGCLASS
9298 (!cast(NAME#"Zrr")
9312 (!cast(Name#"Zrr")
92999313 (INSERT_SUBREG (ExtendInfo.VT (IMPLICIT_DEF)),
93009314 _.RC:$src, _.SubRegIdx)),
93019315 _.KRC))>;
93149328 EVEX_V128;
93159329 }
93169330 let Predicates = [prd, NoVLX] in {
9317 defm Z256_Alt : convert_vector_to_mask_lowering;
9318 defm Z128_Alt : convert_vector_to_mask_lowering>;
9331 defm Z256_Alt : convert_vector_to_mask_lowering>;
9332 defm Z128_Alt : convert_vector_to_mask_lowering;
93199333 }
93209334 }
93219335
93649378 Sched<[sched.Folded]>;
93659379 }
93669380
9367 multiclass compress_by_vec_width_lowering > {
9381 multiclass compress_by_vec_width_lowering, string Name> {
93689382 def : Pat<(X86mCompressingStore addr:$dst, _.KRCWM:$mask,
93699383 (_.VT _.RC:$src)),
9370 (!cast(NAME#_.ZSuffix##mrk)
9384 (!cast(Name#_.ZSuffix##mrk)
93719385 addr:$dst, _.KRCWM:$mask, _.RC:$src)>;
93729386 }
93739387
93779391 Predicate Pred = HasAVX512> {
93789392 let Predicates = [Pred] in
93799393 defm Z : compress_by_vec_width_common,
9380 compress_by_vec_width_lowering>, EVEX_V512;
9394 compress_by_vec_width_lowering, NAME>, EVEX_V512;
93819395
93829396 let Predicates = [Pred, HasVLX] in {
93839397 defm Z256 : compress_by_vec_width_common,
9384 compress_by_vec_width_lowering>, EVEX_V256;
9398 compress_by_vec_width_lowering, NAME>, EVEX_V256;
93859399 defm Z128 : compress_by_vec_width_common,
9386 compress_by_vec_width_lowering>, EVEX_V128;
9400 compress_by_vec_width_lowering, NAME>, EVEX_V128;
93879401 }
93889402 }
93899403
94139427 Sched<[sched.Folded, ReadAfterLd]>;
94149428 }
94159429
9416 multiclass expand_by_vec_width_lowering > {
9430 multiclass expand_by_vec_width_lowering, string Name> {
94179431
94189432 def : Pat<(_.VT (X86mExpandingLoad addr:$src, _.KRCWM:$mask, undef)),
9419 (!cast(NAME#_.ZSuffix##rmkz)
9433 (!cast(Name#_.ZSuffix##rmkz)
94209434 _.KRCWM:$mask, addr:$src)>;
94219435
94229436 def : Pat<(_.VT (X86mExpandingLoad addr:$src, _.KRCWM:$mask, _.ImmAllZerosV)),
9423 (!cast(NAME#_.ZSuffix##rmkz)
9437 (!cast(Name#_.ZSuffix##rmkz)
94249438 _.KRCWM:$mask, addr:$src)>;
94259439
94269440 def : Pat<(_.VT (X86mExpandingLoad addr:$src, _.KRCWM:$mask,
94279441 (_.VT _.RC:$src0))),
9428 (!cast(NAME#_.ZSuffix##rmk)
9442 (!cast(Name#_.ZSuffix##rmk)
94299443 _.RC:$src0, _.KRCWM:$mask, addr:$src)>;
94309444 }
94319445
94359449 Predicate Pred = HasAVX512> {
94369450 let Predicates = [Pred] in
94379451 defm Z : expand_by_vec_width,
9438 expand_by_vec_width_lowering>, EVEX_V512;
9452 expand_by_vec_width_lowering, NAME>, EVEX_V512;
94399453
94409454 let Predicates = [Pred, HasVLX] in {
94419455 defm Z256 : expand_by_vec_width,
9442 expand_by_vec_width_lowering>, EVEX_V256;
9456 expand_by_vec_width_lowering, NAME>, EVEX_V256;
94439457 defm Z128 : expand_by_vec_width,
9444 expand_by_vec_width_lowering>, EVEX_V128;
9458 expand_by_vec_width_lowering, NAME>, EVEX_V128;
94459459 }
94469460 }
94479461
1058310597 }]>;
1058410598
1058510599 multiclass avx512_ternlog opc, string OpcodeStr, SDNode OpNode,
10586 X86FoldableSchedWrite sched, X86VectorVTInfo _>{
10600 X86FoldableSchedWrite sched, X86VectorVTInfo _,
10601 string Name>{
1058710602 let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain in {
1058810603 defm rri : AVX512_maskable_3src
1058910604 (ins _.RC:$src2, _.RC:$src3, u8imm:$src4),
1061810633 def : Pat<(_.VT (vselect _.KRCWM:$mask,
1061910634 (OpNode _.RC:$src3, _.RC:$src2, _.RC:$src1, (i8 imm:$src4)),
1062010635 _.RC:$src1)),
10621 (!cast(NAME#_.ZSuffix#rrik) _.RC:$src1, _.KRCWM:$mask,
10636 (!cast(Name#_.ZSuffix#rrik) _.RC:$src1, _.KRCWM:$mask,
1062210637 _.RC:$src2, _.RC:$src3, (VPTERNLOG321_imm8 imm:$src4))>;
1062310638 def : Pat<(_.VT (vselect _.KRCWM:$mask,
1062410639 (OpNode _.RC:$src2, _.RC:$src1, _.RC:$src3, (i8 imm:$src4)),
1062510640 _.RC:$src1)),
10626 (!cast(NAME#_.ZSuffix#rrik) _.RC:$src1, _.KRCWM:$mask,
10641 (!cast(Name#_.ZSuffix#rrik) _.RC:$src1, _.KRCWM:$mask,
1062710642 _.RC:$src2, _.RC:$src3, (VPTERNLOG213_imm8 imm:$src4))>;
1062810643
1062910644 // Additional patterns for matching loads in other positions.
1063010645 def : Pat<(_.VT (OpNode (bitconvert (_.LdFrag addr:$src3)),
1063110646 _.RC:$src2, _.RC:$src1, (i8 imm:$src4))),
10632 (!cast(NAME#_.ZSuffix#rmi) _.RC:$src1, _.RC:$src2,
10647 (!cast(Name#_.ZSuffix#rmi) _.RC:$src1, _.RC:$src2,
1063310648 addr:$src3, (VPTERNLOG321_imm8 imm:$src4))>;
1063410649 def : Pat<(_.VT (OpNode _.RC:$src1,
1063510650 (bitconvert (_.LdFrag addr:$src3)),
1063610651 _.RC:$src2, (i8 imm:$src4))),
10637 (!cast(NAME#_.ZSuffix#rmi) _.RC:$src1, _.RC:$src2,
10652 (!cast(Name#_.ZSuffix#rmi) _.RC:$src1, _.RC:$src2,
1063810653 addr:$src3, (VPTERNLOG132_imm8 imm:$src4))>;
1063910654
1064010655 // Additional patterns for matching zero masking with loads in other
1064310658 (OpNode (bitconvert (_.LdFrag addr:$src3)),
1064410659 _.RC:$src2, _.RC:$src1, (i8 imm:$src4)),
1064510660 _.ImmAllZerosV)),
10646 (!cast(NAME#_.ZSuffix#rmikz) _.RC:$src1, _.KRCWM:$mask,
10661 (!cast(Name#_.ZSuffix#rmikz) _.RC:$src1, _.KRCWM:$mask,
1064710662 _.RC:$src2, addr:$src3, (VPTERNLOG321_imm8 imm:$src4))>;
1064810663 def : Pat<(_.VT (vselect _.KRCWM:$mask,
1064910664 (OpNode _.RC:$src1, (bitconvert (_.LdFrag addr:$src3)),
1065010665 _.RC:$src2, (i8 imm:$src4)),
1065110666 _.ImmAllZerosV)),
10652 (!cast(NAME#_.ZSuffix#rmikz) _.RC:$src1, _.KRCWM:$mask,
10667 (!cast(Name#_.ZSuffix#rmikz) _.RC:$src1, _.KRCWM:$mask,
1065310668 _.RC:$src2, addr:$src3, (VPTERNLOG132_imm8 imm:$src4))>;
1065410669
1065510670 // Additional patterns for matching masked loads with different
1065810673 (OpNode _.RC:$src1, (bitconvert (_.LdFrag addr:$src3)),
1065910674 _.RC:$src2, (i8 imm:$src4)),
1066010675 _.RC:$src1)),
10661 (!cast(NAME#_.ZSuffix#rmik) _.RC:$src1, _.KRCWM:$mask,
10676 (!cast(Name#_.ZSuffix#rmik) _.RC:$src1, _.KRCWM:$mask,
1066210677 _.RC:$src2, addr:$src3, (VPTERNLOG132_imm8 imm:$src4))>;
1066310678 def : Pat<(_.VT (vselect _.KRCWM:$mask,
1066410679 (OpNode (bitconvert (_.LdFrag addr:$src3)),
1066510680 _.RC:$src2, _.RC:$src1, (i8 imm:$src4)),
1066610681 _.RC:$src1)),
10667 (!cast(NAME#_.ZSuffix#rmik) _.RC:$src1, _.KRCWM:$mask,
10682 (!cast(Name#_.ZSuffix#rmik) _.RC:$src1, _.KRCWM:$mask,
1066810683 _.RC:$src2, addr:$src3, (VPTERNLOG321_imm8 imm:$src4))>;
1066910684 def : Pat<(_.VT (vselect _.KRCWM:$mask,
1067010685 (OpNode _.RC:$src2, _.RC:$src1,
1067110686 (bitconvert (_.LdFrag addr:$src3)), (i8 imm:$src4)),
1067210687 _.RC:$src1)),
10673 (!cast(NAME#_.ZSuffix#rmik) _.RC:$src1, _.KRCWM:$mask,
10688 (!cast(Name#_.ZSuffix#rmik) _.RC:$src1, _.KRCWM:$mask,
1067410689 _.RC:$src2, addr:$src3, (VPTERNLOG213_imm8 imm:$src4))>;
1067510690 def : Pat<(_.VT (vselect _.KRCWM:$mask,
1067610691 (OpNode _.RC:$src2, (bitconvert (_.LdFrag addr:$src3)),
1067710692 _.RC:$src1, (i8 imm:$src4)),
1067810693 _.RC:$src1)),
10679 (!cast(NAME#_.ZSuffix#rmik) _.RC:$src1, _.KRCWM:$mask,
10694 (!cast(Name#_.ZSuffix#rmik) _.RC:$src1, _.KRCWM:$mask,
1068010695 _.RC:$src2, addr:$src3, (VPTERNLOG231_imm8 imm:$src4))>;
1068110696 def : Pat<(_.VT (vselect _.KRCWM:$mask,
1068210697 (OpNode (bitconvert (_.LdFrag addr:$src3)),
1068310698 _.RC:$src1, _.RC:$src2, (i8 imm:$src4)),
1068410699 _.RC:$src1)),
10685 (!cast(NAME#_.ZSuffix#rmik) _.RC:$src1, _.KRCWM:$mask,
10700 (!cast(Name#_.ZSuffix#rmik) _.RC:$src1, _.KRCWM:$mask,
1068610701 _.RC:$src2, addr:$src3, (VPTERNLOG312_imm8 imm:$src4))>;
1068710702
1068810703 // Additional patterns for matching broadcasts in other positions.
1068910704 def : Pat<(_.VT (OpNode (X86VBroadcast (_.ScalarLdFrag addr:$src3)),
1069010705 _.RC:$src2, _.RC:$src1, (i8 imm:$src4))),
10691 (!cast(NAME#_.ZSuffix#rmbi) _.RC:$src1, _.RC:$src2,
10706 (!cast(Name#_.ZSuffix#rmbi) _.RC:$src1, _.RC:$src2,
1069210707 addr:$src3, (VPTERNLOG321_imm8 imm:$src4))>;
1069310708 def : Pat<(_.VT (OpNode _.RC:$src1,
1069410709 (X86VBroadcast (_.ScalarLdFrag addr:$src3)),
1069510710 _.RC:$src2, (i8 imm:$src4))),
10696 (!cast(NAME#_.ZSuffix#rmbi) _.RC:$src1, _.RC:$src2,
10711 (!cast(Name#_.ZSuffix#rmbi) _.RC:$src1, _.RC:$src2,
1069710712 addr:$src3, (VPTERNLOG132_imm8 imm:$src4))>;
1069810713
1069910714 // Additional patterns for matching zero masking with broadcasts in other
1070210717 (OpNode (X86VBroadcast (_.ScalarLdFrag addr:$src3)),
1070310718 _.RC:$src2, _.RC:$src1, (i8 imm:$src4)),
1070410719 _.ImmAllZerosV)),
10705 (!cast(NAME#_.ZSuffix#rmbikz) _.RC:$src1,
10720 (!cast(Name#_.ZSuffix#rmbikz) _.RC:$src1,
1070610721 _.KRCWM:$mask, _.RC:$src2, addr:$src3,
1070710722 (VPTERNLOG321_imm8 imm:$src4))>;
1070810723 def : Pat<(_.VT (vselect _.KRCWM:$mask,
1071010725 (X86VBroadcast (_.ScalarLdFrag addr:$src3)),
1071110726 _.RC:$src2, (i8 imm:$src4)),
1071210727 _.ImmAllZerosV)),
10713 (!cast(NAME#_.ZSuffix#rmbikz) _.RC:$src1,
10728 (!cast(Name#_.ZSuffix#rmbikz) _.RC:$src1,
1071410729 _.KRCWM:$mask, _.RC:$src2, addr:$src3,
1071510730 (VPTERNLOG132_imm8 imm:$src4))>;
1071610731
1072110736 (X86VBroadcast (_.ScalarLdFrag addr:$src3)),
1072210737 _.RC:$src2, (i8 imm:$src4)),
1072310738 _.RC:$src1)),
10724 (!cast(NAME#_.ZSuffix#rmbik) _.RC:$src1, _.KRCWM:$mask,
10739 (!cast(Name#_.ZSuffix#rmbik) _.RC:$src1, _.KRCWM:$mask,
1072510740 _.RC:$src2, addr:$src3, (VPTERNLOG132_imm8 imm:$src4))>;
1072610741 def : Pat<(_.VT (vselect _.KRCWM:$mask,
1072710742 (OpNode (X86VBroadcast (_.ScalarLdFrag addr:$src3)),
1072810743 _.RC:$src2, _.RC:$src1, (i8 imm:$src4)),
1072910744 _.RC:$src1)),
10730 (!cast(NAME#_.ZSuffix#rmbik) _.RC:$src1, _.KRCWM:$mask,
10745 (!cast(Name#_.ZSuffix#rmbik) _.RC:$src1, _.KRCWM:$mask,
1073110746 _.RC:$src2, addr:$src3, (VPTERNLOG321_imm8 imm:$src4))>;
1073210747 def : Pat<(_.VT (vselect _.KRCWM:$mask,
1073310748 (OpNode _.RC:$src2, _.RC:$src1,
1073410749 (X86VBroadcast (_.ScalarLdFrag addr:$src3)),
1073510750 (i8 imm:$src4)), _.RC:$src1)),
10736 (!cast(NAME#_.ZSuffix#rmbik) _.RC:$src1, _.KRCWM:$mask,
10751 (!cast(Name#_.ZSuffix#rmbik) _.RC:$src1, _.KRCWM:$mask,
1073710752 _.RC:$src2, addr:$src3, (VPTERNLOG213_imm8 imm:$src4))>;
1073810753 def : Pat<(_.VT (vselect _.KRCWM:$mask,
1073910754 (OpNode _.RC:$src2,
1074010755 (X86VBroadcast (_.ScalarLdFrag addr:$src3)),
1074110756 _.RC:$src1, (i8 imm:$src4)),
1074210757 _.RC:$src1)),
10743 (!cast(NAME#_.ZSuffix#rmbik) _.RC:$src1, _.KRCWM:$mask,
10758 (!cast(Name#_.ZSuffix#rmbik) _.RC:$src1, _.KRCWM:$mask,
1074410759 _.RC:$src2, addr:$src3, (VPTERNLOG231_imm8 imm:$src4))>;
1074510760 def : Pat<(_.VT (vselect _.KRCWM:$mask,
1074610761 (OpNode (X86VBroadcast (_.ScalarLdFrag addr:$src3)),
1074710762 _.RC:$src1, _.RC:$src2, (i8 imm:$src4)),
1074810763 _.RC:$src1)),
10749 (!cast(NAME#_.ZSuffix#rmbik) _.RC:$src1, _.KRCWM:$mask,
10764 (!cast(Name#_.ZSuffix#rmbik) _.RC:$src1, _.KRCWM:$mask,
1075010765 _.RC:$src2, addr:$src3, (VPTERNLOG312_imm8 imm:$src4))>;
1075110766 }
1075210767
1075410769 AVX512VLVectorVTInfo _> {
1075510770 let Predicates = [HasAVX512] in
1075610771 defm Z : avx512_ternlog<0x25, OpcodeStr, X86vpternlog, sched.ZMM,
10757 _.info512>, EVEX_V512;
10772 _.info512, NAME>, EVEX_V512;
1075810773 let Predicates = [HasAVX512, HasVLX] in {
1075910774 defm Z128 : avx512_ternlog<0x25, OpcodeStr, X86vpternlog, sched.XMM,
10760 _.info128>, EVEX_V128;
10775 _.info128, NAME>, EVEX_V128;
1076110776 defm Z256 : avx512_ternlog<0x25, OpcodeStr, X86vpternlog, sched.YMM,
10762 _.info256>, EVEX_V256;
10777 _.info256, NAME>, EVEX_V256;
1076310778 }
1076410779 }
1076510780
27392739 Operand intmemop, ComplexPattern int_cpat,
27402740 Intrinsic Intr, SDNode OpNode, Domain d,
27412741 X86FoldableSchedWrite sched,
2742 Predicate target, string Suffix> {
2742 Predicate target> {
27432743 let hasSideEffects = 0 in {
27442744 def r : I
27452745 !strconcat(OpcodeStr, "\t{$src1, $dst|$dst, $src1}"),
27672767 // These are unary operations, but they are modeled as having 2 source operands
27682768 // because the high elements of the destination are unchanged in SSE.
27692769 def : Pat<(Intr VR128:$src),
2770 (!cast(NAME#Suffix##r_Int) VR128:$src, VR128:$src)>;
2770 (!cast(NAME#r_Int) VR128:$src, VR128:$src)>;
27712771 }
27722772 // We don't want to fold scalar loads into these instructions unless
27732773 // optimizing for size. This is because the folded instruction will have a
27782778 // rcpss mem, %xmm0
27792779 let Predicates = [target, OptForSize] in {
27802780 def : Pat<(Intr int_cpat:$src2),
2781 (!cast(NAME#Suffix##m_Int)
2781 (!cast(NAME#m_Int)
27822782 (vt (IMPLICIT_DEF)), addr:$src2)>;
27832783 }
27842784 }
27882788 X86MemOperand x86memop,
27892789 Operand intmemop, ComplexPattern int_cpat,
27902790 Intrinsic Intr, SDNode OpNode, Domain d,
2791 X86FoldableSchedWrite sched, Predicate target,
2792 string Suffix> {
2791 X86FoldableSchedWrite sched, Predicate target> {
27932792 let hasSideEffects = 0 in {
27942793 def r : I
27952794 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
28212820 // TODO: In theory, we could fold the load, and avoid the stall caused by
28222821 // the partial register store, either in BreakFalseDeps or with smarter RA.
28232822 let Predicates = [target] in {
2824 def : Pat<(OpNode RC:$src), (!cast("V"#NAME#Suffix##r)
2823 def : Pat<(OpNode RC:$src), (!cast(NAME#r)
28252824 (ScalarVT (IMPLICIT_DEF)), RC:$src)>;
28262825 def : Pat<(Intr VR128:$src),
2827 (!cast("V"#NAME#Suffix##r_Int) VR128:$src,
2826 (!cast(NAME#r_Int) VR128:$src,
28282827 VR128:$src)>;
28292828 }
28302829 let Predicates = [target, OptForSize] in {
28312830 def : Pat<(Intr int_cpat:$src2),
2832 (!cast("V"#NAME#Suffix##m_Int)
2831 (!cast(NAME#m_Int)
28332832 (vt (IMPLICIT_DEF)), addr:$src2)>;
28342833 def : Pat<(ScalarVT (OpNode (load addr:$src))),
2835 (!cast("V"#NAME#Suffix##m) (ScalarVT (IMPLICIT_DEF)),
2834 (!cast(NAME#m) (ScalarVT (IMPLICIT_DEF)),
28362835 addr:$src)>;
28372836 }
28382837 }
29142913 defm SS : sse_fp_unop_s
29152914 ssmem, sse_load_f32,
29162915 !cast("int_x86_sse_"##OpcodeStr##_ss), OpNode,
2917 SSEPackedSingle, sched.Scl, UseSSE1, "SS">, XS;
2916 SSEPackedSingle, sched.Scl, UseSSE1>, XS;
29182917 defm V#NAME#SS : avx_fp_unop_s
29192918 f32mem, ssmem, sse_load_f32,
29202919 !cast("int_x86_sse_"##OpcodeStr##_ss), OpNode,
2921 SSEPackedSingle, sched.Scl, AVXTarget, "SS">, XS, VEX_4V,
2920 SSEPackedSingle, sched.Scl, AVXTarget>, XS, VEX_4V,
29222921 VEX_LIG, VEX_WIG, NotMemoryFoldable;
29232922 }
29242923
29272926 defm SD : sse_fp_unop_s
29282927 sdmem, sse_load_f64,
29292928 !cast("int_x86_sse2_"##OpcodeStr##_sd),
2930 OpNode, SSEPackedDouble, sched.Scl, UseSSE2, "SD">, XD;
2929 OpNode, SSEPackedDouble, sched.Scl, UseSSE2>, XD;
29312930 defm V#NAME#SD : avx_fp_unop_s
29322931 f64mem, sdmem, sse_load_f64,
29332932 !cast("int_x86_sse2_"##OpcodeStr##_sd),
2934 OpNode, SSEPackedDouble, sched.Scl, AVXTarget, "SD">,
2933 OpNode, SSEPackedDouble, sched.Scl, AVXTarget>,
29352934 XD, VEX_4V, VEX_LIG, VEX_WIG, NotMemoryFoldable;
29362935 }
29372936
5959 // CHECK-NEXT: dag Dag1 = (somedef1 1);
6060 // CHECK-NEXT: dag Dag2 = (somedef1 2);
6161 // CHECK-NEXT: dag Dag3 = (somedef1 2);
62 // CHECK-NEXT: NAME = ?
6362 // CHECK-NEXT: }
6463
6564
6867 // CHECK-NEXT: dag Dag1 = (somedef1 1);
6968 // CHECK-NEXT: dag Dag2 = (somedef2 2);
7069 // CHECK-NEXT: dag Dag3 = (somedef2 2);
71 // CHECK-NEXT: NAME = ?
7270 // CHECK-NEXT: }
7371
7472 def VAL5 : bar {
4242 def ZFizz#s : C;
4343 }
4444
45 defm : MC3<"Buzz">;
45 defm "" : MC3<"Buzz">;
4646
4747 // CHECK: def ZFizzBuzz
4848 // CHECK: string name = "Buzz";
44 // CHECK-NEXT: string element = "Jeffrey Sinclair";
55 // CHECK-NEXT: list rest = [];
66 // CHECK-NEXT: int null = 1;
7 // CHECK-NEXT: string NAME = ?;
87 // CHECK-NEXT: }
98 // CHECK-NEXT: def Three {
109 // CHECK-NEXT: list names = ["Tom", "Dick", "Harry"];
1110 // CHECK-NEXT: string element = "Tom";
1211 // CHECK-NEXT: list rest = ["Dick", "Harry"];
1312 // CHECK-NEXT: int null = 0;
14 // CHECK-NEXT: string NAME = ?;
1513 // CHECK-NEXT: }
1614
1715 class List n> {
0 // RUN: llvm-tblgen %s | FileCheck %s
11 // XFAIL: vg_leak
2
3 // This test demonstrates a number of inconsistencies in how NAME is resolved
4 // and record names are constructed.
5 //
6 // The TODO lines describe a suggested consistent behavior that would result
7 // from:
8 // (1) Treating NAME as an implicit multiclass template argument and
9 // (2) always storing the name of (non-anonymous) prototype records in
10 // multiclasses with at least one explicit reference to NAME.
11 //
12 // Unfortunately, several backends (including X86) rely quite heavily on the
13 // current inconsistent behavior and would have to be fixed.
142
153 // CHECK: def B0a {
164 // CHECK: string e = "B0";
175 // CHECK: }
186
197 // CHECK: def B0ba {
20 // TODO: expect "B0b" here
21 // CHECK: string a = "B0";
8 // CHECK: string a = "B0b";
229 // CHECK: string b = "B0";
2310 // CHECK: }
2411
12 // CHECK: def B0bys {
13 // CHECK: string f = "B0b";
14 // CHECK: string g = "B0";
15 // CHECK: }
16
2517 // CHECK: def B0cza {
26 // TODO: expect "B0cz" here
27 // CHECK: string a = "B0";
18 // CHECK: string a = "B0cz";
2819 // CHECK: string b = "B0";
2920 // CHECK: }
3021
31 // TODO: expect this to be named 'xB0b'
32 // CHECK: def B0xb {
33 // TODO: expect "B0b" here
34 // CHECK: string c = "b";
35 // CHECK: string d = "b";
22 // CHECK: def B0czyt {
23 // CHECK: string f = "B0cz";
24 // CHECK: string g = "B0";
3625 // CHECK: }
3726
38 // TODO: expect this to be named B0bys
39 // CHECK: def B0ys {
40 // TODO: expect "B0b" here
41 // CHECK: string f = "b";
42 // CHECK: string g = "b";
27 // CHECK: def C0 {
28 // CHECK: string a = "C0";
29 // CHECK: string b = "C0";
30 // CHECK: string c = "a";
31 // CHECK: }
32
33 // CHECK: def D0a {
34 // CHECK: string a = "D0a";
35 // CHECK: string b = "D0a";
36 // CHECK: string c = "D0";
37 // CHECK: }
38
39 // CHECK: def D0b {
40 // CHECK: string a = "D0b";
41 // CHECK: string b = "D0b";
42 // CHECK: string c = "a";
43 // CHECK: }
44
45 // CHECK: def xB0b {
46 // CHECK: string c = "B0b";
47 // CHECK: string d = "B0";
4348 // CHECK: }
4449
4550 // CHECK: def xB0cz {
4651 // CHECK: string c = "B0cz";
47 // CHECK: string d = "B0cz";
48 // CHECK: }
49
50 // TODO: expect this to be named B0czyt
51 // CHECK: def yt {
52 // CHECK: string f = "B0cz";
53 // CHECK: string g = "B0cz";
52 // CHECK: string d = "B0";
5453 // CHECK: }
5554
5655 multiclass A {
8180 }
8281
8382 defm B0 : B<"z", "t">;
83
84 class Cbase {
85 string a = NAME;
86 }
87
88 class C : Cbase {
89 string b = NAME;
90 string c = arg;
91 }
92
93 def C0 : C<"a">;
94
95 multiclass D {
96 def a : C;
97 def b : C;
98 }
99
100 defm D0 : D<"a">;
2727 // CHECK-NEXT: class AName {
2828 // CHECK-NEXT: string name = !subst("FIRST", "John", !subst("LAST", "Smith", AName:name));
2929 // CHECK-NEXT: Honorific honorific = !subst(TVAR, Mr, AName:honorific);
30 // CHECK-NEXT: string NAME = ?;
3130 // CHECK-NEXT: }
3231 // CHECK-NEXT: class Honorific {
3332 // CHECK-NEXT: string honorific = Honorific:t;
34 // CHECK-NEXT: string NAME = ?;
3533 // CHECK-NEXT: }
3634 // CHECK-NEXT: class Name {
3735 // CHECK-NEXT: string name = Name:n;
3836 // CHECK-NEXT: Honorific honorific = Name:t;
39 // CHECK-NEXT: string NAME = ?;
4037 // CHECK-NEXT: }
4138 // CHECK-NEXT: ------------- Defs -----------------
4239 // CHECK-NEXT: def JaneSmith {
4340 // CHECK-NEXT: string name = "Jane Smith";
4441 // CHECK-NEXT: Honorific honorific = Ms;
45 // CHECK-NEXT: string NAME = ?;
4642 // CHECK-NEXT: }
4743 // CHECK-NEXT: def JimmyJohnson {
4844 // CHECK-NEXT: string name = "Jimmy Johnson";
4945 // CHECK-NEXT: Honorific honorific = Mr;
50 // CHECK-NEXT: string NAME = ?;
5146 // CHECK-NEXT: }
5247 // CHECK-NEXT: def JohnSmith {
5348 // CHECK-NEXT: string name = "John Smith";
5449 // CHECK-NEXT: Honorific honorific = Mr;
55 // CHECK-NEXT: string NAME = ?;
5650 // CHECK-NEXT: }
5751 // CHECK-NEXT: def JohnSmithJones {
5852 // CHECK-NEXT: string name = "John Smith-Jones";
5953 // CHECK-NEXT: Honorific honorific = Mr;
60 // CHECK-NEXT: string NAME = ?;
6154 // CHECK-NEXT: }
6255 // CHECK-NEXT: def Mr
6356 // CHECK-NEXT: string honorific = "Mr.";
64 // CHECK-NEXT: string NAME = ?;
6557 // CHECK-NEXT: }
6658 // CHECK-NEXT: def Mrs {
6759 // CHECK-NEXT: string honorific = "Mrs.";
68 // CHECK-NEXT: string NAME = ?;
6960 // CHECK-NEXT: }
7061 // CHECK-NEXT: def Ms {
7162 // CHECK-NEXT: string honorific = "Ms.";
72 // CHECK-NEXT: string NAME = ?;
7363 // CHECK-NEXT: }
7464 // CHECK-NEXT: def TVAR {
7565 // CHECK-NEXT: string honorific = "Bogus";
76 // CHECK-NEXT: string NAME = ?;
7766 // CHECK-NEXT: }