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[mips] Split mem_msa into range checked mem_simm10 and mem_simm10_lsl[123] Summary: Also, made test_mi10.s formatting consistent with the majority of the MC tests. Reviewers: vkalintiris Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D18435 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265014 91177308-0d34-0410-b5e6-96231b3b80d8 Daniel Sanders 4 years ago
7 changed file(s) with 138 addition(s) and 115 deletion(s). Raw diff Collapse all Expand all
10541054 bool isConstantMemOff() const {
10551055 return isMem() && isa(getMemOff());
10561056 }
1057 template bool isMemWithSimmOffset() const {
1058 return isMem() && isConstantMemOff() && isInt(getConstantMemOff())
1059 && getMemBase()->isGPRAsmReg();
1057 template
1058 bool isMemWithSimmOffset() const {
1059 return isMem() && isConstantMemOff() &&
1060 isShiftedInt(getConstantMemOff()) &&
1061 getMemBase()->isGPRAsmReg();
10601062 }
10611063 template bool isMemWithSimmOffsetGPR() const {
10621064 return isMem() && isConstantMemOff() && isInt(getConstantMemOff()) &&
37993801 case Match_MemGPSImm9:
38003802 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
38013803 "expected memory with $gp and 9-bit signed offset");
3804 case Match_MemSImm10:
3805 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
3806 "expected memory with 10-bit signed offset");
3807 case Match_MemSImm10Lsl1:
3808 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
3809 "expected memory with 11-bit signed offset and multiple of 2");
3810 case Match_MemSImm10Lsl2:
3811 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
3812 "expected memory with 12-bit signed offset and multiple of 4");
3813 case Match_MemSImm10Lsl3:
3814 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
3815 "expected memory with 13-bit signed offset and multiple of 8");
38023816 }
38033817
38043818 llvm_unreachable("Implement any new match types added!");
652652 return getExprOpValue(MO.getExpr(),Fixups, STI);
653653 }
654654
655 /// getMSAMemEncoding - Return binary encoding of memory operand for LD/ST
656 /// instructions.
657 unsigned
658 MipsMCCodeEmitter::getMSAMemEncoding(const MCInst &MI, unsigned OpNo,
659 SmallVectorImpl &Fixups,
660 const MCSubtargetInfo &STI) const {
655 /// Return binary encoding of memory related operand.
656 /// If the offset operand requires relocation, record the relocation.
657 template
658 unsigned MipsMCCodeEmitter::getMemEncoding(const MCInst &MI, unsigned OpNo,
659 SmallVectorImpl &Fixups,
660 const MCSubtargetInfo &STI) const {
661661 // Base register is encoded in bits 20-16, offset is encoded in bits 15-0.
662662 assert(MI.getOperand(OpNo).isReg());
663663 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),Fixups, STI) << 16;
664664 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
665665
666 // The immediate field of an LD/ST instruction is scaled which means it must
667 // be divided (when encoding) by the size (in bytes) of the instructions'
668 // data format.
669 // .b - 1 byte
670 // .h - 2 bytes
671 // .w - 4 bytes
672 // .d - 8 bytes
673 switch(MI.getOpcode())
674 {
675 default:
676 assert (0 && "Unexpected instruction");
677 break;
678 case Mips::LD_B:
679 case Mips::ST_B:
680 // We don't need to scale the offset in this case
681 break;
682 case Mips::LD_H:
683 case Mips::ST_H:
684 OffBits >>= 1;
685 break;
686 case Mips::LD_W:
687 case Mips::ST_W:
688 OffBits >>= 2;
689 break;
690 case Mips::LD_D:
691 case Mips::ST_D:
692 OffBits >>= 3;
693 break;
694 }
695
696 return (OffBits & 0xFFFF) | RegBits;
697 }
698
699 /// getMemEncoding - Return binary encoding of memory related operand.
700 /// If the offset operand requires relocation, record the relocation.
701 unsigned
702 MipsMCCodeEmitter::getMemEncoding(const MCInst &MI, unsigned OpNo,
703 SmallVectorImpl &Fixups,
704 const MCSubtargetInfo &STI) const {
705 // Base register is encoded in bits 20-16, offset is encoded in bits 15-0.
706 assert(MI.getOperand(OpNo).isReg());
707 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),Fixups, STI) << 16;
708 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
666 // Apply the scale factor if there is one.
667 OffBits >>= ShiftAmount;
709668
710669 return (OffBits & 0xFFFF) | RegBits;
711670 }
160160 SmallVectorImpl &Fixups,
161161 const MCSubtargetInfo &STI) const;
162162
163 template
163164 unsigned getMemEncoding(const MCInst &MI, unsigned OpNo,
164165 SmallVectorImpl &Fixups,
165166 const MCSubtargetInfo &STI) const;
464464 }
465465 def UImm16AsmOperandClass
466466 : UImmAsmOperandClass<16, [UImm16RelaxedAsmOperandClass]>;
467 def ConstantSImm10Lsl3AsmOperandClass : AsmOperandClass {
468 let Name = "SImm10Lsl3";
469 let RenderMethod = "addImmOperands";
470 let PredicateMethod = "isScaledSImm<10, 3>";
471 let SuperClasses = [UImm16AsmOperandClass];
472 let DiagnosticType = "SImm10_Lsl3";
473 }
474 def ConstantSImm10Lsl2AsmOperandClass : AsmOperandClass {
475 let Name = "SImm10Lsl2";
476 let RenderMethod = "addImmOperands";
477 let PredicateMethod = "isScaledSImm<10, 2>";
478 let SuperClasses = [ConstantSImm10Lsl3AsmOperandClass];
479 let DiagnosticType = "SImm10_Lsl2";
480 }
481 def ConstantSImm10Lsl1AsmOperandClass : AsmOperandClass {
482 let Name = "SImm10Lsl1";
483 let RenderMethod = "addImmOperands";
484 let PredicateMethod = "isScaledSImm<10, 1>";
485 let SuperClasses = [ConstantSImm10Lsl2AsmOperandClass];
486 let DiagnosticType = "SImm10_Lsl1";
487 }
467488 def ConstantUImm10AsmOperandClass
468 : ConstantUImmAsmOperandClass<10, [UImm16AsmOperandClass]>;
489 : ConstantUImmAsmOperandClass<10, [ConstantSImm10Lsl1AsmOperandClass]>;
469490 def ConstantSImm10AsmOperandClass
470491 : ConstantSImmAsmOperandClass<10, [ConstantUImm10AsmOperandClass]>;
471492 def ConstantSImm9AsmOperandClass
576597
577598 def imm64: Operand;
578599
579 def simm10 : Operand;
580600 def simm11 : Operand;
581601
582602 def simm16 : Operand {
742762 }
743763
744764 // Signed operands
745 foreach I = {4, 5, 6, 9} in
765 foreach I = {4, 5, 6, 9, 10} in
746766 def simm # I : Operand {
747767 let DecoderMethod = "DecodeSImmWithOffsetAndScale<" # I # ">";
748768 let ParserMatchClass =
749769 !cast("ConstantSImm" # I # "AsmOperandClass");
770 }
771
772 foreach I = {1, 2, 3} in
773 def simm10_lsl # I : Operand {
774 let DecoderMethod = "DecodeSImmWithOffsetAndScale<10, " # I # ">";
775 let ParserMatchClass =
776 !cast("ConstantSImm10Lsl" # I # "AsmOperandClass");
750777 }
751778
752779 foreach I = {10} in
792819 let DiagnosticType = "MemSImm9";
793820 }
794821
822 def MipsMemSimm10AsmOperand : AsmOperandClass {
823 let Name = "MemOffsetSimm10";
824 let SuperClasses = [MipsMemAsmOperand];
825 let RenderMethod = "addMemOperands";
826 let ParserMethod = "parseMemOperand";
827 let PredicateMethod = "isMemWithSimmOffset<10>";
828 let DiagnosticType = "MemSImm10";
829 }
830
831 foreach I = {1, 2, 3} in
832 def MipsMemSimm10Lsl # I # AsmOperand : AsmOperandClass {
833 let Name = "MemOffsetSimm10_" # I;
834 let SuperClasses = [MipsMemAsmOperand];
835 let RenderMethod = "addMemOperands";
836 let ParserMethod = "parseMemOperand";
837 let PredicateMethod = "isMemWithSimmOffset<10, " # I # ">";
838 let DiagnosticType = "MemSImm10Lsl" # I;
839 }
840
795841 def MipsMemSimm9GPRAsmOperand : AsmOperandClass {
796842 let Name = "MemOffsetSimm9GPR";
797843 let SuperClasses = [MipsMemAsmOperand];
853899 let EncoderMethod = "getMemEncoding";
854900 let ParserMatchClass = MipsMemSimm9AsmOperand;
855901 }
902
903 def mem_simm10 : mem_generic {
904 let MIOperandInfo = (ops ptr_rc, simm10);
905 let EncoderMethod = "getMemEncoding";
906 let ParserMatchClass = MipsMemSimm10AsmOperand;
907 }
908
909 foreach I = {1, 2, 3} in
910 def mem_simm10_lsl # I : mem_generic {
911 let MIOperandInfo = (ops ptr_rc, !cast("simm10_lsl" # I));
912 let EncoderMethod = "getMemEncoding<" # I # ">";
913 let ParserMatchClass =
914 !cast("MipsMemSimm10Lsl" # I # "AsmOperand");
915 }
856916
857917 def mem_simm9gpr : mem_generic {
858918 let MIOperandInfo = (ops ptr_rc, simm9);
22962296
22972297 class LD_DESC_BASE
22982298 ValueType TyNode, RegisterOperand ROWD,
2299 Operand MemOpnd = mem_msa, ComplexPattern Addr = addrimm10,
2299 Operand MemOpnd, ComplexPattern Addr = addrimm10,
23002300 InstrItinClass itin = NoItinerary> {
23012301 dag OutOperandList = (outs ROWD:$wd);
23022302 dag InOperandList = (ins MemOpnd:$addr);
23062306 string DecoderMethod = "DecodeMSA128Mem";
23072307 }
23082308
2309 class LD_B_DESC : LD_DESC_BASE<"ld.b", load, v16i8, MSA128BOpnd>;
2310 class LD_H_DESC : LD_DESC_BASE<"ld.h", load, v8i16, MSA128HOpnd>;
2311 class LD_W_DESC : LD_DESC_BASE<"ld.w", load, v4i32, MSA128WOpnd>;
2312 class LD_D_DESC : LD_DESC_BASE<"ld.d", load, v2i64, MSA128DOpnd>;
2309 class LD_B_DESC : LD_DESC_BASE<"ld.b", load, v16i8, MSA128BOpnd, mem_simm10>;
2310 class LD_H_DESC : LD_DESC_BASE<"ld.h", load, v8i16, MSA128HOpnd, mem_simm10_lsl1>;
2311 class LD_W_DESC : LD_DESC_BASE<"ld.w", load, v4i32, MSA128WOpnd, mem_simm10_lsl2>;
2312 class LD_D_DESC : LD_DESC_BASE<"ld.d", load, v2i64, MSA128DOpnd, mem_simm10_lsl3>;
23132313
23142314 class LDI_B_DESC : MSA_I10_LDI_DESC_BASE<"ldi.b", MSA128BOpnd>;
23152315 class LDI_H_DESC : MSA_I10_LDI_DESC_BASE<"ldi.h", MSA128HOpnd>;
26302630
26312631 class ST_DESC_BASE
26322632 ValueType TyNode, RegisterOperand ROWD,
2633 Operand MemOpnd = mem_msa, ComplexPattern Addr = addrimm10,
2633 Operand MemOpnd, ComplexPattern Addr = addrimm10,
26342634 InstrItinClass itin = NoItinerary> {
26352635 dag OutOperandList = (outs);
26362636 dag InOperandList = (ins ROWD:$wd, MemOpnd:$addr);
26402640 string DecoderMethod = "DecodeMSA128Mem";
26412641 }
26422642
2643 class ST_B_DESC : ST_DESC_BASE<"st.b", store, v16i8, MSA128BOpnd>;
2644 class ST_H_DESC : ST_DESC_BASE<"st.h", store, v8i16, MSA128HOpnd>;
2645 class ST_W_DESC : ST_DESC_BASE<"st.w", store, v4i32, MSA128WOpnd>;
2646 class ST_D_DESC : ST_DESC_BASE<"st.d", store, v2i64, MSA128DOpnd>;
2643 class ST_B_DESC : ST_DESC_BASE<"st.b", store, v16i8, MSA128BOpnd, mem_simm10>;
2644 class ST_H_DESC : ST_DESC_BASE<"st.h", store, v8i16, MSA128HOpnd, mem_simm10_lsl1>;
2645 class ST_W_DESC : ST_DESC_BASE<"st.w", store, v4i32, MSA128WOpnd, mem_simm10_lsl2>;
2646 class ST_D_DESC : ST_DESC_BASE<"st.d", store, v2i64, MSA128DOpnd, mem_simm10_lsl3>;
26472647
26482648 class SUBS_S_B_DESC : MSA_3R_DESC_BASE<"subs_s.b", int_mips_subs_s_b,
26492649 MSA128BOpnd>;
134134 insve.h $w24[2], $w2[1] # CHECK: :[[@LINE]]:26: error: expected '0'
135135 insve.w $w0[2], $w13[1] # CHECK: :[[@LINE]]:26: error: expected '0'
136136 insve.d $w3[0], $w18[1] # CHECK: :[[@LINE]]:26: error: expected '0'
137 ld.b $w0, -513($2) # CHECK: :[[@LINE]]:15: error: expected memory with 10-bit signed offset
138 ld.b $w0, 512($2) # CHECK: :[[@LINE]]:15: error: expected memory with 10-bit signed offset
139 ld.h $w0, -1025($2) # CHECK: :[[@LINE]]:15: error: expected memory with 11-bit signed offset and multiple of 2
140 ld.h $w0, 1024($2) # CHECK: :[[@LINE]]:15: error: expected memory with 11-bit signed offset and multiple of 2
141 ld.w $w0, -2049($2) # CHECK: :[[@LINE]]:15: error: expected memory with 12-bit signed offset and multiple of 4
142 ld.w $w0, 2048($2) # CHECK: :[[@LINE]]:15: error: expected memory with 12-bit signed offset and multiple of 4
143 ld.d $w0, -4097($2) # CHECK: :[[@LINE]]:15: error: expected memory with 13-bit signed offset and multiple of 8
144 ld.d $w0, 4096($2) # CHECK: :[[@LINE]]:15: error: expected memory with 13-bit signed offset and multiple of 8
137145 ldi.b $w1, -1025 # CHECK: :[[@LINE]]:16: error: expected 10-bit signed immediate
138146 ldi.b $w1, 1024 # CHECK: :[[@LINE]]:16: error: expected 10-bit signed immediate
139147 ldi.h $w1, -1025 # CHECK: :[[@LINE]]:16: error: expected 10-bit signed immediate
258266 srlri.w $w18, $w3, 32 # CHECK: :[[@LINE]]:24: error: expected 5-bit unsigned immediate
259267 srlri.d $w18, $w3, -1 # CHECK: :[[@LINE]]:24: error: expected 6-bit unsigned immediate
260268 srlri.d $w18, $w3, 64 # CHECK: :[[@LINE]]:24: error: expected 6-bit unsigned immediate
269 st.b $w0, -513($2) # CHECK: :[[@LINE]]:15: error: expected memory with 10-bit signed offset
270 st.b $w0, 512($2) # CHECK: :[[@LINE]]:15: error: expected memory with 10-bit signed offset
271 st.h $w0, -1025($2) # CHECK: :[[@LINE]]:15: error: expected memory with 11-bit signed offset and multiple of 2
272 st.h $w0, 1024($2) # CHECK: :[[@LINE]]:15: error: expected memory with 11-bit signed offset and multiple of 2
273 st.w $w0, -2049($2) # CHECK: :[[@LINE]]:15: error: expected memory with 12-bit signed offset and multiple of 4
274 st.w $w0, 2048($2) # CHECK: :[[@LINE]]:15: error: expected memory with 12-bit signed offset and multiple of 4
275 st.d $w0, -4097($2) # CHECK: :[[@LINE]]:15: error: expected memory with 13-bit signed offset and multiple of 8
276 st.d $w0, 4096($2) # CHECK: :[[@LINE]]:15: error: expected memory with 13-bit signed offset and multiple of 8
261277 subvi.b $w1, $w2, -1 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate
262278 subvi.b $w1, $w2, 32 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate
263279 subvi.h $w1, $w2, -1 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate
0 # RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -mattr=+msa -show-encoding | FileCheck %s
11 #
2 # CHECK: ld.b $w0, -512($1) # encoding: [0x7a,0x00,0x08,0x20]
3 # CHECK: ld.b $w1, 0($2) # encoding: [0x78,0x00,0x10,0x60]
4 # CHECK: ld.b $w2, 511($3) # encoding: [0x79,0xff,0x18,0xa0]
2 ld.b $w0, -512($1) # CHECK: ld.b $w0, -512($1) # encoding: [0x7a,0x00,0x08,0x20]
3 ld.b $w1, 0($2) # CHECK: ld.b $w1, 0($2) # encoding: [0x78,0x00,0x10,0x60]
4 ld.b $w2, 511($3) # CHECK: ld.b $w2, 511($3) # encoding: [0x79,0xff,0x18,0xa0]
55
6 # CHECK: ld.h $w3, -1024($4) # encoding: [0x7a,0x00,0x20,0xe1]
7 # CHECK: ld.h $w4, -512($5) # encoding: [0x7b,0x00,0x29,0x21]
8 # CHECK: ld.h $w5, 0($6) # encoding: [0x78,0x00,0x31,0x61]
9 # CHECK: ld.h $w6, 512($7) # encoding: [0x79,0x00,0x39,0xa1]
10 # CHECK: ld.h $w7, 1022($8) # encoding: [0x79,0xff,0x41,0xe1]
6 ld.h $w3, -1024($4) # CHECK: ld.h $w3, -1024($4) # encoding: [0x7a,0x00,0x20,0xe1]
7 ld.h $w4, -512($5) # CHECK: ld.h $w4, -512($5) # encoding: [0x7b,0x00,0x29,0x21]
8 ld.h $w5, 0($6) # CHECK: ld.h $w5, 0($6) # encoding: [0x78,0x00,0x31,0x61]
9 ld.h $w6, 512($7) # CHECK: ld.h $w6, 512($7) # encoding: [0x79,0x00,0x39,0xa1]
10 ld.h $w7, 1022($8) # CHECK: ld.h $w7, 1022($8) # encoding: [0x79,0xff,0x41,0xe1]
1111
12 # CHECK: ld.w $w8, -2048($9) # encoding: [0x7a,0x00,0x4a,0x22]
13 # CHECK: ld.w $w9, -1024($10) # encoding: [0x7b,0x00,0x52,0x62]
14 # CHECK: ld.w $w10, -512($11) # encoding: [0x7b,0x80,0x5a,0xa2]
15 # CHECK: ld.w $w11, 512($12) # encoding: [0x78,0x80,0x62,0xe2]
16 # CHECK: ld.w $w12, 1024($13) # encoding: [0x79,0x00,0x6b,0x22]
17 # CHECK: ld.w $w13, 2044($14) # encoding: [0x79,0xff,0x73,0x62]
12 ld.w $w8, -2048($9) # CHECK: ld.w $w8, -2048($9) # encoding: [0x7a,0x00,0x4a,0x22]
13 ld.w $w9, -1024($10) # CHECK: ld.w $w9, -1024($10) # encoding: [0x7b,0x00,0x52,0x62]
14 ld.w $w10, -512($11) # CHECK: ld.w $w10, -512($11) # encoding: [0x7b,0x80,0x5a,0xa2]
15 ld.w $w11, 512($12) # CHECK: ld.w $w11, 512($12) # encoding: [0x78,0x80,0x62,0xe2]
16 ld.w $w12, 1024($13) # CHECK: ld.w $w12, 1024($13) # encoding: [0x79,0x00,0x6b,0x22]
17 ld.w $w13, 2044($14) # CHECK: ld.w $w13, 2044($14) # encoding: [0x79,0xff,0x73,0x62]
1818
19 # CHECK: ld.d $w14, -4096($15) # encoding: [0x7a,0x00,0x7b,0xa3]
20 # CHECK: ld.d $w15, -2048($16) # encoding: [0x7b,0x00,0x83,0xe3]
21 # CHECK: ld.d $w16, -1024($17) # encoding: [0x7b,0x80,0x8c,0x23]
22 # CHECK: ld.d $w17, -512($18) # encoding: [0x7b,0xc0,0x94,0x63]
23 # CHECK: ld.d $w18, 0($19) # encoding: [0x78,0x00,0x9c,0xa3]
24 # CHECK: ld.d $w19, 512($20) # encoding: [0x78,0x40,0xa4,0xe3]
25 # CHECK: ld.d $w20, 1024($21) # encoding: [0x78,0x80,0xad,0x23]
26 # CHECK: ld.d $w21, 2048($22) # encoding: [0x79,0x00,0xb5,0x63]
27 # CHECK: ld.d $w22, 4088($23) # encoding: [0x79,0xff,0xbd,0xa3]
28
29 ld.b $w0, -512($1)
30 ld.b $w1, 0($2)
31 ld.b $w2, 511($3)
32
33 ld.h $w3, -1024($4)
34 ld.h $w4, -512($5)
35 ld.h $w5, 0($6)
36 ld.h $w6, 512($7)
37 ld.h $w7, 1022($8)
38
39 ld.w $w8, -2048($9)
40 ld.w $w9, -1024($10)
41 ld.w $w10, -512($11)
42 ld.w $w11, 512($12)
43 ld.w $w12, 1024($13)
44 ld.w $w13, 2044($14)
45
46 ld.d $w14, -4096($15)
47 ld.d $w15, -2048($16)
48 ld.d $w16, -1024($17)
49 ld.d $w17, -512($18)
50 ld.d $w18, 0($19)
51 ld.d $w19, 512($20)
52 ld.d $w20, 1024($21)
53 ld.d $w21, 2048($22)
54 ld.d $w22, 4088($23)
19 ld.d $w14, -4096($15) # CHECK: ld.d $w14, -4096($15) # encoding: [0x7a,0x00,0x7b,0xa3]
20 ld.d $w15, -2048($16) # CHECK: ld.d $w15, -2048($16) # encoding: [0x7b,0x00,0x83,0xe3]
21 ld.d $w16, -1024($17) # CHECK: ld.d $w16, -1024($17) # encoding: [0x7b,0x80,0x8c,0x23]
22 ld.d $w17, -512($18) # CHECK: ld.d $w17, -512($18) # encoding: [0x7b,0xc0,0x94,0x63]
23 ld.d $w18, 0($19) # CHECK: ld.d $w18, 0($19) # encoding: [0x78,0x00,0x9c,0xa3]
24 ld.d $w19, 512($20) # CHECK: ld.d $w19, 512($20) # encoding: [0x78,0x40,0xa4,0xe3]
25 ld.d $w20, 1024($21) # CHECK: ld.d $w20, 1024($21) # encoding: [0x78,0x80,0xad,0x23]
26 ld.d $w21, 2048($22) # CHECK: ld.d $w21, 2048($22) # encoding: [0x79,0x00,0xb5,0x63]
27 ld.d $w22, 4088($23) # CHECK: ld.d $w22, 4088($23) # encoding: [0x79,0xff,0xbd,0xa3]