llvm.org GIT mirror llvm / 2673179
Merging r342884: ------------------------------------------------------------------------ r342884 | petarj | 2018-09-24 07:14:19 -0700 (Mon, 24 Sep 2018) | 12 lines [Mips][FastISel] Fix selectBranch on icmp i1 The r337288 tried to fix result of icmp i1 when its input is not sanitized by falling back to DagISel. While it now produces the correct result for bit 0, the other bits can still hold arbitrary value which is not supported by MipsFastISel branch lowering. This patch fixes the issue by falling back to DagISel in this case. Patch by Dragan Mladjenovic. Differential Revision: https://reviews.llvm.org/D52045 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_70@346741 91177308-0d34-0410-b5e6-96231b3b80d8 Tom Stellard 1 year, 11 months ago
2 changed file(s) with 194 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
952952 MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
953953 // For now, just try the simplest case where it's fed by a compare.
954954 if (const CmpInst *CI = dyn_cast(BI->getCondition())) {
955 MVT CIMVT =
956 TLI.getValueType(DL, CI->getOperand(0)->getType(), true).getSimpleVT();
957 if (CIMVT == MVT::i1)
958 return false;
959
955960 unsigned CondReg = getRegForValue(CI);
956961 BuildMI(*BrBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::BGTZ))
957962 .addReg(CondReg)
0 ; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel=true -mcpu=mips32r2 \
1 ; RUN: < %s -verify-machineinstrs | FileCheck %s
2
3 define void @testeq(i32, i32) {
4 ; CHECK-LABEL: testeq:
5 ; CHECK: andi $[[REG0:[0-9]+]], $4, 1
6 ; CHECK: andi $[[REG1:[0-9]+]], $5, 1
7 ; CHECK: beq $[[REG0]], $[[REG1]],
8 %3 = trunc i32 %0 to i1
9 %4 = trunc i32 %1 to i1
10 %5 = icmp eq i1 %3, %4
11 br i1 %5, label %end, label %trap
12 trap:
13 call void @llvm.trap()
14 br label %end
15 end:
16 ret void
17 }
18
19
20 define void @testne(i32, i32) {
21 ; CHECK-LABEL: testne:
22 ; CHECK: andi $[[REG0:[0-9]+]], $4, 1
23 ; CHECK: andi $[[REG1:[0-9]+]], $5, 1
24 ; CHECK: bne $[[REG0]], $[[REG1]],
25 %3 = trunc i32 %0 to i1
26 %4 = trunc i32 %1 to i1
27 %5 = icmp ne i1 %3, %4
28 br i1 %5, label %end, label %trap
29 trap:
30 call void @llvm.trap()
31 br label %end
32 end:
33 ret void
34 }
35
36
37 define void @testugt(i32, i32) {
38 ; CHECK-LABEL: testugt:
39 ; CHECK: andi $[[REG0:[0-9]+]], $4, 1
40 ; CHECK: andi $[[REG1:[0-9]+]], $5, 1
41 ; CHECK: sltu $[[REG2:[0-9]+]], $[[REG1]], $[[REG0]]
42 ; CHECK: bnez $[[REG2]],
43 %3 = trunc i32 %0 to i1
44 %4 = trunc i32 %1 to i1
45 %5 = icmp ugt i1 %3, %4
46 br i1 %5, label %end, label %trap
47 trap:
48 call void @llvm.trap()
49 br label %end
50 end:
51 ret void
52 }
53
54
55 define void @testuge(i32, i32) {
56 ; CHECK-LABEL: testuge:
57 ; CHECK: andi $[[REG0:[0-9]+]], $4, 1
58 ; CHECK: andi $[[REG1:[0-9]+]], $5, 1
59 ; CHECK: sltu $[[REG2:[0-9]+]], $[[REG0]], $[[REG1]]
60 ; CHECK: beqz $[[REG2]],
61 %3 = trunc i32 %0 to i1
62 %4 = trunc i32 %1 to i1
63 %5 = icmp uge i1 %3, %4
64 br i1 %5, label %end, label %trap
65 trap:
66 call void @llvm.trap()
67 br label %end
68 end:
69 ret void
70 }
71
72
73 define void @testult(i32, i32) {
74 ; CHECK-LABEL: testult:
75 ; CHECK: andi $[[REG0:[0-9]+]], $4, 1
76 ; CHECK: andi $[[REG1:[0-9]+]], $5, 1
77 ; CHECK: sltu $[[REG2:[0-9]+]], $[[REG0]], $[[REG1]]
78 ; CHECK: bnez $[[REG2]],
79 %3 = trunc i32 %0 to i1
80 %4 = trunc i32 %1 to i1
81 %5 = icmp ult i1 %3, %4
82 br i1 %5, label %end, label %trap
83 trap:
84 call void @llvm.trap()
85 br label %end
86 end:
87 ret void
88 }
89
90
91 define void @testule(i32, i32) {
92 ; CHECK: andi $[[REG0:[0-9]+]], $4, 1
93 ; CHECK: andi $[[REG1:[0-9]+]], $5, 1
94 ; CHECK: sltu $[[REG2:[0-9]+]], $[[REG1]], $[[REG0]]
95 ; CHECK: beqz $[[REG2]],
96 %3 = trunc i32 %0 to i1
97 %4 = trunc i32 %1 to i1
98 %5 = icmp ule i1 %3, %4
99 br i1 %5, label %end, label %trap
100 trap:
101 call void @llvm.trap()
102 br label %end
103 end:
104 ret void
105 }
106
107
108 define void @testsgt(i32, i32) {
109 ; CHECK-LABEL: testsgt:
110 ; CHECK: andi $[[REG0:[0-9]+]], $4, 1
111 ; CHECK: negu $[[REG0]], $[[REG0]]
112 ; CHECK: andi $[[REG1:[0-9]+]], $5, 1
113 ; CHECK: negu $[[REG1]], $[[REG1]]
114 ; CHECK: slt $[[REG2:[0-9]+]], $[[REG1]], $[[REG0]]
115 ; CHECK: bnez $[[REG2]],
116 %3 = trunc i32 %0 to i1
117 %4 = trunc i32 %1 to i1
118 %5 = icmp sgt i1 %3, %4
119 br i1 %5, label %end, label %trap
120 trap:
121 call void @llvm.trap()
122 br label %end
123 end:
124 ret void
125 }
126
127
128 define void @testsge(i32, i32) {
129 ; CHECK-LABEL: testsge:
130 ; CHECK: andi $[[REG0:[0-9]+]], $4, 1
131 ; CHECK: negu $[[REG0]], $[[REG0]]
132 ; CHECK: andi $[[REG1:[0-9]+]], $5, 1
133 ; CHECK: negu $[[REG1]], $[[REG1]]
134 ; CHECK: slt $[[REG2:[0-9]+]], $[[REG0]], $[[REG1]]
135 ; CHECK: beqz $[[REG2]],
136 %3 = trunc i32 %0 to i1
137 %4 = trunc i32 %1 to i1
138 %5 = icmp sge i1 %3, %4
139 br i1 %5, label %end, label %trap
140 trap:
141 call void @llvm.trap()
142 br label %end
143 end:
144 ret void
145 }
146
147
148 define void @testslt(i32, i32) {
149 ; CHECK-LABEL: testslt:
150 ; CHECK: andi $[[REG0:[0-9]+]], $4, 1
151 ; CHECK: negu $[[REG0]], $[[REG0]]
152 ; CHECK: andi $[[REG1:[0-9]+]], $5, 1
153 ; CHECK: negu $[[REG1]], $[[REG1]]
154 ; CHECK: slt $[[REG2:[0-9]+]], $[[REG0]], $[[REG1]]
155 ; CHECK: bnez $[[REG2]],
156 %3 = trunc i32 %0 to i1
157 %4 = trunc i32 %1 to i1
158 %5 = icmp slt i1 %3, %4
159 br i1 %5, label %end, label %trap
160 trap:
161 call void @llvm.trap()
162 br label %end
163 end:
164 ret void
165 }
166
167
168 define void @testsle(i32, i32) {
169 ; CHECK-LABEL: testsle:
170 ; CHECK: andi $[[REG0:[0-9]+]], $4, 1
171 ; CHECK: negu $[[REG0]], $[[REG0]]
172 ; CHECK: andi $[[REG1:[0-9]+]], $5, 1
173 ; CHECK: negu $[[REG1]], $[[REG1]]
174 ; CHECK: slt $[[REG2:[0-9]+]], $[[REG1]], $[[REG0]]
175 ; CHECK: beqz $[[REG2]],
176 %3 = trunc i32 %0 to i1
177 %4 = trunc i32 %1 to i1
178 %5 = icmp sle i1 %3, %4
179 br i1 %5, label %end, label %trap
180 trap:
181 call void @llvm.trap()
182 br label %end
183 end:
184 ret void
185 }
186
187
188 declare void @llvm.trap()