llvm.org GIT mirror llvm / 2637dc9
McARM: Make ARMOperand use a union where appropriate. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123744 91177308-0d34-0410-b5e6-96231b3b80d8 Daniel Dunbar 9 years ago
1 changed file(s) with 13 addition(s) and 9 deletion(s). Raw diff Collapse all Expand all
144144 /// Combined record for all forms of ARM address expressions.
145145 struct {
146146 unsigned BaseRegNum;
147 unsigned OffsetRegNum; // used when OffsetIsReg is true
148 const MCExpr *Offset; // used when OffsetIsReg is false
147 union {
148 unsigned RegNum; ///< Offset register num, when OffsetIsReg.
149 const MCExpr *Value; ///< Offset value, when !OffsetIsReg.
150 } Offset;
149151 const MCExpr *ShiftAmount; // used when OffsetRegShifted is true
150152 enum ShiftType ShiftType; // used when OffsetRegShifted is true
151153 unsigned OffsetRegShifted : 1; // only used when OffsetIsReg is true
233235 Mem.Writeback || Mem.Negative)
234236 return false;
235237
236 const MCConstantExpr *CE = dyn_cast(Mem.Offset);
238 const MCConstantExpr *CE = dyn_cast(Mem.Offset.Value);
237239 if (!CE) return false;
238240
239241 // The offset must be a multiple of 4 in the range 0-1020.
249251 if (!isMemory() || Mem.OffsetIsReg || Mem.Writeback)
250252 return false;
251253
252 const MCConstantExpr *CE = dyn_cast(Mem.Offset);
254 const MCConstantExpr *CE = dyn_cast(Mem.Offset.Value);
253255 if (!CE) return false;
254256
255257 // The offset must be a multiple of 4 in the range 0-124.
313315
314316 // FIXME: #-0 is encoded differently than #0. Does the parser preserve
315317 // the difference?
316 const MCConstantExpr *CE = dyn_cast(Mem.Offset);
318 const MCConstantExpr *CE = dyn_cast(Mem.Offset.Value);
317319 assert(CE && "Non-constant mode 5 offset operand!");
318320
319321 // The MCInst offset operand doesn't include the low two bits (like
330332 void addMemModeRegThumbOperands(MCInst &Inst, unsigned N) const {
331333 assert(N == 2 && isMemModeRegThumb() && "Invalid number of operands!");
332334 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
333 Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
335 Inst.addOperand(MCOperand::CreateReg(Mem.Offset.RegNum));
334336 }
335337
336338 void addMemModeImmThumbOperands(MCInst &Inst, unsigned N) const {
337339 assert(N == 2 && isMemModeImmThumb() && "Invalid number of operands!");
338340 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
339 const MCConstantExpr *CE = dyn_cast(Mem.Offset);
341 const MCConstantExpr *CE = dyn_cast(Mem.Offset.Value);
340342 assert(CE && "Non-constant mode offset operand!");
341343 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
342344 }
424426 ARMOperand *Op = new ARMOperand(Memory);
425427 Op->Mem.BaseRegNum = BaseRegNum;
426428 Op->Mem.OffsetIsReg = OffsetIsReg;
427 Op->Mem.Offset = Offset;
428 Op->Mem.OffsetRegNum = OffsetRegNum;
429 if (OffsetIsReg)
430 Op->Mem.Offset.RegNum = OffsetRegNum;
431 else
432 Op->Mem.Offset.Value = Offset;
429433 Op->Mem.OffsetRegShifted = OffsetRegShifted;
430434 Op->Mem.ShiftType = ShiftType;
431435 Op->Mem.ShiftAmount = ShiftAmount;