llvm.org GIT mirror llvm / 2626e5e
[llvm-exegesis] Allow the target to disable the selection of some registers. Summary: This prevents "Cannot encode high byte register in REX-prefixed instruction" from happening on instructions that require REX encoding when AH & co get selected. On the down side, these 4 registers can no longer be selected automatically, but this avoids having to expose all the X86 encoding complexity. Reviewers: gchatelet Subscribers: tschuett, jdoerfert, llvm-commits, bdb Tags: #llvm Differential Revision: https://reviews.llvm.org/D59821 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357003 91177308-0d34-0410-b5e6-96231b3b80d8 Clement Courbet 1 year, 8 months ago
5 changed file(s) with 38 addition(s) and 2 deletion(s). Raw diff Collapse all Expand all
0 # RUN: llvm-exegesis -mode=latency -opcode-name=SBB8rr | FileCheck %s
1
2 CHECK: ---
3 CHECK-NEXT: mode: latency
4 CHECK-NEXT: key:
5 CHECK-NEXT: instructions:
6 CHECK-NEXT: SBB8rr
7 CHECK-NEXT: config: ''
8 CHECK-NEXT: register_initial_values:
9 CHECK-DAG: - '[[REG1:[A-Z0-9]+]]=0x0'
10 CHECK-LAST: ...
3737 }
3838 PfmCounters = &TheExegesisTarget->getPfmCounters(CpuName);
3939
40 RATC.reset(new RegisterAliasingTrackerCache(
41 getRegInfo(), getFunctionReservedRegs(getTargetMachine())));
40 BitVector ReservedRegs = getFunctionReservedRegs(getTargetMachine());
41 for (const unsigned Reg : TheExegesisTarget->getUnavailableRegisters())
42 ReservedRegs.set(Reg);
43 RATC.reset(
44 new RegisterAliasingTrackerCache(getRegInfo(), std::move(ReservedRegs)));
4245 IC.reset(new InstructionsCache(getInstrInfo(), getRATC()));
4346 }
4447
8989 "fillMemoryOperands() requires getScratchMemoryRegister() > 0");
9090 }
9191
92 // Returns a list of unavailable registers.
93 // Targets can use this to prevent some registers to be automatically selected
94 // for use in snippets.
95 virtual ArrayRef getUnavailableRegisters() const { return {}; }
96
9297 // Returns the maximum number of bytes a load/store instruction can access at
9398 // once. This is typically the size of the largest register available on the
9499 // processor. Note that this only used as a hint to generate independant
434434 unsigned Reg,
435435 const llvm::APInt &Value) const override;
436436
437 ArrayRef getUnavailableRegisters() const override {
438 return makeArrayRef(kUnavailableRegisters,
439 sizeof(kUnavailableRegisters) /
440 sizeof(kUnavailableRegisters[0]));
441 }
442
437443 std::unique_ptr
438444 createLatencySnippetGenerator(const LLVMState &State) const override {
439445 return llvm::make_unique(State);
447453 bool matchesArch(llvm::Triple::ArchType Arch) const override {
448454 return Arch == llvm::Triple::x86_64 || Arch == llvm::Triple::x86;
449455 }
456
457 static const unsigned kUnavailableRegisters[4];
450458 };
459
460 // We disable a few registers that cannot be encoded on instructions with a REX
461 // prefix.
462 const unsigned ExegesisX86Target::kUnavailableRegisters[4] = {X86::AH, X86::BH,
463 X86::CH, X86::DH};
451464 } // namespace
452465
453466 void ExegesisX86Target::addTargetSpecificPasses(
142142 public:
143143 Core2Avx512TargetTest() : X86TargetTest("+avx512vl") {}
144144 };
145
146 TEST_F(Core2TargetTest, NoHighByteRegs) {
147 EXPECT_TRUE(State.getRATC().reservedRegisters().test(X86::AH));
148 }
145149
146150 TEST_F(Core2TargetTest, SetFlags) {
147151 const unsigned Reg = llvm::X86::EFLAGS;