llvm.org GIT mirror llvm / 26160f4
When generating spill and reload code for vector registers on PowerPC, the compiler makes use of GPR0. However, there are two flavors of GPR0 defined by the target: the 32-bit GPR0 (R0) and the 64-bit GPR0 (X0). The spill/reload code makes use of R0 regardless of whether we are generating 32- or 64-bit code. This patch corrects the problem in the obvious manner, using X0 and ADDI8 for 64-bit and R0 and ADDI for 32-bit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165658 91177308-0d34-0410-b5e6-96231b3b80d8 Bill Schmidt 7 years ago
2 changed file(s) with 31 addition(s) and 6 deletion(s). Raw diff Collapse all Expand all
569569 // STVX VAL, 0, R0
570570 //
571571 // FIXME: We use R0 here, because it isn't available for RA.
572 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::ADDI), PPC::R0),
572 bool Is64Bit = TM.getSubtargetImpl()->isPPC64();
573 unsigned Instr = Is64Bit ? PPC::ADDI8 : PPC::ADDI;
574 unsigned GPR0 = Is64Bit ? PPC::X0 : PPC::R0;
575 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(Instr), GPR0),
573576 FrameIdx, 0, 0));
574577 NewMIs.push_back(BuildMI(MF, DL, get(PPC::STVX))
575578 .addReg(SrcReg, getKillRegState(isKill))
576 .addReg(PPC::R0)
577 .addReg(PPC::R0));
579 .addReg(GPR0)
580 .addReg(GPR0));
578581 } else {
579582 llvm_unreachable("Unknown regclass!");
580583 }
706709 // Dest = LVX 0, R0
707710 //
708711 // FIXME: We use R0 here, because it isn't available for RA.
709 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::ADDI), PPC::R0),
712 bool Is64Bit = TM.getSubtargetImpl()->isPPC64();
713 unsigned Instr = Is64Bit ? PPC::ADDI8 : PPC::ADDI;
714 unsigned GPR0 = Is64Bit ? PPC::X0 : PPC::R0;
715 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(Instr), GPR0),
710716 FrameIdx, 0, 0));
711 NewMIs.push_back(BuildMI(MF, DL, get(PPC::LVX),DestReg).addReg(PPC::R0)
712 .addReg(PPC::R0));
717 NewMIs.push_back(BuildMI(MF, DL, get(PPC::LVX),DestReg).addReg(GPR0)
718 .addReg(GPR0));
713719 } else {
714720 llvm_unreachable("Unknown regclass!");
715721 }
0 ; RUN: llc -O0 -mtriple=powerpc-unknown-linux-gnu -verify-machineinstrs < %s | FileCheck %s
1 ; RUN: llc -O0 -mtriple=powerpc64-unknown-linux-gnu -verify-machineinstrs < %s | FileCheck %s
2
3 ; This verifies that we generate correct spill/reload code for vector regs.
4
5 define void @addrtaken(i32 %i, <4 x float> %w) nounwind {
6 entry:
7 %i.addr = alloca i32, align 4
8 %w.addr = alloca <4 x float>, align 16
9 store i32 %i, i32* %i.addr, align 4
10 store <4 x float> %w, <4 x float>* %w.addr, align 16
11 call void @foo(i32* %i.addr)
12 ret void
13 }
14
15 ; CHECK: stvx 2, 0, 0
16 ; CHECK: lvx 2, 0, 0
17
18 declare void @foo(i32*)