llvm.org GIT mirror llvm / 26012ce
AArch64: remove unnecessary pseudo-instruction. Sufficiently twisted use of TableGen lets us write patterns directly for f16 (as an i16 promoted to i32) -> f32 conversion. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212933 91177308-0d34-0410-b5e6-96231b3b80d8 Tim Northover 6 years ago
3 changed file(s) with 5 addition(s) and 17 deletion(s). Raw diff Collapse all Expand all
633633 return true;
634634 }
635635
636 case AArch64::FCVTSHpseudo: {
637 MachineOperand Src = MI.getOperand(1);
638 Src.setImplicit();
639 unsigned SrcH =
640 TII->getRegisterInfo().getSubReg(Src.getReg(), AArch64::hsub);
641 auto MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::FCVTSHr))
642 .addOperand(MI.getOperand(0))
643 .addReg(SrcH, RegState::Undef)
644 .addOperand(Src);
645 transferImpOps(MI, MIB, MIB);
646 MI.eraseFromParent();
647 return true;
648 }
649636 case AArch64::LOADgot: {
650637 // Expand into ADRP + LDR.
651638 unsigned DstReg = MI.getOperand(0).getReg();
22382238 (f32 (SUBREG_TO_REG (i32 0), (FCVTHSr FPR32:$Rn), hsub)),
22392239 GPR32))>;
22402240
2241 def FCVTSHpseudo : Pseudo<(outs FPR32:$Rd), (ins FPR32:$Rn),
2242 [(set (f32 FPR32:$Rd), (f16_to_f32 i32:$Rn))]>;
2241 def : Pat<(f32 (f16_to_f32 i32:$Rn)),
2242 (FCVTSHr (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS i32:$Rn, FPR32)),
2243 hsub))>;
22432244
22442245 // When converting from f16 coming directly from a load, make sure we
22452246 // load into the FPR16 registers rather than going through the GPRs.
7171
7272 define float @from_half(i16 %in) {
7373 ; CHECK-LABEL: from_half:
74 ; CHECK: fmov s[[HALFVAL:[0-9]+]], {{w[0-9]+}}
75 ; CHECK: fcvt s0, h[[HALFVAL]]
74 ; CHECK: fmov {{s[0-9]+}}, {{w[0-9]+}}
75 ; CHECK: fcvt s0, {{h[0-9]+}}
7676 %res = call float @llvm.convert.from.fp16(i16 %in)
7777 ret float %res
7878 }