llvm.org GIT mirror llvm / 25d437f
[C++11] Use 'nullptr' in tablegen output files. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207611 91177308-0d34-0410-b5e6-96231b3b80d8 Craig Topper 6 years ago
3 changed file(s) with 11 addition(s) and 11 deletion(s). Raw diff Collapse all Expand all
522522 // Emit the implicit uses and defs lists...
523523 std::vector UseList = Inst.TheDef->getValueAsListOfDefs("Uses");
524524 if (UseList.empty())
525 OS << "NULL, ";
525 OS << "nullptr, ";
526526 else
527527 OS << "ImplicitList" << EmittedLists[UseList] << ", ";
528528
529529 std::vector DefList = Inst.TheDef->getValueAsListOfDefs("Defs");
530530 if (DefList.empty())
531 OS << "NULL, ";
531 OS << "nullptr, ";
532532 else
533533 OS << "ImplicitList" << EmittedLists[DefList] << ", ";
534534
535535 // Emit the operand info.
536536 std::vector OperandInfo = GetOperandInfo(Inst);
537537 if (OperandInfo.empty())
538 OS << "0";
538 OS << "nullptr";
539539 else
540540 OS << "OperandInfo" << OpInfo.find(OperandInfo)->second;
541541
547547 else if (!Inst.DeprecatedReason.empty())
548548 // Emit the Subtarget feature.
549549 OS << "," << Target.getInstNamespace() << "::" << Inst.DeprecatedReason
550 << ",0";
550 << ",nullptr";
551551 else
552552 // Instruction isn't deprecated.
553 OS << ",0,0";
553 OS << ",0,nullptr";
554554
555555 OS << " }, // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n";
556556 }
224224 for (unsigned i = 0; i < NumSets; ++i ) {
225225 OS << " \"" << RegBank.getRegSetAt(i).Name << "\",\n";
226226 }
227 OS << " 0 };\n"
227 OS << " nullptr };\n"
228228 << " return PressureNameTable[Idx];\n"
229229 << "}\n\n";
230230
10671067 // Now that all of the structs have been emitted, emit the instances.
10681068 if (!RegisterClasses.empty()) {
10691069 OS << "\nstatic const TargetRegisterClass *const "
1070 << "NullRegClasses[] = { NULL };\n\n";
1070 << "NullRegClasses[] = { nullptr };\n\n";
10711071
10721072 // Emit register class bit mask tables. The first bit mask emitted for a
10731073 // register class, RC, is the set of sub-classes, including RC itself.
11341134 << RC.getName() << "Superclasses[] = {\n";
11351135 for (unsigned i = 0; i != Supers.size(); ++i)
11361136 OS << " &" << Supers[i]->getQualifiedName() << "RegClass,\n";
1137 OS << " NULL\n};\n\n";
1137 OS << " nullptr\n};\n\n";
11381138 }
11391139
11401140 // Emit methods.
11881188 else
11891189 OS << RC.getName() << "Superclasses,\n ";
11901190 if (RC.AltOrderSelect.empty())
1191 OS << "0\n";
1191 OS << "nullptr\n";
11921192 else
11931193 OS << RC.getName() << "GetRawAllocationOrder\n";
11941194 OS << " };\n\n";
12571257 << " if (!Idx) return RC;\n --Idx;\n"
12581258 << " assert(Idx < " << SubRegIndices.size() << " && \"Bad subreg\");\n"
12591259 << " unsigned TV = Table[RC->getID()][Idx];\n"
1260 << " return TV ? getRegClass(TV - 1) : 0;\n}\n\n";
1260 << " return TV ? getRegClass(TV - 1) : nullptr;\n}\n\n";
12611261 }
12621262
12631263 EmitRegUnitPressure(OS, RegBank, ClassName);
577577 OS << "\n";
578578 OS << "static const llvm::InstrItinerary ";
579579 if (ItinList.empty()) {
580 OS << '*' << Name << " = 0;\n";
580 OS << '*' << Name << " = nullptr;\n";
581581 continue;
582582 }
583583