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Use #NAME# to have the CMOV multiclass define things with the same names as before (e.g. CMOVBE16rr instead of CMOVBErr16). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115705 91177308-0d34-0410-b5e6-96231b3b80d8 Chris Lattner 10 years ago
4 changed file(s) with 46 addition(s) and 43 deletion(s). Raw diff Collapse all Expand all
15371537 case X86::CMOVB16rr: case X86::CMOVB16rm:
15381538 case X86::CMOVB32rr: case X86::CMOVB32rm:
15391539 case X86::CMOVB64rr: case X86::CMOVB64rm:
1540 case X86::CMOVBErr16: case X86::CMOVBErm16:
1541 case X86::CMOVBErr32: case X86::CMOVBErm32:
1542 case X86::CMOVBErr64: case X86::CMOVBErm64:
1540 case X86::CMOVBE16rr: case X86::CMOVBE16rm:
1541 case X86::CMOVBE32rr: case X86::CMOVBE32rm:
1542 case X86::CMOVBE64rr: case X86::CMOVBE64rm:
15431543 case X86::CMOVE16rr: case X86::CMOVE16rm:
15441544 case X86::CMOVE32rr: case X86::CMOVE32rm:
15451545 case X86::CMOVE64rr: case X86::CMOVE64rm:
1616 multiclass CMOV opc, string Mnemonic, PatLeaf CondNode> {
1717 let Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst",
1818 isCommutable = 1 in {
19 def rr16 : I
20 !strconcat(Mnemonic, "{w}\t{$src2, $dst|$dst, $src2}"),
21 [(set GR16:$dst,
22 (X86cmov GR16:$src1, GR16:$src2, CondNode, EFLAGS))]>,
23 TB, OpSize;
24 def rr32 : I
25 !strconcat(Mnemonic, "{l}\t{$src2, $dst|$dst, $src2}"),
26 [(set GR32:$dst,
27 (X86cmov GR32:$src1, GR32:$src2, CondNode, EFLAGS))]>,
28 TB;
29 def rr64 :RI
30 !strconcat(Mnemonic, "{q}\t{$src2, $dst|$dst, $src2}"),
31 [(set GR64:$dst,
32 (X86cmov GR64:$src1, GR64:$src2, CondNode, EFLAGS))]>,
33 TB;
19 def #NAME#16rr
20 : I
21 !strconcat(Mnemonic, "{w}\t{$src2, $dst|$dst, $src2}"),
22 [(set GR16:$dst,
23 (X86cmov GR16:$src1, GR16:$src2, CondNode, EFLAGS))]>,TB,OpSize;
24 def #NAME#32rr
25 : I
26 !strconcat(Mnemonic, "{l}\t{$src2, $dst|$dst, $src2}"),
27 [(set GR32:$dst,
28 (X86cmov GR32:$src1, GR32:$src2, CondNode, EFLAGS))]>, TB;
29 def #NAME#64rr
30 :RI
31 !strconcat(Mnemonic, "{q}\t{$src2, $dst|$dst, $src2}"),
32 [(set GR64:$dst,
33 (X86cmov GR64:$src1, GR64:$src2, CondNode, EFLAGS))]>, TB;
3434 }
3535
3636 let Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst"in {
37 def rm16 : I
38 !strconcat(Mnemonic, "{w}\t{$src2, $dst|$dst, $src2}"),
39 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
40 CondNode, EFLAGS))]>, TB, OpSize;
41 def rm32 : I
42 !strconcat(Mnemonic, "{l}\t{$src2, $dst|$dst, $src2}"),
43 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
44 CondNode, EFLAGS))]>, TB;
45 def rm64 :RI
46 !strconcat(Mnemonic, "{q}\t{$src2, $dst|$dst, $src2}"),
47 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
48 CondNode, EFLAGS))]>, TB;
37 def #NAME#16rm
38 : I
39 !strconcat(Mnemonic, "{w}\t{$src2, $dst|$dst, $src2}"),
40 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
41 CondNode, EFLAGS))]>, TB, OpSize;
42 def #NAME#32rm
43 : I
44 !strconcat(Mnemonic, "{l}\t{$src2, $dst|$dst, $src2}"),
45 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
46 CondNode, EFLAGS))]>, TB;
47 def #NAME#64rm
48 :RI
49 !strconcat(Mnemonic, "{q}\t{$src2, $dst|$dst, $src2}"),
50 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
51 CondNode, EFLAGS))]>, TB;
4952 } // Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst"
5053 } // end multiclass
5154
864864 defm : CMOVmr;
865865 defm : CMOVmr;
866866 defm : CMOVmr;
867 defm : CMOVmrrm16, CMOVBErm32, CMOVBErm64>;
867 defm : CMOVmr16rm, CMOVBE32rm, CMOVBE64rm>;
868868 defm : CMOVmr;
869869 defm : CMOVmr;
870870 defm : CMOVmr;
481481 { X86::CMOVB16rr, X86::CMOVB16rm, 0 },
482482 { X86::CMOVB32rr, X86::CMOVB32rm, 0 },
483483 { X86::CMOVB64rr, X86::CMOVB64rm, 0 },
484 { X86::CMOVBErr16, X86::CMOVBErm16, 0 },
485 { X86::CMOVBErr32, X86::CMOVBErm32, 0 },
486 { X86::CMOVBErr64, X86::CMOVBErm64, 0 },
484 { X86::CMOVBE16rr, X86::CMOVBE16rm, 0 },
485 { X86::CMOVBE32rr, X86::CMOVBE32rm, 0 },
486 { X86::CMOVBE64rr, X86::CMOVBE64rm, 0 },
487487 { X86::CMOVE16rr, X86::CMOVE16rm, 0 },
488488 { X86::CMOVE32rr, X86::CMOVE32rm, 0 },
489489 { X86::CMOVE64rr, X86::CMOVE64rm, 0 },
14441444 case X86::CMOVNE16rr:
14451445 case X86::CMOVNE32rr:
14461446 case X86::CMOVNE64rr:
1447 case X86::CMOVBErr16:
1448 case X86::CMOVBErr32:
1449 case X86::CMOVBErr64:
1447 case X86::CMOVBE16rr:
1448 case X86::CMOVBE32rr:
1449 case X86::CMOVBE64rr:
14501450 case X86::CMOVA16rr:
14511451 case X86::CMOVA32rr:
14521452 case X86::CMOVA64rr:
14951495 case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
14961496 case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
14971497 case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
1498 case X86::CMOVBErr16: Opc = X86::CMOVA16rr; break;
1499 case X86::CMOVBErr32: Opc = X86::CMOVA32rr; break;
1500 case X86::CMOVBErr64: Opc = X86::CMOVA64rr; break;
1501 case X86::CMOVA16rr: Opc = X86::CMOVBErr16; break;
1502 case X86::CMOVA32rr: Opc = X86::CMOVBErr32; break;
1503 case X86::CMOVA64rr: Opc = X86::CMOVBErr64; break;
1498 case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
1499 case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
1500 case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
1501 case X86::CMOVA16rr: Opc = X86::CMOVBE16rr; break;
1502 case X86::CMOVA32rr: Opc = X86::CMOVBE32rr; break;
1503 case X86::CMOVA64rr: Opc = X86::CMOVBE64rr; break;
15041504 case X86::CMOVL16rr: Opc = X86::CMOVGE16rr; break;
15051505 case X86::CMOVL32rr: Opc = X86::CMOVGE32rr; break;
15061506 case X86::CMOVL64rr: Opc = X86::CMOVGE64rr; break;