llvm.org GIT mirror llvm / 2527d91
[ARM] Add MVE vector bit-operations (register inputs). This includes all the obvious bitwise operations (AND, OR, BIC, ORN, MVN) in register-to-register forms, and the immediate forms of AND/OR/BIC/ORN; byte-order reverse instructions; and the VMOVs that access a single lane of a vector. Some of those VMOVs (specifically, the ones that access a 32-bit lane) share an encoding with existing instructions that were disassembled as accessing half of a d-register (e.g. `vmov.32 r0, d1[0]`), but in 8.1-M they're now written as accessing a quarter of a q-register (e.g. `vmov.32 r0, q0[2]`). The older syntax is still accepted by the assembler. Reviewers: dmgreen, samparker, SjoerdMeijer, t.p.northover Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62673 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363838 91177308-0d34-0410-b5e6-96231b3b80d8 Simon Tatham 1 year, 1 month ago
12 changed file(s) with 1100 addition(s) and 28 deletion(s). Raw diff Collapse all Expand all
464464 : AsmPseudoInst, Requires<[HasVFP2]>;
465465 class NEONAsmPseudo
466466 : AsmPseudoInst, Requires<[HasNEON]>;
467 class MVEAsmPseudo
468 : AsmPseudoInst, Requires<[HasMVEInt]>;
467469
468470 // Pseudo instructions for the code generator.
469471 class PseudoInst pattern>
458458 rot_imm_XFORM> {
459459 let PrintMethod = "printRotImmOperand";
460460 let ParserMatchClass = RotImmAsmOperand;
461 }
462
463 // Vector indexing
464 class MVEVectorIndexOperand : AsmOperandClass {
465 let Name = "MVEVectorIndex"#NumLanes;
466 let RenderMethod = "addMVEVectorIndexOperands";
467 let PredicateMethod = "isVectorIndexInRange<"#NumLanes#">";
468 }
469
470 class MVEVectorIndex : Operand {
471 let PrintMethod = "printVectorIndex";
472 let ParserMatchClass = MVEVectorIndexOperand;
473 let MIOperandInfo = (ops i32imm);
461474 }
462475
463476 // shift_imm: An integer that encodes a shift amount and the type of shift
88 // This file describes the ARM MVE instruction set.
99 //
1010 //===----------------------------------------------------------------------===//
11
12 class ExpandImmAsmOp : AsmOperandClass {
13 let Name = !strconcat("ExpandImm", shift);
14 let PredicateMethod = !strconcat("isExpImm<", shift, ">");
15 let RenderMethod = "addImmOperands";
16 }
17 class InvertedExpandImmAsmOp : AsmOperandClass {
18 let Name = !strconcat("InvertedExpandImm", shift, "_", size);
19 let PredicateMethod = !strconcat("isInvertedExpImm<", shift, ",", size, ">");
20 let RenderMethod = "addImmOperands";
21 }
22
23 class ExpandImm : Operand {
24 let ParserMatchClass = ExpandImmAsmOp;
25 let EncoderMethod = !strconcat("getExpandedImmOpValue<",shift,",false>");
26 let DecoderMethod = !strconcat("DecodeExpandedImmOperand<",shift,">");
27 let PrintMethod = "printExpandedImmOperand";
28 }
29 class InvertedExpandImm : Operand {
30 let ParserMatchClass = InvertedExpandImmAsmOp;
31 let EncoderMethod = !strconcat("getExpandedImmOpValue<",shift,",true>");
32 let PrintMethod = "printExpandedImmOperand";
33 // No decoder method needed, because this operand type is only used
34 // by aliases (VAND and VORN)
35 }
36
37 def expzero00 : ExpandImm<"0">;
38 def expzero08 : ExpandImm<"8">;
39 def expzero16 : ExpandImm<"16">;
40 def expzero24 : ExpandImm<"24">;
41
42 def expzero00inv16 : InvertedExpandImm<"0", "16">;
43 def expzero08inv16 : InvertedExpandImm<"8", "16">;
44
45 def expzero00inv32 : InvertedExpandImm<"0", "32">;
46 def expzero08inv32 : InvertedExpandImm<"8", "32">;
47 def expzero16inv32 : InvertedExpandImm<"16", "32">;
48 def expzero24inv32 : InvertedExpandImm<"24", "32">;
1149
1250 // VPT condition mask
1351 def vpt_mask : Operand {
107145 string ops, string cstr, list pattern>
108146 : Thumb2I
109147 pattern>,
148 Requires<[HasV8_1MMainline, HasMVEInt]> {
149 let D = MVEDomain;
150 let DecoderNamespace = "MVE";
151 }
152
153 class MVE_VMOV_lane_base
154 string suffix, string ops, string cstr,
155 list pattern>
156 : Thumb2I
157 !if(!eq(suffix, ""), "", "." # suffix) # "\t" # ops,
158 cstr, pattern>,
110159 Requires<[HasV8_1MMainline, HasMVEInt]> {
111160 let D = MVEDomain;
112161 let DecoderNamespace = "MVE";
12161265 }
12171266 // end of mve_shift instructions
12181267
1268 // start of mve_bit instructions
1269
1270 class MVE_bit_arith
1271 string ops, string cstr, list pattern=[]>
1272 : MVE_p {
1273 bits<4> Qd;
1274 bits<4> Qm;
1275
1276 let Inst{22} = Qd{3};
1277 let Inst{15-13} = Qd{2-0};
1278 let Inst{5} = Qm{3};
1279 let Inst{3-1} = Qm{2-0};
1280 }
1281
1282 def MVE_VBIC : MVE_bit_arith<(outs MQPR:$Qd), (ins MQPR:$Qn, MQPR:$Qm),
1283 "vbic", "", "$Qd, $Qn, $Qm", ""> {
1284 bits<4> Qn;
1285
1286 let Inst{28} = 0b0;
1287 let Inst{25-23} = 0b110;
1288 let Inst{21-20} = 0b01;
1289 let Inst{19-17} = Qn{2-0};
1290 let Inst{16} = 0b0;
1291 let Inst{12-8} = 0b00001;
1292 let Inst{7} = Qn{3};
1293 let Inst{6} = 0b1;
1294 let Inst{4} = 0b1;
1295 let Inst{0} = 0b0;
1296 }
1297
1298 class MVE_VREV size, bits<2> bit_8_7>
1299 : MVE_bit_arith<(outs MQPR:$Qd), (ins MQPR:$Qm), iname,
1300 suffix, "$Qd, $Qm", ""> {
1301
1302 let Inst{28} = 0b1;
1303 let Inst{25-23} = 0b111;
1304 let Inst{21-20} = 0b11;
1305 let Inst{19-18} = size;
1306 let Inst{17-16} = 0b00;
1307 let Inst{12-9} = 0b0000;
1308 let Inst{8-7} = bit_8_7;
1309 let Inst{6} = 0b1;
1310 let Inst{4} = 0b0;
1311 let Inst{0} = 0b0;
1312 }
1313
1314 def MVE_VREV64_8 : MVE_VREV<"vrev64", "8", 0b00, 0b00>;
1315 def MVE_VREV64_16 : MVE_VREV<"vrev64", "16", 0b01, 0b00>;
1316 def MVE_VREV64_32 : MVE_VREV<"vrev64", "32", 0b10, 0b00>;
1317
1318 def MVE_VREV32_8 : MVE_VREV<"vrev32", "8", 0b00, 0b01>;
1319 def MVE_VREV32_16 : MVE_VREV<"vrev32", "16", 0b01, 0b01>;
1320
1321 def MVE_VREV16_8 : MVE_VREV<"vrev16", "8", 0b00, 0b10>;
1322
1323 def MVE_VMVN : MVE_bit_arith<(outs MQPR:$Qd), (ins MQPR:$Qm),
1324 "vmvn", "", "$Qd, $Qm", ""> {
1325 let Inst{28} = 0b1;
1326 let Inst{25-23} = 0b111;
1327 let Inst{21-16} = 0b110000;
1328 let Inst{12-6} = 0b0010111;
1329 let Inst{4} = 0b0;
1330 let Inst{0} = 0b0;
1331 }
1332
1333 class MVE_bit_ops bit_21_20, bit bit_28>
1334 : MVE_bit_arith<(outs MQPR:$Qd), (ins MQPR:$Qn, MQPR:$Qm),
1335 iname, "", "$Qd, $Qn, $Qm", ""> {
1336 bits<4> Qn;
1337
1338 let Inst{28} = bit_28;
1339 let Inst{25-23} = 0b110;
1340 let Inst{21-20} = bit_21_20;
1341 let Inst{19-17} = Qn{2-0};
1342 let Inst{16} = 0b0;
1343 let Inst{12-8} = 0b00001;
1344 let Inst{7} = Qn{3};
1345 let Inst{6} = 0b1;
1346 let Inst{4} = 0b1;
1347 let Inst{0} = 0b0;
1348 }
1349
1350 def MVE_VEOR : MVE_bit_ops<"veor", 0b00, 0b1>;
1351 def MVE_VORN : MVE_bit_ops<"vorn", 0b11, 0b0>;
1352 def MVE_VORR : MVE_bit_ops<"vorr", 0b10, 0b0>;
1353 def MVE_VAND : MVE_bit_ops<"vand", 0b00, 0b0>;
1354
1355 // add ignored suffixes as aliases
1356
1357 foreach s=["s8", "s16", "s32", "u8", "u16", "u32", "i8", "i16", "i32", "f16", "f32"] in {
1358 def : MVEInstAlias<"vbic${vp}." # s # "\t$QdSrc, $QnSrc, $QmSrc",
1359 (MVE_VBIC MQPR:$QdSrc, MQPR:$QnSrc, MQPR:$QmSrc, vpred_r:$vp)>;
1360 def : MVEInstAlias<"veor${vp}." # s # "\t$QdSrc, $QnSrc, $QmSrc",
1361 (MVE_VEOR MQPR:$QdSrc, MQPR:$QnSrc, MQPR:$QmSrc, vpred_r:$vp)>;
1362 def : MVEInstAlias<"vorn${vp}." # s # "\t$QdSrc, $QnSrc, $QmSrc",
1363 (MVE_VORN MQPR:$QdSrc, MQPR:$QnSrc, MQPR:$QmSrc, vpred_r:$vp)>;
1364 def : MVEInstAlias<"vorr${vp}." # s # "\t$QdSrc, $QnSrc, $QmSrc",
1365 (MVE_VORR MQPR:$QdSrc, MQPR:$QnSrc, MQPR:$QmSrc, vpred_r:$vp)>;
1366 def : MVEInstAlias<"vand${vp}." # s # "\t$QdSrc, $QnSrc, $QmSrc",
1367 (MVE_VAND MQPR:$QdSrc, MQPR:$QnSrc, MQPR:$QmSrc, vpred_r:$vp)>;
1368 }
1369
1370 class MVE_bit_cmode cmode, dag inOps>
1371 : MVE_p<(outs MQPR:$Qd), inOps, NoItinerary,
1372 iname, suffix, "$Qd, $imm", vpred_n, "$Qd = $Qd_src"> {
1373 bits<8> imm;
1374 bits<4> Qd;
1375
1376 let Inst{28} = imm{7};
1377 let Inst{27-23} = 0b11111;
1378 let Inst{22} = Qd{3};
1379 let Inst{21-19} = 0b000;
1380 let Inst{18-16} = imm{6-4};
1381 let Inst{15-13} = Qd{2-0};
1382 let Inst{12} = 0b0;
1383 let Inst{11-8} = cmode;
1384 let Inst{7-6} = 0b01;
1385 let Inst{4} = 0b1;
1386 let Inst{3-0} = imm{3-0};
1387 }
1388
1389 class MVE_VORR cmode, ExpandImm imm_type>
1390 : MVE_bit_cmode<"vorr", suffix, cmode, (ins MQPR:$Qd_src, imm_type:$imm)> {
1391 let Inst{5} = 0b0;
1392 }
1393
1394 def MVE_VORRIZ0v4i32 : MVE_VORR<"i32", 0b0001, expzero00>;
1395 def MVE_VORRIZ0v8i16 : MVE_VORR<"i16", 0b1001, expzero00>;
1396 def MVE_VORRIZ8v4i32 : MVE_VORR<"i32", 0b0011, expzero08>;
1397 def MVE_VORRIZ8v8i16 : MVE_VORR<"i16", 0b1011, expzero08>;
1398 def MVE_VORRIZ16v4i32 : MVE_VORR<"i32", 0b0101, expzero16>;
1399 def MVE_VORRIZ24v4i32 : MVE_VORR<"i32", 0b0111, expzero24>;
1400
1401 def MVE_VORNIZ0v4i32 : MVEAsmPseudo<"vorn${vp}.i32\t$Qd, $imm",
1402 (ins MQPR:$Qd_src, expzero00inv32:$imm, vpred_n:$vp), (outs MQPR:$Qd)>;
1403 def MVE_VORNIZ0v8i16 : MVEAsmPseudo<"vorn${vp}.i16\t$Qd, $imm",
1404 (ins MQPR:$Qd_src, expzero00inv16:$imm, vpred_n:$vp), (outs MQPR:$Qd)>;
1405 def MVE_VORNIZ8v4i32 : MVEAsmPseudo<"vorn${vp}.i32\t$Qd, $imm",
1406 (ins MQPR:$Qd_src, expzero08inv32:$imm, vpred_n:$vp), (outs MQPR:$Qd)>;
1407 def MVE_VORNIZ8v8i16 : MVEAsmPseudo<"vorn${vp}.i16\t$Qd, $imm",
1408 (ins MQPR:$Qd_src, expzero08inv16:$imm, vpred_n:$vp), (outs MQPR:$Qd)>;
1409 def MVE_VORNIZ16v4i32 : MVEAsmPseudo<"vorn${vp}.i32\t$Qd, $imm",
1410 (ins MQPR:$Qd_src, expzero16inv32:$imm, vpred_n:$vp), (outs MQPR:$Qd)>;
1411 def MVE_VORNIZ24v4i32 : MVEAsmPseudo<"vorn${vp}.i32\t$Qd, $imm",
1412 (ins MQPR:$Qd_src, expzero24inv32:$imm, vpred_n:$vp), (outs MQPR:$Qd)>;
1413
1414 def MVE_VMOV : MVEInstAlias<"vmov${vp}\t$Qd, $Qm",
1415 (MVE_VORR MQPR:$Qd, MQPR:$Qm, MQPR:$Qm, vpred_r:$vp)>;
1416
1417 class MVE_VBIC cmode, ExpandImm imm_type>
1418 : MVE_bit_cmode<"vbic", suffix, cmode, (ins MQPR:$Qd_src, imm_type:$imm)> {
1419 let Inst{5} = 0b1;
1420 }
1421
1422 def MVE_VBICIZ0v4i32 : MVE_VBIC<"i32", 0b0001, expzero00>;
1423 def MVE_VBICIZ0v8i16 : MVE_VBIC<"i16", 0b1001, expzero00>;
1424 def MVE_VBICIZ8v4i32 : MVE_VBIC<"i32", 0b0011, expzero08>;
1425 def MVE_VBICIZ8v8i16 : MVE_VBIC<"i16", 0b1011, expzero08>;
1426 def MVE_VBICIZ16v4i32 : MVE_VBIC<"i32", 0b0101, expzero16>;
1427 def MVE_VBICIZ24v4i32 : MVE_VBIC<"i32", 0b0111, expzero24>;
1428
1429 def MVE_VANDIZ0v4i32 : MVEAsmPseudo<"vand${vp}.i32\t$Qda, $imm",
1430 (ins MQPR:$Qda_src, expzero00inv32:$imm, vpred_n:$vp), (outs MQPR:$Qda)>;
1431 def MVE_VANDIZ0v8i16 : MVEAsmPseudo<"vand${vp}.i16\t$Qda, $imm",
1432 (ins MQPR:$Qda_src, expzero00inv16:$imm, vpred_n:$vp), (outs MQPR:$Qda)>;
1433 def MVE_VANDIZ8v4i32 : MVEAsmPseudo<"vand${vp}.i32\t$Qda, $imm",
1434 (ins MQPR:$Qda_src, expzero08inv32:$imm, vpred_n:$vp), (outs MQPR:$Qda)>;
1435 def MVE_VANDIZ8v8i16 : MVEAsmPseudo<"vand${vp}.i16\t$Qda, $imm",
1436 (ins MQPR:$Qda_src, expzero08inv16:$imm, vpred_n:$vp), (outs MQPR:$Qda)>;
1437 def MVE_VANDIZ16v4i32 : MVEAsmPseudo<"vand${vp}.i32\t$Qda, $imm",
1438 (ins MQPR:$Qda_src, expzero16inv32:$imm, vpred_n:$vp), (outs MQPR:$Qda)>;
1439 def MVE_VANDIZ24v4i32 : MVEAsmPseudo<"vand${vp}.i32\t$Qda, $imm",
1440 (ins MQPR:$Qda_src, expzero24inv32:$imm, vpred_n:$vp), (outs MQPR:$Qda)>;
1441
1442 class MVE_VMOV_lane_direction {
1443 bit bit_20;
1444 dag oops;
1445 dag iops;
1446 string ops;
1447 string cstr;
1448 }
1449 def MVE_VMOV_from_lane : MVE_VMOV_lane_direction {
1450 let bit_20 = 0b1;
1451 let oops = (outs rGPR:$Rt);
1452 let iops = (ins MQPR:$Qd);
1453 let ops = "$Rt, $Qd$Idx";
1454 let cstr = "";
1455 }
1456 def MVE_VMOV_to_lane : MVE_VMOV_lane_direction {
1457 let bit_20 = 0b0;
1458 let oops = (outs MQPR:$Qd);
1459 let iops = (ins MQPR:$Qd_src, rGPR:$Rt);
1460 let ops = "$Qd$Idx, $Rt";
1461 let cstr = "$Qd = $Qd_src";
1462 }
1463
1464 class MVE_VMOV_lane
1465 MVE_VMOV_lane_direction dir>
1466 : MVE_VMOV_lane_base
1467 "vmov", suffix, dir.ops, dir.cstr, []> {
1468 bits<4> Qd;
1469 bits<5> Rt;
1470
1471 let Inst{31-24} = 0b11101110;
1472 let Inst{23} = U;
1473 let Inst{20} = dir.bit_20;
1474 let Inst{19-17} = Qd{2-0};
1475 let Inst{15-12} = Rt{3-0};
1476 let Inst{11-8} = 0b1011;
1477 let Inst{7} = Qd{3};
1478 let Inst{4-0} = 0b10000;
1479 }
1480
1481 class MVE_VMOV_lane_32
1482 : MVE_VMOV_lane<"32", 0b0, (ins MVEVectorIndex<4>:$Idx), dir> {
1483 bits<2> Idx;
1484 let Inst{22} = 0b0;
1485 let Inst{6-5} = 0b00;
1486 let Inst{16} = Idx{1};
1487 let Inst{21} = Idx{0};
1488
1489 let Predicates = [HasFPRegsV8_1M];
1490 }
1491
1492 class MVE_VMOV_lane_16
1493 : MVE_VMOV_lane:$Idx), dir> {
1494 bits<3> Idx;
1495 let Inst{22} = 0b0;
1496 let Inst{5} = 0b1;
1497 let Inst{16} = Idx{2};
1498 let Inst{21} = Idx{1};
1499 let Inst{6} = Idx{0};
1500 }
1501
1502 class MVE_VMOV_lane_8
1503 : MVE_VMOV_lane:$Idx), dir> {
1504 bits<4> Idx;
1505 let Inst{22} = 0b1;
1506 let Inst{16} = Idx{3};
1507 let Inst{21} = Idx{2};
1508 let Inst{6} = Idx{1};
1509 let Inst{5} = Idx{0};
1510 }
1511
1512 def MVE_VMOV_from_lane_32 : MVE_VMOV_lane_32< MVE_VMOV_from_lane>;
1513 def MVE_VMOV_to_lane_32 : MVE_VMOV_lane_32< MVE_VMOV_to_lane>;
1514 def MVE_VMOV_from_lane_s16 : MVE_VMOV_lane_16<"s16", 0b0, MVE_VMOV_from_lane>;
1515 def MVE_VMOV_from_lane_u16 : MVE_VMOV_lane_16<"u16", 0b1, MVE_VMOV_from_lane>;
1516 def MVE_VMOV_to_lane_16 : MVE_VMOV_lane_16< "16", 0b0, MVE_VMOV_to_lane>;
1517 def MVE_VMOV_from_lane_s8 : MVE_VMOV_lane_8 < "s8", 0b0, MVE_VMOV_from_lane>;
1518 def MVE_VMOV_from_lane_u8 : MVE_VMOV_lane_8 < "u8", 0b1, MVE_VMOV_from_lane>;
1519 def MVE_VMOV_to_lane_8 : MVE_VMOV_lane_8 < "8", 0b0, MVE_VMOV_to_lane>;
1520
1521 // end of mve_bit instructions
1522
12191523 class MVE_VPT size, dag iops, string asm, list pattern=[]>
12201524 : MVE_MI<(outs ), iops, NoItinerary, !strconcat("vpt", "${Mk}", ".", suffix), asm, "", pattern> {
12211525 bits<3> fc;
11421142 return isImmediate<1, 33>();
11431143 }
11441144
1145 template
1146 bool isExpImmValue(uint64_t Value) const {
1147 uint64_t mask = (1 << shift) - 1;
1148 if ((Value & mask) != 0 || (Value >> shift) > 0xff)
1149 return false;
1150 return true;
1151 }
1152
1153 template
1154 bool isExpImm() const {
1155 if (!isImm()) return false;
1156 const MCConstantExpr *CE = dyn_cast(getImm());
1157 if (!CE) return false;
1158
1159 return isExpImmValue(CE->getValue());
1160 }
1161
1162 template
1163 bool isInvertedExpImm() const {
1164 if (!isImm()) return false;
1165 const MCConstantExpr *CE = dyn_cast(getImm());
1166 if (!CE) return false;
1167
1168 uint64_t OriginalValue = CE->getValue();
1169 uint64_t InvertedValue = OriginalValue ^ (((uint64_t)1 << size) - 1);
1170 return isExpImmValue(InvertedValue);
1171 }
1172
11451173 bool isPKHLSLImm() const {
11461174 return isImmediate<0, 32>();
11471175 }
18961924
18971925 bool isVectorIndex() const { return Kind == k_VectorIndex; }
18981926
1899 bool isVectorIndex8() const {
1927 template
1928 bool isVectorIndexInRange() const {
19001929 if (Kind != k_VectorIndex) return false;
1901 return VectorIndex.Val < 8;
1902 }
1903
1904 bool isVectorIndex16() const {
1905 if (Kind != k_VectorIndex) return false;
1906 return VectorIndex.Val < 4;
1907 }
1908
1909 bool isVectorIndex32() const {
1910 if (Kind != k_VectorIndex) return false;
1911 return VectorIndex.Val < 2;
1912 }
1913 bool isVectorIndex64() const {
1914 if (Kind != k_VectorIndex) return false;
1915 return VectorIndex.Val < 1;
1916 }
1930 return VectorIndex.Val < NumLanes;
1931 }
1932
1933 bool isVectorIndex8() const { return isVectorIndexInRange<8>(); }
1934 bool isVectorIndex16() const { return isVectorIndexInRange<4>(); }
1935 bool isVectorIndex32() const { return isVectorIndexInRange<2>(); }
1936 bool isVectorIndex64() const { return isVectorIndexInRange<1>(); }
19171937
19181938 bool isNEONi8splat() const {
19191939 if (!isImm()) return false;
29562976 }
29572977
29582978 void addVectorIndex64Operands(MCInst &Inst, unsigned N) const {
2979 assert(N == 1 && "Invalid number of operands!");
2980 Inst.addOperand(MCOperand::createImm(getVectorIndex()));
2981 }
2982
2983 void addMVEVectorIndexOperands(MCInst &Inst, unsigned N) const {
29592984 assert(N == 1 && "Invalid number of operands!");
29602985 Inst.addOperand(MCOperand::createImm(getVectorIndex()));
29612986 }
59355960 Mnemonic != "sbcs" && Mnemonic != "rscs" &&
59365961 !(hasMVE() &&
59375962 (Mnemonic == "vmine" ||
5938 Mnemonic == "vshle" || Mnemonic == "vshlt" || Mnemonic == "vshllt"))) {
5963 Mnemonic == "vshle" || Mnemonic == "vshlt" || Mnemonic == "vshllt" ||
5964 Mnemonic == "vmvne" || Mnemonic == "vorne"))) {
59395965 unsigned CC = ARMCondCodeFromString(Mnemonic.substr(Mnemonic.size()-2));
59405966 if (CC != ~0U) {
59415967 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
63096335 if (!hasMVE() || Operands.size() < 3)
63106336 return true;
63116337
6312 for (auto &Operand : Operands) {
6313 // We check the larger class QPR instead of just the legal class
6314 // MQPR, to more accurately report errors when using Q registers
6315 // outside of the allowed range.
6316 if (static_cast(*Operand).isVectorIndex() ||
6317 (Operand->isReg() &&
6318 (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(
6338 if (Mnemonic.startswith("vmov") &&
6339 !(Mnemonic.startswith("vmovl") || Mnemonic.startswith("vmovn") ||
6340 Mnemonic.startswith("vmovx"))) {
6341 for (auto &Operand : Operands) {
6342 if (static_cast(*Operand).isVectorIndex() ||
6343 ((*Operand).isReg() &&
6344 (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(
6345 (*Operand).getReg()) ||
6346 ARMMCRegisterClasses[ARM::DPRRegClassID].contains(
6347 (*Operand).getReg())))) {
6348 return true;
6349 }
6350 }
6351 return false;
6352 } else {
6353 for (auto &Operand : Operands) {
6354 // We check the larger class QPR instead of just the legal class
6355 // MQPR, to more accurately report errors when using Q registers
6356 // outside of the allowed range.
6357 if (static_cast(*Operand).isVectorIndex() ||
6358 (Operand->isReg() &&
6359 (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(
63196360 Operand->getReg()))))
6320 return false;
6321 }
6322 return true;
6361 return false;
6362 }
6363 return true;
6364 }
63236365 }
63246366
63256367 static bool isDataTypeToken(StringRef Tok) {
66176659 ARMOperand::CreateVPTPred(ARMVCC::None, PLoc));
66186660 Operands.insert(Operands.begin(),
66196661 ARMOperand::CreateToken(StringRef("vmovlt"), MLoc));
6662 }
6663 // For vmov instructions, as mentioned earlier, we did not add the vector
6664 // predication code, since these may contain operands that require
6665 // special parsing. So now we have to see if they require vector
6666 // predication and replace the scalar one with the vector predication
6667 // operand if that is the case.
6668 else if (Mnemonic == "vmov") {
6669 if (!shouldOmitVectorPredicateOperand(Mnemonic, Operands)) {
6670 Operands.erase(Operands.begin() + 1);
6671 SMLoc PLoc = SMLoc::getFromPointer(NameLoc.getPointer() +
6672 Mnemonic.size() + CarrySetting);
6673 Operands.insert(Operands.begin() + 1,
6674 ARMOperand::CreateVPTPred(
6675 ARMVCC::VPTCodes(VPTPredicationCode), PLoc));
6676 }
66206677 } else if (CanAcceptVPTPredicationCode) {
66216678 // For all other instructions, make sure only one of the two
66226679 // predication operands is left behind, depending on whether we should
77137770 }
77147771
77157772 switch (Inst.getOpcode()) {
7773 case ARM::MVE_VORNIZ0v4i32:
7774 case ARM::MVE_VORNIZ0v8i16:
7775 case ARM::MVE_VORNIZ8v4i32:
7776 case ARM::MVE_VORNIZ8v8i16:
7777 case ARM::MVE_VORNIZ16v4i32:
7778 case ARM::MVE_VORNIZ24v4i32:
7779 case ARM::MVE_VANDIZ0v4i32:
7780 case ARM::MVE_VANDIZ0v8i16:
7781 case ARM::MVE_VANDIZ8v4i32:
7782 case ARM::MVE_VANDIZ8v8i16:
7783 case ARM::MVE_VANDIZ16v4i32:
7784 case ARM::MVE_VANDIZ24v4i32: {
7785 unsigned Opcode;
7786 bool imm16 = false;
7787 switch(Inst.getOpcode()) {
7788 case ARM::MVE_VORNIZ0v4i32: Opcode = ARM::MVE_VORRIZ0v4i32; break;
7789 case ARM::MVE_VORNIZ0v8i16: Opcode = ARM::MVE_VORRIZ0v8i16; imm16 = true; break;
7790 case ARM::MVE_VORNIZ8v4i32: Opcode = ARM::MVE_VORRIZ8v4i32; break;
7791 case ARM::MVE_VORNIZ8v8i16: Opcode = ARM::MVE_VORRIZ8v8i16; imm16 = true; break;
7792 case ARM::MVE_VORNIZ16v4i32: Opcode = ARM::MVE_VORRIZ16v4i32; break;
7793 case ARM::MVE_VORNIZ24v4i32: Opcode = ARM::MVE_VORRIZ24v4i32; break;
7794 case ARM::MVE_VANDIZ0v4i32: Opcode = ARM::MVE_VBICIZ0v4i32; break;
7795 case ARM::MVE_VANDIZ0v8i16: Opcode = ARM::MVE_VBICIZ0v8i16; imm16 = true; break;
7796 case ARM::MVE_VANDIZ8v4i32: Opcode = ARM::MVE_VBICIZ8v4i32; break;
7797 case ARM::MVE_VANDIZ8v8i16: Opcode = ARM::MVE_VBICIZ8v8i16; imm16 = true; break;
7798 case ARM::MVE_VANDIZ16v4i32: Opcode = ARM::MVE_VBICIZ16v4i32; break;
7799 case ARM::MVE_VANDIZ24v4i32: Opcode = ARM::MVE_VBICIZ24v4i32; break;
7800 default: llvm_unreachable("unexpected opcode");
7801 }
7802
7803 MCInst TmpInst;
7804 TmpInst.setOpcode(Opcode);
7805 TmpInst.addOperand(Inst.getOperand(0));
7806 TmpInst.addOperand(Inst.getOperand(1));
7807
7808 // invert immediate
7809 unsigned imm = ~Inst.getOperand(2).getImm() & (imm16 ? 0xffff : 0xffffffff);
7810 TmpInst.addOperand(MCOperand::createImm(imm));
7811
7812 TmpInst.addOperand(Inst.getOperand(3));
7813 TmpInst.addOperand(Inst.getOperand(4));
7814 Inst = TmpInst;
7815 return true;
7816 }
77167817 // Alias for alternate form of 'ldr{,b}t Rt, [Rn], #imm' instruction.
77177818 case ARM::LDRT_POST:
77187819 case ARM::LDRBT_POST: {
503503 static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Insn,
504504 uint64_t Address,
505505 const void *Decoder);
506 template
507 static DecodeStatus DecodeExpandedImmOperand(MCInst &Inst, unsigned Val,
508 uint64_t Address,
509 const void *Decoder);
506510 static DecodeStatus DecodeMVEOverlappingLongShift(MCInst &Inst, unsigned Insn,
507511 uint64_t Address,
508512 const void *Decoder);
60246028 return S;
60256029 }
60266030
6031 template
6032 static DecodeStatus DecodeExpandedImmOperand(MCInst &Inst, unsigned Val,
6033 uint64_t Address,
6034 const void *Decoder) {
6035 Val <<= shift;
6036
6037 Inst.addOperand(MCOperand::createImm(Val));
6038 return MCDisassembler::Success;
6039 }
6040
60276041 static DecodeStatus DecodeMVEOverlappingLongShift(
60286042 MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) {
60296043 DecodeStatus S = MCDisassembler::Success;
16191619 }
16201620 }
16211621
1622 void ARMInstPrinter::printExpandedImmOperand(const MCInst *MI, unsigned OpNum,
1623 const MCSubtargetInfo &STI,
1624 raw_ostream &O) {
1625 uint32_t Val = MI->getOperand(OpNum).getImm();
1626 O << markup("
1627 O.write_hex(Val);
1628 O << markup(">");
1629 }
251251 raw_ostream &O);
252252 void printVPTMask(const MCInst *MI, unsigned OpNum,
253253 const MCSubtargetInfo &STI, raw_ostream &O);
254 void printExpandedImmOperand(const MCInst *MI, unsigned OpNum,
255 const MCSubtargetInfo &STI, raw_ostream &O);
254256
255257 private:
256258 unsigned DefaultAltIdx = ARM::NoRegAltName;
397397 unsigned getThumbSRImmOpValue(const MCInst &MI, unsigned Op,
398398 SmallVectorImpl &Fixups,
399399 const MCSubtargetInfo &STI) const;
400 template
401 unsigned getExpandedImmOpValue(const MCInst &MI, unsigned Op,
402 SmallVectorImpl &Fixups,
403 const MCSubtargetInfo &STI) const {
404 static_assert(shift <= 32, "Shift count must be less than or equal to 32.");
405 const MCOperand MO = MI.getOperand(Op);
406 return (invert ? (MO.getImm() ^ 0xff) : MO.getImm()) >> shift;
407 }
400408
401409 unsigned NEONThumb2DataIPostEncoder(const MCInst &MI,
402410 unsigned EncodedValue,
0 # RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+mve -show-encoding < %s \
1 # RUN: | FileCheck --check-prefix=CHECK-NOFP %s
2 # RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+mve.fp,+fp64 -show-encoding < %s 2>%t \
3 # RUN: | FileCheck --check-prefix=CHECK %s
4 # RUN: FileCheck --check-prefix=ERROR < %t %s
5
6 # CHECK: vorr.i16 q0, #0x12 @ encoding: [0x81,0xef,0x52,0x09]
7 # CHECK-NOFP: vorr.i16 q0, #0x12 @ encoding: [0x81,0xef,0x52,0x09]
8 vorr.i16 q0, #0x12
9
10 # CHECK: vorr.i32 q0, #0x1200 @ encoding: [0x81,0xef,0x52,0x03]
11 # CHECK-NOFP: vorr.i32 q0, #0x1200 @ encoding: [0x81,0xef,0x52,0x03]
12 vorr.i32 q0, #0x1200
13
14 # CHECK: vorr.i16 q0, #0xed @ encoding: [0x86,0xff,0x5d,0x09]
15 # CHECK-NOFP: vorr.i16 q0, #0xed @ encoding: [0x86,0xff,0x5d,0x09]
16 vorn.i16 q0, #0xff12
17
18 # CHECK: vorr.i32 q0, #0xed00 @ encoding: [0x86,0xff,0x5d,0x03]
19 # CHECK-NOFP: vorr.i32 q0, #0xed00 @ encoding: [0x86,0xff,0x5d,0x03]
20 vorn.i32 q0, #0xffff12ff
21
22 # CHECK: vorr.i32 q0, #0xed0000 @ encoding: [0x86,0xff,0x5d,0x05]
23 # CHECK-NOFP: vorr.i32 q0, #0xed0000 @ encoding: [0x86,0xff,0x5d,0x05]
24 vorn.i32 q0, #0xff12ffff
25
26 # CHECK: vorr.i32 q0, #0xed000000 @ encoding: [0x86,0xff,0x5d,0x07]
27 # CHECK-NOFP: vorr.i32 q0, #0xed000000 @ encoding: [0x86,0xff,0x5d,0x07]
28 vorn.i32 q0, #0x12ffffff
29
30 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
31 vorn.i16 q0, #0xed00
32
33 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
34 vorn.i16 q0, #0x00ed
35
36 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
37 vorn.i32 q0, #0xed000000
38
39 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
40 vorn.i32 q0, #0x00ed0000
41
42 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
43 vorn.i32 q0, #0x0000ed00
44
45 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
46 vorn.i32 q0, #0x000000ed
47
48 # CHECK: vbic.i16 q0, #0x22 @ encoding: [0x82,0xef,0x72,0x09]
49 # CHECK-NOFP: vbic.i16 q0, #0x22 @ encoding: [0x82,0xef,0x72,0x09]
50 vbic.i16 q0, #0x22
51
52 # CHECK: vbic.i32 q0, #0x1100 @ encoding: [0x81,0xef,0x71,0x03]
53 # CHECK-NOFP: vbic.i32 q0, #0x1100 @ encoding: [0x81,0xef,0x71,0x03]
54 vbic.i32 q0, #0x1100
55
56 # CHECK: vbic.i16 q0, #0xdd @ encoding: [0x85,0xff,0x7d,0x09]
57 # CHECK-NOFP: vbic.i16 q0, #0xdd @ encoding: [0x85,0xff,0x7d,0x09]
58 vand.i16 q0, #0xff22
59
60 # CHECK: vbic.i16 q0, #0xdd00 @ encoding: [0x85,0xff,0x7d,0x0b]
61 # CHECK-NOFP: vbic.i16 q0, #0xdd00 @ encoding: [0x85,0xff,0x7d,0x0b]
62 vand.i16 q0, #0x22ff
63
64 # CHECK: vbic.i32 q0, #0xee @ encoding: [0x86,0xff,0x7e,0x01]
65 # CHECK-NOFP: vbic.i32 q0, #0xee @ encoding: [0x86,0xff,0x7e,0x01]
66 vand.i32 q0, #0xffffff11
67
68 # CHECK: vbic.i32 q0, #0xee00 @ encoding: [0x86,0xff,0x7e,0x03]
69 # CHECK-NOFP: vbic.i32 q0, #0xee00 @ encoding: [0x86,0xff,0x7e,0x03]
70 vand.i32 q0, #0xffff11ff
71
72 # CHECK: vbic.i32 q0, #0xee0000 @ encoding: [0x86,0xff,0x7e,0x05]
73 # CHECK-NOFP: vbic.i32 q0, #0xee0000 @ encoding: [0x86,0xff,0x7e,0x05]
74 vand.i32 q0, #0xff11ffff
75
76 # CHECK: vbic.i32 q0, #0xee000000 @ encoding: [0x86,0xff,0x7e,0x07]
77 # CHECK-NOFP: vbic.i32 q0, #0xee000000 @ encoding: [0x86,0xff,0x7e,0x07]
78 vand.i32 q0, #0x11ffffff
79
80 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
81 vand.i16 q0, #0xed00
82
83 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
84 vand.i16 q0, #0x00ed
85
86 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
87 vand.i32 q0, #0xed000000
88
89 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
90 vand.i32 q0, #0x00ed0000
91
92 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
93 vand.i32 q0, #0x0000ed00
94
95 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
96 vand.i32 q0, #0x000000ed
97
98 # CHECK: vbic q0, q1, q7 @ encoding: [0x12,0xef,0x5e,0x01]
99 # CHECK-NOFP: vbic q0, q1, q7 @ encoding: [0x12,0xef,0x5e,0x01]
100 vbic q0, q1, q7
101
102 # CHECK: vbic q0, q1, q7 @ encoding: [0x12,0xef,0x5e,0x01]
103 # CHECK-NOFP: vbic q0, q1, q7 @ encoding: [0x12,0xef,0x5e,0x01]
104 vbic.s8 q0, q1, q7
105
106 # CHECK: vbic q0, q1, q7 @ encoding: [0x12,0xef,0x5e,0x01]
107 # CHECK-NOFP: vbic q0, q1, q7 @ encoding: [0x12,0xef,0x5e,0x01]
108 vbic.s16 q0, q1, q7
109
110 # CHECK: vbic q0, q1, q7 @ encoding: [0x12,0xef,0x5e,0x01]
111 # CHECK-NOFP: vbic q0, q1, q7 @ encoding: [0x12,0xef,0x5e,0x01]
112 vbic.s32 q0, q1, q7
113
114 # CHECK: vbic q0, q1, q7 @ encoding: [0x12,0xef,0x5e,0x01]
115 # CHECK-NOFP: vbic q0, q1, q7 @ encoding: [0x12,0xef,0x5e,0x01]
116 vbic.u8 q0, q1, q7
117
118 # CHECK: vbic q0, q1, q7 @ encoding: [0x12,0xef,0x5e,0x01]
119 # CHECK-NOFP: vbic q0, q1, q7 @ encoding: [0x12,0xef,0x5e,0x01]
120 vbic.u16 q0, q1, q7
121
122 # CHECK: vbic q0, q1, q7 @ encoding: [0x12,0xef,0x5e,0x01]
123 # CHECK-NOFP: vbic q0, q1, q7 @ encoding: [0x12,0xef,0x5e,0x01]
124 vbic.u32 q0, q1, q7
125
126 # CHECK: vbic q0, q1, q7 @ encoding: [0x12,0xef,0x5e,0x01]
127 # CHECK-NOFP: vbic q0, q1, q7 @ encoding: [0x12,0xef,0x5e,0x01]
128 vbic.i8 q0, q1, q7
129
130 # CHECK: vbic q0, q1, q7 @ encoding: [0x12,0xef,0x5e,0x01]
131 # CHECK-NOFP: vbic q0, q1, q7 @ encoding: [0x12,0xef,0x5e,0x01]
132 vbic.i16 q0, q1, q7
133
134 # CHECK: vbic q0, q1, q7 @ encoding: [0x12,0xef,0x5e,0x01]
135 # CHECK-NOFP: vbic q0, q1, q7 @ encoding: [0x12,0xef,0x5e,0x01]
136 vbic.i32 q0, q1, q7
137
138 # CHECK: vbic q0, q1, q7 @ encoding: [0x12,0xef,0x5e,0x01]
139 # CHECK-NOFP: vbic q0, q1, q7 @ encoding: [0x12,0xef,0x5e,0x01]
140 vbic.f16 q0, q1, q7
141
142 # CHECK: vbic q0, q1, q7 @ encoding: [0x12,0xef,0x5e,0x01]
143 # CHECK-NOFP: vbic q0, q1, q7 @ encoding: [0x12,0xef,0x5e,0x01]
144 vbic.f32 q0, q1, q7
145
146 # CHECK: vrev64.8 q0, q4 @ encoding: [0xb0,0xff,0x48,0x00]
147 # CHECK-NOFP: vrev64.8 q0, q4 @ encoding: [0xb0,0xff,0x48,0x00]
148 vrev64.8 q0, q4
149
150 # CHECK: vrev64.16 q1, q3 @ encoding: [0xb4,0xff,0x46,0x20]
151 # CHECK-NOFP: vrev64.16 q1, q3 @ encoding: [0xb4,0xff,0x46,0x20]
152 vrev64.16 q1, q3
153
154 # CHECK: vrev64.32 q0, q2 @ encoding: [0xb8,0xff,0x44,0x00]
155 # CHECK-NOFP: vrev64.32 q0, q2 @ encoding: [0xb8,0xff,0x44,0x00]
156 vrev64.32 q0, q2
157
158 # CHECK: vrev32.8 q0, q1 @ encoding: [0xb0,0xff,0xc2,0x00]
159 # CHECK-NOFP: vrev32.8 q0, q1 @ encoding: [0xb0,0xff,0xc2,0x00]
160 vrev32.8 q0, q1
161
162 # CHECK: vrev32.16 q0, q5 @ encoding: [0xb4,0xff,0xca,0x00]
163 # CHECK-NOFP: vrev32.16 q0, q5 @ encoding: [0xb4,0xff,0xca,0x00]
164 vrev32.16 q0, q5
165
166 # CHECK: vrev16.8 q0, q2 @ encoding: [0xb0,0xff,0x44,0x01]
167 # CHECK-NOFP: vrev16.8 q0, q2 @ encoding: [0xb0,0xff,0x44,0x01]
168 vrev16.8 q0, q2
169
170 # CHECK: vmvn q0, q2 @ encoding: [0xb0,0xff,0xc4,0x05]
171 # CHECK-NOFP: vmvn q0, q2 @ encoding: [0xb0,0xff,0xc4,0x05]
172 vmvn q0, q2
173
174 # CHECK: veor q2, q1, q7 @ encoding: [0x02,0xff,0x5e,0x41]
175 # CHECK-NOFP: veor q2, q1, q7 @ encoding: [0x02,0xff,0x5e,0x41]
176 veor q2, q1, q7
177
178 # CHECK: veor q2, q1, q7 @ encoding: [0x02,0xff,0x5e,0x41]
179 # CHECK-NOFP: veor q2, q1, q7 @ encoding: [0x02,0xff,0x5e,0x41]
180 veor.s8 q2, q1, q7
181
182 # CHECK: veor q2, q1, q7 @ encoding: [0x02,0xff,0x5e,0x41]
183 # CHECK-NOFP: veor q2, q1, q7 @ encoding: [0x02,0xff,0x5e,0x41]
184 veor.s16 q2, q1, q7
185
186 # CHECK: veor q2, q1, q7 @ encoding: [0x02,0xff,0x5e,0x41]
187 # CHECK-NOFP: veor q2, q1, q7 @ encoding: [0x02,0xff,0x5e,0x41]
188 veor.s32 q2, q1, q7
189
190 # CHECK: veor q2, q1, q7 @ encoding: [0x02,0xff,0x5e,0x41]
191 # CHECK-NOFP: veor q2, q1, q7 @ encoding: [0x02,0xff,0x5e,0x41]
192 veor.u8 q2, q1, q7
193
194 # CHECK: veor q2, q1, q7 @ encoding: [0x02,0xff,0x5e,0x41]
195 # CHECK-NOFP: veor q2, q1, q7 @ encoding: [0x02,0xff,0x5e,0x41]
196 veor.u16 q2, q1, q7
197
198 # CHECK: veor q2, q1, q7 @ encoding: [0x02,0xff,0x5e,0x41]
199 # CHECK-NOFP: veor q2, q1, q7 @ encoding: [0x02,0xff,0x5e,0x41]
200 veor.u32 q2, q1, q7
201
202 # CHECK: veor q2, q1, q7 @ encoding: [0x02,0xff,0x5e,0x41]
203 # CHECK-NOFP: veor q2, q1, q7 @ encoding: [0x02,0xff,0x5e,0x41]
204 veor.i8 q2, q1, q7
205
206 # CHECK: veor q2, q1, q7 @ encoding: [0x02,0xff,0x5e,0x41]
207 # CHECK-NOFP: veor q2, q1, q7 @ encoding: [0x02,0xff,0x5e,0x41]
208 veor.i16 q2, q1, q7
209
210 # CHECK: veor q2, q1, q7 @ encoding: [0x02,0xff,0x5e,0x41]
211 # CHECK-NOFP: veor q2, q1, q7 @ encoding: [0x02,0xff,0x5e,0x41]
212 veor.i32 q2, q1, q7
213
214 # CHECK: veor q2, q1, q7 @ encoding: [0x02,0xff,0x5e,0x41]
215 # CHECK-NOFP: veor q2, q1, q7 @ encoding: [0x02,0xff,0x5e,0x41]
216 veor.f16 q2, q1, q7
217
218 # CHECK: veor q2, q1, q7 @ encoding: [0x02,0xff,0x5e,0x41]
219 # CHECK-NOFP: veor q2, q1, q7 @ encoding: [0x02,0xff,0x5e,0x41]
220 veor.f32 q2, q1, q7
221
222 # CHECK: vorn q0, q3, q2 @ encoding: [0x36,0xef,0x54,0x01]
223 # CHECK-NOFP: vorn q0, q3, q2 @ encoding: [0x36,0xef,0x54,0x01]
224 vorn q0, q3, q2
225
226 # CHECK: vorn q0, q3, q2 @ encoding: [0x36,0xef,0x54,0x01]
227 # CHECK-NOFP: vorn q0, q3, q2 @ encoding: [0x36,0xef,0x54,0x01]
228 vorn.s8 q0, q3, q2
229
230 # CHECK: vorn q0, q3, q2 @ encoding: [0x36,0xef,0x54,0x01]
231 # CHECK-NOFP: vorn q0, q3, q2 @ encoding: [0x36,0xef,0x54,0x01]
232 vorn.s16 q0, q3, q2
233
234 # CHECK: vorn q0, q3, q2 @ encoding: [0x36,0xef,0x54,0x01]
235 # CHECK-NOFP: vorn q0, q3, q2 @ encoding: [0x36,0xef,0x54,0x01]
236 vorn.s32 q0, q3, q2
237
238 # CHECK: vorn q0, q3, q2 @ encoding: [0x36,0xef,0x54,0x01]
239 # CHECK-NOFP: vorn q0, q3, q2 @ encoding: [0x36,0xef,0x54,0x01]
240 vorn.u8 q0, q3, q2
241
242 # CHECK: vorn q0, q3, q2 @ encoding: [0x36,0xef,0x54,0x01]
243 # CHECK-NOFP: vorn q0, q3, q2 @ encoding: [0x36,0xef,0x54,0x01]
244 vorn.u16 q0, q3, q2
245
246 # CHECK: vorn q0, q3, q2 @ encoding: [0x36,0xef,0x54,0x01]
247 # CHECK-NOFP: vorn q0, q3, q2 @ encoding: [0x36,0xef,0x54,0x01]
248 vorn.u32 q0, q3, q2
249
250 # CHECK: vorn q0, q3, q2 @ encoding: [0x36,0xef,0x54,0x01]
251 # CHECK-NOFP: vorn q0, q3, q2 @ encoding: [0x36,0xef,0x54,0x01]
252 vorn.i8 q0, q3, q2
253
254 # CHECK: vorn q0, q3, q2 @ encoding: [0x36,0xef,0x54,0x01]
255 # CHECK-NOFP: vorn q0, q3, q2 @ encoding: [0x36,0xef,0x54,0x01]
256 vorn.i16 q0, q3, q2
257
258 # CHECK: vorn q0, q3, q2 @ encoding: [0x36,0xef,0x54,0x01]
259 # CHECK-NOFP: vorn q0, q3, q2 @ encoding: [0x36,0xef,0x54,0x01]
260 vorn.i32 q0, q3, q2
261
262 # CHECK: vorn q0, q3, q2 @ encoding: [0x36,0xef,0x54,0x01]
263 # CHECK-NOFP: vorn q0, q3, q2 @ encoding: [0x36,0xef,0x54,0x01]
264 vorn.f16 q0, q3, q2
265
266 # CHECK: vorn q0, q3, q2 @ encoding: [0x36,0xef,0x54,0x01]
267 # CHECK-NOFP: vorn q0, q3, q2 @ encoding: [0x36,0xef,0x54,0x01]
268 vorn.f32 q0, q3, q2
269
270 # CHECK: vorr q1, q2, q1 @ encoding: [0x24,0xef,0x52,0x21]
271 # CHECK-NOFP: vorr q1, q2, q1 @ encoding: [0x24,0xef,0x52,0x21]
272 vorr q1, q2, q1
273
274 # CHECK: vorr q1, q2, q1 @ encoding: [0x24,0xef,0x52,0x21]
275 # CHECK-NOFP: vorr q1, q2, q1 @ encoding: [0x24,0xef,0x52,0x21]
276 vorr.s8 q1, q2, q1
277
278 # CHECK: vorr q1, q2, q1 @ encoding: [0x24,0xef,0x52,0x21]
279 # CHECK-NOFP: vorr q1, q2, q1 @ encoding: [0x24,0xef,0x52,0x21]
280 vorr.s16 q1, q2, q1
281
282 # CHECK: vorr q1, q2, q1 @ encoding: [0x24,0xef,0x52,0x21]
283 # CHECK-NOFP: vorr q1, q2, q1 @ encoding: [0x24,0xef,0x52,0x21]
284 vorr.s32 q1, q2, q1
285
286 # CHECK: vorr q1, q2, q1 @ encoding: [0x24,0xef,0x52,0x21]
287 # CHECK-NOFP: vorr q1, q2, q1 @ encoding: [0x24,0xef,0x52,0x21]
288 vorr.u8 q1, q2, q1
289
290 # CHECK: vorr q1, q2, q1 @ encoding: [0x24,0xef,0x52,0x21]
291 # CHECK-NOFP: vorr q1, q2, q1 @ encoding: [0x24,0xef,0x52,0x21]
292 vorr.u16 q1, q2, q1
293
294 # CHECK: vorr q1, q2, q1 @ encoding: [0x24,0xef,0x52,0x21]
295 # CHECK-NOFP: vorr q1, q2, q1 @ encoding: [0x24,0xef,0x52,0x21]
296 vorr.u32 q1, q2, q1
297
298 # CHECK: vorr q1, q2, q1 @ encoding: [0x24,0xef,0x52,0x21]
299 # CHECK-NOFP: vorr q1, q2, q1 @ encoding: [0x24,0xef,0x52,0x21]
300 vorr.i8 q1, q2, q1
301
302 # CHECK: vorr q1, q2, q1 @ encoding: [0x24,0xef,0x52,0x21]
303 # CHECK-NOFP: vorr q1, q2, q1 @ encoding: [0x24,0xef,0x52,0x21]
304 vorr.i16 q1, q2, q1
305
306 # CHECK: vorr q1, q2, q1 @ encoding: [0x24,0xef,0x52,0x21]
307 # CHECK-NOFP: vorr q1, q2, q1 @ encoding: [0x24,0xef,0x52,0x21]
308 vorr.i32 q1, q2, q1
309
310 # CHECK: vorr q1, q2, q1 @ encoding: [0x24,0xef,0x52,0x21]
311 # CHECK-NOFP: vorr q1, q2, q1 @ encoding: [0x24,0xef,0x52,0x21]
312 vorr.f16 q1, q2, q1
313
314 # CHECK: vorr q1, q2, q1 @ encoding: [0x24,0xef,0x52,0x21]
315 # CHECK-NOFP: vorr q1, q2, q1 @ encoding: [0x24,0xef,0x52,0x21]
316 vorr.f32 q1, q2, q1
317
318 # CHECK: vand q0, q2, q0 @ encoding: [0x04,0xef,0x50,0x01]
319 # CHECK-NOFP: vand q0, q2, q0 @ encoding: [0x04,0xef,0x50,0x01]
320 vand q0, q2, q0
321
322 # CHECK: vand q0, q2, q0 @ encoding: [0x04,0xef,0x50,0x01]
323 # CHECK-NOFP: vand q0, q2, q0 @ encoding: [0x04,0xef,0x50,0x01]
324 vand.s8 q0, q2, q0
325
326 # CHECK: vand q0, q2, q0 @ encoding: [0x04,0xef,0x50,0x01]
327 # CHECK-NOFP: vand q0, q2, q0 @ encoding: [0x04,0xef,0x50,0x01]
328 vand.s16 q0, q2, q0
329
330 # CHECK: vand q0, q2, q0 @ encoding: [0x04,0xef,0x50,0x01]
331 # CHECK-NOFP: vand q0, q2, q0 @ encoding: [0x04,0xef,0x50,0x01]
332 vand.s32 q0, q2, q0
333
334 # CHECK: vand q0, q2, q0 @ encoding: [0x04,0xef,0x50,0x01]
335 # CHECK-NOFP: vand q0, q2, q0 @ encoding: [0x04,0xef,0x50,0x01]
336 vand.u8 q0, q2, q0
337
338 # CHECK: vand q0, q2, q0 @ encoding: [0x04,0xef,0x50,0x01]
339 # CHECK-NOFP: vand q0, q2, q0 @ encoding: [0x04,0xef,0x50,0x01]
340 vand.u16 q0, q2, q0
341
342 # CHECK: vand q0, q2, q0 @ encoding: [0x04,0xef,0x50,0x01]
343 # CHECK-NOFP: vand q0, q2, q0 @ encoding: [0x04,0xef,0x50,0x01]
344 vand.u32 q0, q2, q0
345
346 # CHECK: vand q0, q2, q0 @ encoding: [0x04,0xef,0x50,0x01]
347 # CHECK-NOFP: vand q0, q2, q0 @ encoding: [0x04,0xef,0x50,0x01]
348 vand.i8 q0, q2, q0
349
350 # CHECK: vand q0, q2, q0 @ encoding: [0x04,0xef,0x50,0x01]
351 # CHECK-NOFP: vand q0, q2, q0 @ encoding: [0x04,0xef,0x50,0x01]
352 vand.i16 q0, q2, q0
353
354 # CHECK: vand q0, q2, q0 @ encoding: [0x04,0xef,0x50,0x01]
355 # CHECK-NOFP: vand q0, q2, q0 @ encoding: [0x04,0xef,0x50,0x01]
356 vand.i32 q0, q2, q0
357
358 # CHECK: vand q0, q2, q0 @ encoding: [0x04,0xef,0x50,0x01]
359 # CHECK-NOFP: vand q0, q2, q0 @ encoding: [0x04,0xef,0x50,0x01]
360 vand.f16 q0, q2, q0
361
362 # CHECK: vand q0, q2, q0 @ encoding: [0x04,0xef,0x50,0x01]
363 # CHECK-NOFP: vand q0, q2, q0 @ encoding: [0x04,0xef,0x50,0x01]
364 vand.f32 q0, q2, q0
365
366 # CHECK: vmov.8 q0[1], r8 @ encoding: [0x40,0xee,0x30,0x8b]
367 # CHECK-NOFP: vmov.8 q0[1], r8 @ encoding: [0x40,0xee,0x30,0x8b]
368 vmov.8 q0[1], r8
369
370 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
371 vmov.8 q0[16], r8
372
373 # CHECK: vmov.16 q0[2], r5 @ encoding: [0x20,0xee,0x30,0x5b]
374 # CHECK-NOFP: vmov.16 q0[2], r5 @ encoding: [0x20,0xee,0x30,0x5b]
375 vmov.16 q0[2], r5
376
377 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
378 vmov.16 q0[8], r5
379
380 # CHECK: vmov.32 q6[3], r11 @ encoding: [0x2d,0xee,0x10,0xbb]
381 # CHECK-NOFP: vmov.32 q6[3], r11 @ encoding: [0x2d,0xee,0x10,0xbb]
382 vmov.32 q6[3], r11
383
384 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
385 vmov.32 q6[4], r11
386
387 # CHECK: vmov.32 r0, q1[0] @ encoding: [0x12,0xee,0x10,0x0b]
388 # CHECK-NOFP: vmov.32 r0, q1[0] @ encoding: [0x12,0xee,0x10,0x0b]
389 vmov.32 r0, q1[0]
390
391 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
392 vmov.32 r0, q1[4]
393
394 # CHECK: vmov.s16 r1, q2[7] @ encoding: [0x35,0xee,0x70,0x1b]
395 # CHECK-NOFP: vmov.s16 r1, q2[7] @ encoding: [0x35,0xee,0x70,0x1b]
396 vmov.s16 r1, q2[7]
397
398 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
399 vmov.s16 r1, q2[8]
400
401 # CHECK: vmov.s8 r0, q4[13] @ encoding: [0x79,0xee,0x30,0x0b]
402 # CHECK-NOFP: vmov.s8 r0, q4[13] @ encoding: [0x79,0xee,0x30,0x0b]
403 vmov.s8 r0, q4[13]
404
405 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
406 vmov.s8 r0, q4[16]
407
408 # CHECK: vmov.u16 r0, q1[4] @ encoding: [0x93,0xee,0x30,0x0b]
409 # CHECK-NOFP: vmov.u16 r0, q1[4] @ encoding: [0x93,0xee,0x30,0x0b]
410 vmov.u16 r0, q1[4]
411
412 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
413 vmov.u16 r0, q1[8]
414
415 # CHECK: vmov.u8 r0, q5[7] @ encoding: [0xfa,0xee,0x70,0x0b]
416 # CHECK-NOFP: vmov.u8 r0, q5[7] @ encoding: [0xfa,0xee,0x70,0x0b]
417 vmov.u8 r0, q5[7]
418
419 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
420 vmov.u8 r0, q5[16]
421
422 vpste
423 vmvnt q0, q1
424 vmvne q0, q1
425 # CHECK: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
426 # CHECK-NOFP: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
427 # CHECK: vmvnt q0, q1 @ encoding: [0xb0,0xff,0xc2,0x05]
428 # CHECK-NOFP: vmvnt q0, q1 @ encoding: [0xb0,0xff,0xc2,0x05]
429 # CHECK: vmvne q0, q1 @ encoding: [0xb0,0xff,0xc2,0x05]
430 # CHECK-NOFP: vmvne q0, q1 @ encoding: [0xb0,0xff,0xc2,0x05]
431
432 vpste
433 vornt.s8 q0, q1, q2
434 vorne.s8 q0, q1, q2
435 # CHECK: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
436 # CHECK-NOFP: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
437 # CHECK: vornt q0, q1, q2 @ encoding: [0x32,0xef,0x54,0x01]
438 # CHECK-NOFP: vornt q0, q1, q2 @ encoding: [0x32,0xef,0x54,0x01]
439 # CHECK: vorne q0, q1, q2 @ encoding: [0x32,0xef,0x54,0x01]
440 # CHECK-NOFP: vorne q0, q1, q2 @ encoding: [0x32,0xef,0x54,0x01]
0 // RUN: not llvm-mc -triple=thumbv8m.main -mattr=+fp-armv8 -show-encoding < %s 2>%t | FileCheck %s --check-prefix=V80M
1 // RUN: FileCheck %s < %t --check-prefix=V80M-ERROR
2 // RUN: llvm-mc -triple=thumbv8.1m.main -mattr=+fp-armv8 -show-encoding < %s 2>%t
3 // RUN: llvm-mc -triple=thumbv8.1m.main -mattr=+mve -show-encoding < %s 2>%t
4
5 // v8.1M added the Q register syntax for this instruction. The v8.1M spec does
6 // not list the D register syntax as valid, but we accept it as an extension to
7 // make porting code from v8.0M to v8.1M easier.
8
9 vmov.32 r0, d1[0]
10 // V80M: vmov.32 r0, d1[0] @ encoding: [0x11,0xee,0x10,0x0b]
11 // V81M: vmov.32 r0, d1[0] @ encoding: [0x11,0xee,0x10,0x0b]
12
13 vmov.32 r0, q0[2]
14 // V80M-ERROR: :[[@LINE-1]]:{{[0-9]+}}: error: instruction requires: armv8.1m.main with FP or MVE
15 // V81M: vmov.32 r0, q0[2] @ encoding: [0x11,0xee,0x10,0x0b]
0 # RUN: llvm-mc -disassemble -triple=thumbv8.1m.main-none-eabi -mattr=+mve.fp,+fp64 -show-encoding %s 2> %t | FileCheck %s
1 # RUN: FileCheck --check-prefix=ERROR < %t %s
2 # RUN: not llvm-mc -disassemble -triple=thumbv8.1m.main-none-eabi -show-encoding %s &> %t
3 # RUN: FileCheck --check-prefix=CHECK-NOMVE < %t %s
4
5 # CHECK: vbic q0, q1, q7 @ encoding: [0x12,0xef,0x5e,0x01]
6 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
7 [0x12,0xef,0x5e,0x01]
8
9 # CHECK: vrev64.8 q0, q4 @ encoding: [0xb0,0xff,0x48,0x00]
10 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
11 [0xb0,0xff,0x48,0x00]
12
13 # CHECK: vrev64.16 q1, q3 @ encoding: [0xb4,0xff,0x46,0x20]
14 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
15 [0xb4,0xff,0x46,0x20]
16
17 # CHECK: vrev64.32 q0, q2 @ encoding: [0xb8,0xff,0x44,0x00]
18 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
19 [0xb8,0xff,0x44,0x00]
20
21 # CHECK: vrev32.8 q0, q1 @ encoding: [0xb0,0xff,0xc2,0x00]
22 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
23 [0xb0,0xff,0xc2,0x00]
24
25 # CHECK: vrev32.16 q0, q5 @ encoding: [0xb4,0xff,0xca,0x00]
26 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
27 [0xb4,0xff,0xca,0x00]
28
29 # CHECK: vrev16.8 q0, q2 @ encoding: [0xb0,0xff,0x44,0x01]
30 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
31 [0xb0,0xff,0x44,0x01]
32
33 # CHECK: vmvn q0, q2 @ encoding: [0xb0,0xff,0xc4,0x05]
34 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
35 [0xb0,0xff,0xc4,0x05]
36
37 # CHECK: veor q2, q1, q7 @ encoding: [0x02,0xff,0x5e,0x41]
38 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
39 [0x02,0xff,0x5e,0x41]
40
41 # CHECK: vorn q0, q3, q2 @ encoding: [0x36,0xef,0x54,0x01]
42 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
43 [0x36,0xef,0x54,0x01]
44
45 # CHECK: vorr q1, q2, q1 @ encoding: [0x24,0xef,0x52,0x21]
46 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
47 [0x24,0xef,0x52,0x21]
48
49 # CHECK: vand q0, q2, q0 @ encoding: [0x04,0xef,0x50,0x01]
50 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
51 [0x04,0xef,0x50,0x01]
52
53 # CHECK: vorr.i16 q0, #0x12 @ encoding: [0x81,0xef,0x52,0x09]
54 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
55 [0x81,0xef,0x52,0x09]
56
57 # CHECK: vorr.i32 q0, #0x1200 @ encoding: [0x81,0xef,0x52,0x03]
58 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
59 [0x81,0xef,0x52,0x03]
60
61 # CHECK: vbic.i32 q0, #0x35 @ encoding: [0x83,0xef,0x75,0x01]
62 [0x83,0xef,0x75,0x01]
63
64 # CHECK: vbic.i32 q0, #0x3500 @ encoding: [0x83,0xef,0x75,0x03]
65 [0x83,0xef,0x75,0x03]
66
67 # CHECK: vbic.i32 q0, #0x350000 @ encoding: [0x83,0xef,0x75,0x05]
68 [0x83,0xef,0x75,0x05]
69
70 # CHECK: vbic.i32 q0, #0x35000000 @ encoding: [0x83,0xef,0x75,0x07]
71 [0x83,0xef,0x75,0x07]
72
73 # CHECK: vbic.i16 q0, #0x35 @ encoding: [0x83,0xef,0x75,0x09]
74 [0x83,0xef,0x75,0x09]
75
76 # CHECK: vbic.i16 q0, #0x3500 @ encoding: [0x83,0xef,0x75,0x0b]
77 [0x83,0xef,0x75,0x0b]
78
79 # CHECK: vmov.8 q0[1], r8 @ encoding: [0x40,0xee,0x30,0x8b]
80 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
81 [0x40,0xee,0x30,0x8b]
82
83 # CHECK: vmov.16 q0[2], r5 @ encoding: [0x20,0xee,0x30,0x5b]
84 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
85 [0x20,0xee,0x30,0x5b]
86
87 # CHECK: vmov.32 q6[3], r11 @ encoding: [0x2d,0xee,0x10,0xbb]
88 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
89 [0x2d,0xee,0x10,0xbb]
90
91 # CHECK: vmov.32 r0, q1[0] @ encoding: [0x12,0xee,0x10,0x0b]
92 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
93 [0x12,0xee,0x10,0x0b]
94
95 # CHECK: vmov.s16 r1, q2[7] @ encoding: [0x35,0xee,0x70,0x1b]
96 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
97 [0x35,0xee,0x70,0x1b]
98
99 # CHECK: vmov.s8 r0, q4[13] @ encoding: [0x79,0xee,0x30,0x0b]
100 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
101 [0x79,0xee,0x30,0x0b]
102
103 # CHECK: vmov.u16 r0, q1[4] @ encoding: [0x93,0xee,0x30,0x0b]
104 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
105 [0x93,0xee,0x30,0x0b]
106
107 # CHECK: vmov.u8 r0, q5[7] @ encoding: [0xfa,0xee,0x70,0x0b]
108 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
109 [0xfa,0xee,0x70,0x0b]
110
111 # CHECK: vmov.f16 s7, r8 @ encoding: [0x03,0xee,0x90,0x89]
112 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
113 [0x03,0xee,0x90,0x89]
114
115 # CHECK: vmov.f16 s10, r5 @ encoding: [0x05,0xee,0x10,0x59]
116 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
117 [0x05,0xee,0x10,0x59]
118
119 # CHECK: vmov.f16 s10, sp @ encoding: [0x05,0xee,0x10,0xd9]
120 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
121 [0x05,0xee,0x10,0xd9]
122
123 # CHECK: vmov.f16 s31, r10 @ encoding: [0x0f,0xee,0x90,0xa9]
124 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
125 [0x0f,0xee,0x90,0xa9]
126
127 # CHECK: vmov.f16 r8, s7 @ encoding: [0x13,0xee,0x90,0x89]
128 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
129 [0x13,0xee,0x90,0x89]
130
131 # CHECK: vmov.f16 r5, s10 @ encoding: [0x15,0xee,0x10,0x59]
132 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
133 [0x15,0xee,0x10,0x59]
134
135 # CHECK: vmov.f16 sp, s10 @ encoding: [0x15,0xee,0x10,0xd9]
136 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
137 [0x15,0xee,0x10,0xd9]
138
139 # CHECK: vmov.f16 r10, s31 @ encoding: [0x1f,0xee,0x90,0xa9]
140 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
141 [0x1f,0xee,0x90,0xa9]
142
143 # ERROR: [[@LINE+2]]:2: warning: potentially undefined instruction encoding
144 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
145 [0x05,0xee,0x10,0xf9]
146
147 # ERROR: [[@LINE+2]]:2: warning: potentially undefined instruction encoding
148 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
149 [0x1f,0xee,0x90,0xf9]
0 # RUN: llvm-mc -triple=thumbv8m.main -mattr=+fp-armv8 -disassemble < %s | FileCheck %s --check-prefix=D_REG
1 # RUN: llvm-mc -triple=thumbv8a -mattr=+fp-armv8 -disassemble < %s | FileCheck %s --check-prefix=D_REG
2 # RUN: llvm-mc -triple=thumbv8.1m.main -mattr=+fp-armv8 -disassemble < %s | FileCheck %s --check-prefix=Q_REG
3 # RUN: llvm-mc -triple=thumbv8.1m.main -mattr=+mve -disassemble < %s | FileCheck %s --check-prefix=Q_REG
4
5 # The disassembly for this instruction varies between v8.1M and other
6 # architectures. In v8.1M (with either scalar flotaing point, MVE or both), we
7 # use the Q register syntax, and for all other architectures we use the D
8 # register syntax.
9
10 [0x11,0xee,0x10,0x0b]
11 # D_REG: vmov.32 r0, d1[0]
12 # Q_REG: vmov.32 r0, q0[2]