llvm.org GIT mirror llvm / 24b2348
Merging r246051: ------------------------------------------------------------------------ r246051 | Matthew.Arsenault | 2015-08-26 14:54:50 -0400 (Wed, 26 Aug 2015) | 6 lines AMDGPU: Make sure to reserve super registers I think this could potentially have broken if one of the super registers were allocated that contain v254/v255. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_37@253235 91177308-0d34-0410-b5e6-96231b3b80d8 Tom Stellard 3 years ago
2 changed file(s) with 18 addition(s) and 16 deletion(s). Raw diff Collapse all Expand all
2525
2626 SIRegisterInfo::SIRegisterInfo() : AMDGPURegisterInfo() {}
2727
28 void SIRegisterInfo::reserveRegisterTuples(BitVector &Reserved, unsigned Reg) const {
29 MCRegAliasIterator R(Reg, this, true);
30
31 for (; R.isValid(); ++R)
32 Reserved.set(*R);
33 }
34
2835 BitVector SIRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
2936 BitVector Reserved(getNumRegs());
30 Reserved.set(AMDGPU::EXEC);
31
32 // EXEC_LO and EXEC_HI could be allocated and used as regular register,
33 // but this seems likely to result in bugs, so I'm marking them as reserved.
34 Reserved.set(AMDGPU::EXEC_LO);
35 Reserved.set(AMDGPU::EXEC_HI);
36
3737 Reserved.set(AMDGPU::INDIRECT_BASE_ADDR);
38 Reserved.set(AMDGPU::FLAT_SCR);
39 Reserved.set(AMDGPU::FLAT_SCR_LO);
40 Reserved.set(AMDGPU::FLAT_SCR_HI);
38
39 // EXEC_LO and EXEC_HI could be allocated and used as regular register, but
40 // this seems likely to result in bugs, so I'm marking them as reserved.
41 reserveRegisterTuples(Reserved, AMDGPU::EXEC);
42 reserveRegisterTuples(Reserved, AMDGPU::FLAT_SCR);
4143
4244 // Reserve some VGPRs to use as temp registers in case we have to spill VGPRs
43 Reserved.set(AMDGPU::VGPR255);
44 Reserved.set(AMDGPU::VGPR254);
45 reserveRegisterTuples(Reserved, AMDGPU::VGPR254);
46 reserveRegisterTuples(Reserved, AMDGPU::VGPR255);
4547
4648 // Tonga and Iceland can only allocate a fixed number of SGPRs due
4749 // to a hw bug.
5355
5456 for (unsigned i = Limit; i < NumSGPRs; ++i) {
5557 unsigned Reg = AMDGPU::SGPR_32RegClass.getRegister(i);
56 MCRegAliasIterator R = MCRegAliasIterator(Reg, this, true);
57
58 for (; R.isValid(); ++R)
59 Reserved.set(*R);
58 reserveRegisterTuples(Reserved, Reg);
6059 }
6160 }
6261
2222 namespace llvm {
2323
2424 struct SIRegisterInfo : public AMDGPURegisterInfo {
25 private:
26 void reserveRegisterTuples(BitVector &, unsigned Reg) const;
2527
28 public:
2629 SIRegisterInfo();
2730
2831 BitVector getReservedRegs(const MachineFunction &MF) const override;