llvm.org GIT mirror llvm / 24a3cc4
Fix for PR1306. - A register def / use now implicitly affects sub-register liveness but does not affect liveness information of super-registers. - Def of a larger register (if followed by a use later) is treated as read/mod/write of a smaller register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36434 91177308-0d34-0410-b5e6-96231b3b80d8 Evan Cheng 13 years ago
4 changed file(s) with 210 addition(s) and 60 deletion(s). Raw diff Collapse all Expand all
254254 /// handleLiveInRegister - Create interval for a livein register.
255255 void handleLiveInRegister(MachineBasicBlock* mbb,
256256 unsigned MIIdx,
257 LiveInterval &interval);
257 LiveInterval &interval, bool isAlias = false);
258258
259259 /// Return true if the two specified registers belong to different
260260 /// register classes. The registers may be either phys or virt regs.
123123
124124 const MRegisterInfo *RegInfo;
125125
126 MachineInstr **PhysRegInfo;
127 bool *PhysRegUsed;
126 // PhysRegInfo - Keep track of which instruction was the last def/use of a
127 // physical register. This is a purely local property, because all physical
128 // register references as presumed dead across basic blocks.
129 std::vector PhysRegInfo;
130
131 // PhysRegUsed - Keep track whether the physical register has been used after
132 // its last definition. This is local property.
133 BitVector PhysRegUsed;
134
135 // PhysRegPartDef - Keep track of a list of instructions which "partially"
136 // defined the physical register (e.g. on X86 AX partially defines EAX).
137 // These are turned into use/mod/write if there is a use of the register
138 // later in the same block. This is local property.
139 std::vector > PhysRegPartDef;
140
141 // PhysRegPartUse - Keep track of which instruction was the last partial use
142 // of a physical register (e.g. on X86 a def of EAX followed by a use of AX).
143 // This is a purely local property.
144 std::vector PhysRegPartUse;
128145
129146 typedef std::map
130147 std::vector > PHIVarInfoMap;
674674 exit:
675675 assert(start < end && "did not find end of interval?");
676676
677 LiveRange LR(start, end, interval.getNextValue(SrcReg != 0 ? start : ~0U,
678 SrcReg));
677 // Already exists? Extend old live interval.
678 LiveInterval::iterator OldLR = interval.FindLiveRangeContaining(start);
679 unsigned Id = (OldLR != interval.end())
680 ? OldLR->ValId
681 : interval.getNextValue(SrcReg != 0 ? start : ~0U, SrcReg);
682 LiveRange LR(start, end, Id);
679683 interval.addRange(LR);
680684 DOUT << " +" << LR << '\n';
681685 }
691695 if (!tii_->isMoveInstr(*MI, SrcReg, DstReg))
692696 SrcReg = 0;
693697 handlePhysicalRegisterDef(MBB, MI, MIIdx, getOrCreateInterval(reg), SrcReg);
694 for (const unsigned* AS = mri_->getAliasSet(reg); *AS; ++AS)
695 handlePhysicalRegisterDef(MBB, MI, MIIdx, getOrCreateInterval(*AS), 0);
698 // Def of a register also defines its sub-registers.
699 for (const unsigned* AS = mri_->getSubRegisters(reg); *AS; ++AS)
700 // Avoid processing some defs more than once.
701 if (!MI->findRegisterDefOperand(*AS))
702 handlePhysicalRegisterDef(MBB, MI, MIIdx, getOrCreateInterval(*AS), 0);
696703 }
697704 }
698705
699706 void LiveIntervals::handleLiveInRegister(MachineBasicBlock *MBB,
700707 unsigned MIIdx,
701 LiveInterval &interval) {
708 LiveInterval &interval, bool isAlias) {
702709 DOUT << "\t\tlivein register: "; DEBUG(printRegName(interval.reg));
703710
704711 // Look for kills, if it reaches a def before it's killed, then it shouldn't
727734 }
728735
729736 exit:
737 // Alias of a live-in register might not be used at all.
738 if (isAlias && end == 0) {
739 DOUT << " dead";
740 end = getDefIndex(start) + 1;
741 }
742
730743 assert(start < end && "did not find end of interval?");
731744
732745 LiveRange LR(start, end, interval.getNextValue(~0U, 0));
756769 for (MachineBasicBlock::const_livein_iterator LI = MBB->livein_begin(),
757770 LE = MBB->livein_end(); LI != LE; ++LI) {
758771 handleLiveInRegister(MBB, MIIndex, getOrCreateInterval(*LI));
759 for (const unsigned* AS = mri_->getAliasSet(*LI); *AS; ++AS)
760 handleLiveInRegister(MBB, MIIndex, getOrCreateInterval(*AS));
772 // Multiple live-ins can alias the same register.
773 for (const unsigned* AS = mri_->getSubRegisters(*LI); *AS; ++AS)
774 if (!hasInterval(*AS))
775 handleLiveInRegister(MBB, MIIndex, getOrCreateInterval(*AS), true);
761776 }
762777 }
763778
855870 // If the IntB live range is assigned to a physical register, and if that
856871 // physreg has aliases,
857872 if (MRegisterInfo::isPhysicalRegister(IntB.reg)) {
858 for (const unsigned *AS = mri_->getAliasSet(IntB.reg); *AS; ++AS) {
873 // Update the liveintervals of sub-registers.
874 for (const unsigned *AS = mri_->getSubRegisters(IntB.reg); *AS; ++AS) {
859875 LiveInterval &AliasLI = getInterval(*AS);
860876 AliasLI.addRange(LiveRange(FillerStart, FillerEnd,
861877 AliasLI.getNextValue(~0U, 0)));
10541070 // we have to update any aliased register's live ranges to indicate that they
10551071 // have clobbered values for this range.
10561072 if (MRegisterInfo::isPhysicalRegister(repDstReg)) {
1057 for (const unsigned *AS = mri_->getAliasSet(repDstReg); *AS; ++AS)
1058 getInterval(*AS).MergeInClobberRanges(SrcInt);
1073 // Update the liveintervals of sub-registers.
1074 for (const unsigned *AS = mri_->getSubRegisters(repDstReg); *AS; ++AS)
1075 getInterval(*AS).MergeInClobberRanges(SrcInt);
10591076 } else {
10601077 // Merge use info if the destination is a virtual register.
10611078 LiveVariables::VarInfo& dVI = lv_->getVarInfo(repDstReg);
12781295 SmallVector LHSValNoAssignments;
12791296 SmallVector RHSValNoAssignments;
12801297 SmallVector, 16> ValueNumberInfo;
1298
1299 // If a live interval is a physical register, conservatively check if any
1300 // of its sub-registers is overlapping the live interval of the virtual
1301 // register. If so, do not coalesce.
1302 if (MRegisterInfo::isPhysicalRegister(LHS.reg) &&
1303 *mri_->getSubRegisters(LHS.reg)) {
1304 for (const unsigned* SR = mri_->getSubRegisters(LHS.reg); *SR; ++SR)
1305 if (hasInterval(*SR) && RHS.overlaps(getInterval(*SR))) {
1306 DOUT << "Interfere with sub-register ";
1307 DEBUG(getInterval(*SR).print(DOUT, mri_));
1308 return false;
1309 }
1310 } else if (MRegisterInfo::isPhysicalRegister(RHS.reg) &&
1311 *mri_->getSubRegisters(RHS.reg)) {
1312 for (const unsigned* SR = mri_->getSubRegisters(RHS.reg); *SR; ++SR)
1313 if (hasInterval(*SR) && LHS.overlaps(getInterval(*SR))) {
1314 DOUT << "Interfere with sub-register ";
1315 DEBUG(getInterval(*SR).print(DOUT, mri_));
1316 return false;
1317 }
1318 }
12811319
12821320 // Compute ultimate value numbers for the LHS and RHS values.
12831321 if (RHS.containsOneValue()) {
7676 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
7777 MachineOperand &MO = MI->getOperand(i);
7878 if (MO.isReg() && MO.isKill()) {
79 if (RegInfo->regsOverlap(Reg, MO.getReg()))
79 if ((MO.getReg() == Reg) ||
80 (MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
81 MRegisterInfo::isPhysicalRegister(Reg) &&
82 RegInfo->isSubRegister(MO.getReg(), Reg)))
8083 return true;
8184 }
8285 }
8689 bool LiveVariables::RegisterDefIsDead(MachineInstr *MI, unsigned Reg) const {
8790 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
8891 MachineOperand &MO = MI->getOperand(i);
89 if (MO.isReg() && MO.isDead())
90 if (RegInfo->regsOverlap(Reg, MO.getReg()))
92 if (MO.isReg() && MO.isDead()) {
93 if ((MO.getReg() == Reg) ||
94 (MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
95 MRegisterInfo::isPhysicalRegister(Reg) &&
96 RegInfo->isSubRegister(MO.getReg(), Reg)))
9197 return true;
98 }
9299 }
93100 return false;
94101 }
96103 bool LiveVariables::ModifiesRegister(MachineInstr *MI, unsigned Reg) const {
97104 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
98105 MachineOperand &MO = MI->getOperand(i);
99 if (MO.isReg() && MO.isDef()) {
100 if (RegInfo->regsOverlap(Reg, MO.getReg()))
101 return true;
102 }
106 if (MO.isReg() && MO.isDef() && MO.getReg() == Reg)
107 return true;
103108 }
104109 return false;
105110 }
165170 }
166171
167172 void LiveVariables::addRegisterKilled(unsigned IncomingReg, MachineInstr *MI) {
168 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
169 MachineOperand &MO = MI->getOperand(i);
170 if (MO.isReg() && MO.isUse() && MO.getReg() == IncomingReg) {
171 MO.setIsKill();
172 break;
173 }
174 }
173 bool Found = false;
174 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
175 MachineOperand &MO = MI->getOperand(i);
176 if (MO.isReg() && MO.isUse()) {
177 unsigned Reg = MO.getReg();
178 if (!Reg)
179 continue;
180 if (Reg == IncomingReg) {
181 MO.setIsKill();
182 Found = true;
183 break;
184 } else if (MRegisterInfo::isPhysicalRegister(Reg) &&
185 MRegisterInfo::isPhysicalRegister(IncomingReg) &&
186 RegInfo->isSuperRegister(IncomingReg, Reg) &&
187 MO.isKill())
188 // A super-register kill already exists.
189 return;
190 }
191 }
192
193 // If not found, this means an alias of one of the operand is killed. Add a
194 // new implicit operand.
195 if (!Found)
196 MI->addRegOperand(IncomingReg, false/*IsDef*/,true/*IsImp*/,true/*IsKill*/);
175197 }
176198
177199 void LiveVariables::addRegisterDead(unsigned IncomingReg, MachineInstr *MI) {
178 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
179 MachineOperand &MO = MI->getOperand(i);
180 if (MO.isReg() && MO.isDef() && MO.getReg() == IncomingReg) {
181 MO.setIsDead();
182 break;
183 }
184 }
200 bool Found = false;
201 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
202 MachineOperand &MO = MI->getOperand(i);
203 if (MO.isReg() && MO.isDef()) {
204 unsigned Reg = MO.getReg();
205 if (!Reg)
206 continue;
207 if (Reg == IncomingReg) {
208 MO.setIsDead();
209 Found = true;
210 break;
211 } else if (MRegisterInfo::isPhysicalRegister(Reg) &&
212 MRegisterInfo::isPhysicalRegister(IncomingReg) &&
213 RegInfo->isSuperRegister(IncomingReg, Reg) &&
214 MO.isDead())
215 // There exists a super-register that's marked dead.
216 return;
217 }
218 }
219
220 // If not found, this means an alias of one of the operand is dead. Add a
221 // new implicit operand.
222 if (!Found)
223 MI->addRegOperand(IncomingReg, true/*IsDef*/,true/*IsImp*/,false/*IsKill*/,
224 true/*IsDead*/);
185225 }
186226
187227 void LiveVariables::HandlePhysRegUse(unsigned Reg, MachineInstr *MI) {
228 // There is a now a proper use, forget about the last partial use.
229 PhysRegPartUse[Reg] = NULL;
230
231 // Turn previous partial def's into read/mod/write.
232 for (unsigned i = 0, e = PhysRegPartDef[Reg].size(); i != e; ++i) {
233 MachineInstr *Def = PhysRegPartDef[Reg][i];
234 // First one is just a def. This means the use is reading some undef bits.
235 if (i != 0)
236 Def->addRegOperand(Reg, false/*IsDef*/,true/*IsImp*/,true/*IsKill*/);
237 Def->addRegOperand(Reg, true/*IsDef*/,true/*IsImp*/);
238 }
239 PhysRegPartDef[Reg].clear();
240
241 // There was an earlier def of a super-register. Add implicit def to that MI.
242 // A: EAX = ...
243 // B: = AX
244 // Add implicit def to A.
245 if (PhysRegInfo[Reg] && !PhysRegUsed[Reg]) {
246 MachineInstr *Def = PhysRegInfo[Reg];
247 if (!Def->findRegisterDefOperand(Reg))
248 Def->addRegOperand(Reg, true/*IsDef*/,true/*IsImp*/);
249 }
250
188251 PhysRegInfo[Reg] = MI;
189252 PhysRegUsed[Reg] = true;
190253
191 for (const unsigned *AliasSet = RegInfo->getAliasSet(Reg);
192 unsigned Alias = *AliasSet; ++AliasSet) {
193 PhysRegInfo[Alias] = MI;
194 PhysRegUsed[Alias] = true;
195 }
254 for (const unsigned *SubRegs = RegInfo->getSubRegisters(Reg);
255 unsigned SubReg = *SubRegs; ++SubRegs) {
256 PhysRegInfo[SubReg] = MI;
257 PhysRegUsed[SubReg] = true;
258 }
259
260 // Remember the partial uses.
261 for (const unsigned *SuperRegs = RegInfo->getSuperRegisters(Reg);
262 unsigned SuperReg = *SuperRegs; ++SuperRegs)
263 PhysRegPartUse[SuperReg] = MI;
196264 }
197265
198266 void LiveVariables::HandlePhysRegDef(unsigned Reg, MachineInstr *MI) {
199267 // Does this kill a previous version of this register?
200 if (MachineInstr *LastUse = PhysRegInfo[Reg]) {
268 if (MachineInstr *LastRef = PhysRegInfo[Reg]) {
201269 if (PhysRegUsed[Reg])
202 addRegisterKilled(Reg, LastUse);
270 addRegisterKilled(Reg, LastRef);
271 else if (PhysRegPartUse[Reg])
272 // Add implicit use / kill to last use of a sub-register.
273 addRegisterKilled(Reg, PhysRegPartUse[Reg]);
203274 else
204 addRegisterDead(Reg, LastUse);
275 addRegisterDead(Reg, LastRef);
205276 }
206277 PhysRegInfo[Reg] = MI;
207278 PhysRegUsed[Reg] = false;
208
209 for (const unsigned *AliasSet = RegInfo->getAliasSet(Reg);
210 unsigned Alias = *AliasSet; ++AliasSet) {
211 if (MachineInstr *LastUse = PhysRegInfo[Alias]) {
212 if (PhysRegUsed[Alias])
213 addRegisterKilled(Alias, LastUse);
279 PhysRegPartUse[Reg] = NULL;
280
281 for (const unsigned *SubRegs = RegInfo->getSubRegisters(Reg);
282 unsigned SubReg = *SubRegs; ++SubRegs) {
283 if (MachineInstr *LastRef = PhysRegInfo[SubReg]) {
284 if (PhysRegUsed[SubReg])
285 addRegisterKilled(SubReg, LastRef);
286 else if (PhysRegPartUse[SubReg])
287 // Add implicit use / kill to last use of a sub-register.
288 addRegisterKilled(SubReg, PhysRegPartUse[SubReg]);
214289 else
215 addRegisterDead(Alias, LastUse);
216 }
217 PhysRegInfo[Alias] = MI;
218 PhysRegUsed[Alias] = false;
290 addRegisterDead(SubReg, LastRef);
291 }
292 PhysRegInfo[SubReg] = MI;
293 PhysRegUsed[SubReg] = false;
294 }
295
296 if (MI)
297 for (const unsigned *SuperRegs = RegInfo->getSuperRegisters(Reg);
298 unsigned SuperReg = *SuperRegs; ++SuperRegs) {
299 if (PhysRegInfo[SuperReg]) {
300 // The larger register is previously defined. Now a smaller part is
301 // being re-defined. Treat it as read/mod/write.
302 // EAX =
303 // AX = EAX, EAX
304 MI->addRegOperand(SuperReg, false/*IsDef*/,true/*IsImp*/,true/*IsKill*/);
305 MI->addRegOperand(SuperReg, true/*IsDef*/,true/*IsImp*/);
306 PhysRegInfo[SuperReg] = MI;
307 PhysRegUsed[SuperReg] = false;
308 } else {
309 // Remember this partial def.
310 PhysRegPartDef[SuperReg].push_back(MI);
311 }
219312 }
220313 }
221314
227320
228321 ReservedRegisters = RegInfo->getReservedRegs(mf);
229322
230 // PhysRegInfo - Keep track of which instruction was the last use of a
231 // physical register. This is a purely local property, because all physical
232 // register references as presumed dead across basic blocks.
233 //
234 PhysRegInfo = (MachineInstr**)alloca(sizeof(MachineInstr*) *
235 RegInfo->getNumRegs());
236 PhysRegUsed = (bool*)alloca(sizeof(bool)*RegInfo->getNumRegs());
237 std::fill(PhysRegInfo, PhysRegInfo+RegInfo->getNumRegs(), (MachineInstr*)0);
323 PhysRegInfo.resize(RegInfo->getNumRegs(), (MachineInstr*)NULL);
324 PhysRegUsed.resize(RegInfo->getNumRegs());
325 PhysRegPartDef.resize(RegInfo->getNumRegs());
326 PhysRegPartUse.resize(RegInfo->getNumRegs(), (MachineInstr*)NULL);
238327
239328 /// Get some space for a respectable number of registers...
240329 VirtRegInfo.resize(64);
341430 for (unsigned i = 0, e = RegInfo->getNumRegs(); i != e; ++i)
342431 if (PhysRegInfo[i])
343432 HandlePhysRegDef(i, 0);
433
434 // Clear some states between BB's. These are purely local information.
435 for (unsigned i = 0, e = RegInfo->getNumRegs(); i != e; ++i) {
436 PhysRegPartDef[i].clear();
437 PhysRegPartUse[i] = NULL;
438 }
344439 }
345440
346441 // Convert and transfer the dead / killed information we have gathered into