llvm.org GIT mirror llvm / 24802f3
Fix Incorrect CHECK message [0-31]+ in test case. In regular expression, [0-31]+ equals to [0-3]+, not the number from 0 to 31. So change it to [0-9]+. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197113 91177308-0d34-0410-b5e6-96231b3b80d8 Kevin Qin 6 years ago
16 changed file(s) with 323 addition(s) and 323 deletion(s). Raw diff Collapse all Expand all
0 ; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s
11
22 define <8 x i8> @add8xi8(<8 x i8> %A, <8 x i8> %B) {
3 ;CHECK: add {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
3 ;CHECK: add {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
44 %tmp3 = add <8 x i8> %A, %B;
55 ret <8 x i8> %tmp3
66 }
77
88 define <16 x i8> @add16xi8(<16 x i8> %A, <16 x i8> %B) {
9 ;CHECK: add {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
9 ;CHECK: add {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1010 %tmp3 = add <16 x i8> %A, %B;
1111 ret <16 x i8> %tmp3
1212 }
1313
1414 define <4 x i16> @add4xi16(<4 x i16> %A, <4 x i16> %B) {
15 ;CHECK: add {{v[0-31]+}}.4h, {{v[0-31]+}}.4h, {{v[0-31]+}}.4h
15 ;CHECK: add {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
1616 %tmp3 = add <4 x i16> %A, %B;
1717 ret <4 x i16> %tmp3
1818 }
1919
2020 define <8 x i16> @add8xi16(<8 x i16> %A, <8 x i16> %B) {
21 ;CHECK: add {{v[0-31]+}}.8h, {{v[0-31]+}}.8h, {{v[0-31]+}}.8h
21 ;CHECK: add {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
2222 %tmp3 = add <8 x i16> %A, %B;
2323 ret <8 x i16> %tmp3
2424 }
2525
2626 define <2 x i32> @add2xi32(<2 x i32> %A, <2 x i32> %B) {
27 ;CHECK: add {{v[0-31]+}}.2s, {{v[0-31]+}}.2s, {{v[0-31]+}}.2s
27 ;CHECK: add {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
2828 %tmp3 = add <2 x i32> %A, %B;
2929 ret <2 x i32> %tmp3
3030 }
3131
3232 define <4 x i32> @add4x32(<4 x i32> %A, <4 x i32> %B) {
33 ;CHECK: add {{v[0-31]+}}.4s, {{v[0-31]+}}.4s, {{v[0-31]+}}.4s
33 ;CHECK: add {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
3434 %tmp3 = add <4 x i32> %A, %B;
3535 ret <4 x i32> %tmp3
3636 }
3737
3838 define <2 x i64> @add2xi64(<2 x i64> %A, <2 x i64> %B) {
39 ;CHECK: add {{v[0-31]+}}.2d, {{v[0-31]+}}.2d, {{v[0-31]+}}.2d
39 ;CHECK: add {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
4040 %tmp3 = add <2 x i64> %A, %B;
4141 ret <2 x i64> %tmp3
4242 }
4343
4444 define <2 x float> @add2xfloat(<2 x float> %A, <2 x float> %B) {
45 ;CHECK: fadd {{v[0-31]+}}.2s, {{v[0-31]+}}.2s, {{v[0-31]+}}.2s
45 ;CHECK: fadd {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
4646 %tmp3 = fadd <2 x float> %A, %B;
4747 ret <2 x float> %tmp3
4848 }
4949
5050 define <4 x float> @add4xfloat(<4 x float> %A, <4 x float> %B) {
51 ;CHECK: fadd {{v[0-31]+}}.4s, {{v[0-31]+}}.4s, {{v[0-31]+}}.4s
51 ;CHECK: fadd {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
5252 %tmp3 = fadd <4 x float> %A, %B;
5353 ret <4 x float> %tmp3
5454 }
5555 define <2 x double> @add2xdouble(<2 x double> %A, <2 x double> %B) {
56 ;CHECK: add {{v[0-31]+}}.2d, {{v[0-31]+}}.2d, {{v[0-31]+}}.2d
56 ;CHECK: add {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
5757 %tmp3 = fadd <2 x double> %A, %B;
5858 ret <2 x double> %tmp3
5959 }
6060
6161 define <8 x i8> @sub8xi8(<8 x i8> %A, <8 x i8> %B) {
62 ;CHECK: sub {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
62 ;CHECK: sub {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
6363 %tmp3 = sub <8 x i8> %A, %B;
6464 ret <8 x i8> %tmp3
6565 }
6666
6767 define <16 x i8> @sub16xi8(<16 x i8> %A, <16 x i8> %B) {
68 ;CHECK: sub {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
68 ;CHECK: sub {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
6969 %tmp3 = sub <16 x i8> %A, %B;
7070 ret <16 x i8> %tmp3
7171 }
7272
7373 define <4 x i16> @sub4xi16(<4 x i16> %A, <4 x i16> %B) {
74 ;CHECK: sub {{v[0-31]+}}.4h, {{v[0-31]+}}.4h, {{v[0-31]+}}.4h
74 ;CHECK: sub {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
7575 %tmp3 = sub <4 x i16> %A, %B;
7676 ret <4 x i16> %tmp3
7777 }
7878
7979 define <8 x i16> @sub8xi16(<8 x i16> %A, <8 x i16> %B) {
80 ;CHECK: sub {{v[0-31]+}}.8h, {{v[0-31]+}}.8h, {{v[0-31]+}}.8h
80 ;CHECK: sub {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
8181 %tmp3 = sub <8 x i16> %A, %B;
8282 ret <8 x i16> %tmp3
8383 }
8484
8585 define <2 x i32> @sub2xi32(<2 x i32> %A, <2 x i32> %B) {
86 ;CHECK: sub {{v[0-31]+}}.2s, {{v[0-31]+}}.2s, {{v[0-31]+}}.2s
86 ;CHECK: sub {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
8787 %tmp3 = sub <2 x i32> %A, %B;
8888 ret <2 x i32> %tmp3
8989 }
9090
9191 define <4 x i32> @sub4x32(<4 x i32> %A, <4 x i32> %B) {
92 ;CHECK: sub {{v[0-31]+}}.4s, {{v[0-31]+}}.4s, {{v[0-31]+}}.4s
92 ;CHECK: sub {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
9393 %tmp3 = sub <4 x i32> %A, %B;
9494 ret <4 x i32> %tmp3
9595 }
9696
9797 define <2 x i64> @sub2xi64(<2 x i64> %A, <2 x i64> %B) {
98 ;CHECK: sub {{v[0-31]+}}.2d, {{v[0-31]+}}.2d, {{v[0-31]+}}.2d
98 ;CHECK: sub {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
9999 %tmp3 = sub <2 x i64> %A, %B;
100100 ret <2 x i64> %tmp3
101101 }
102102
103103 define <2 x float> @sub2xfloat(<2 x float> %A, <2 x float> %B) {
104 ;CHECK: fsub {{v[0-31]+}}.2s, {{v[0-31]+}}.2s, {{v[0-31]+}}.2s
104 ;CHECK: fsub {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
105105 %tmp3 = fsub <2 x float> %A, %B;
106106 ret <2 x float> %tmp3
107107 }
108108
109109 define <4 x float> @sub4xfloat(<4 x float> %A, <4 x float> %B) {
110 ;CHECK: fsub {{v[0-31]+}}.4s, {{v[0-31]+}}.4s, {{v[0-31]+}}.4s
110 ;CHECK: fsub {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
111111 %tmp3 = fsub <4 x float> %A, %B;
112112 ret <4 x float> %tmp3
113113 }
114114 define <2 x double> @sub2xdouble(<2 x double> %A, <2 x double> %B) {
115 ;CHECK: sub {{v[0-31]+}}.2d, {{v[0-31]+}}.2d, {{v[0-31]+}}.2d
115 ;CHECK: sub {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
116116 %tmp3 = fsub <2 x double> %A, %B;
117117 ret <2 x double> %tmp3
118118 }
11
22
33 define <8 x i8> @and8xi8(<8 x i8> %a, <8 x i8> %b) {
4 ;CHECK: and {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
4 ;CHECK: and {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
55 %tmp1 = and <8 x i8> %a, %b;
66 ret <8 x i8> %tmp1
77 }
88
99 define <16 x i8> @and16xi8(<16 x i8> %a, <16 x i8> %b) {
10 ;CHECK: and {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
10 ;CHECK: and {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1111 %tmp1 = and <16 x i8> %a, %b;
1212 ret <16 x i8> %tmp1
1313 }
1414
1515
1616 define <8 x i8> @orr8xi8(<8 x i8> %a, <8 x i8> %b) {
17 ;CHECK: orr {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
17 ;CHECK: orr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
1818 %tmp1 = or <8 x i8> %a, %b;
1919 ret <8 x i8> %tmp1
2020 }
2121
2222 define <16 x i8> @orr16xi8(<16 x i8> %a, <16 x i8> %b) {
23 ;CHECK: orr {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
23 ;CHECK: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
2424 %tmp1 = or <16 x i8> %a, %b;
2525 ret <16 x i8> %tmp1
2626 }
2727
2828
2929 define <8 x i8> @xor8xi8(<8 x i8> %a, <8 x i8> %b) {
30 ;CHECK: eor {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
30 ;CHECK: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
3131 %tmp1 = xor <8 x i8> %a, %b;
3232 ret <8 x i8> %tmp1
3333 }
3434
3535 define <16 x i8> @xor16xi8(<16 x i8> %a, <16 x i8> %b) {
36 ;CHECK: eor {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
36 ;CHECK: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
3737 %tmp1 = xor <16 x i8> %a, %b;
3838 ret <16 x i8> %tmp1
3939 }
4040
4141 define <8 x i8> @bsl8xi8_const(<8 x i8> %a, <8 x i8> %b) {
42 ;CHECK: bsl {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
42 ;CHECK: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
4343 %tmp1 = and <8 x i8> %a, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
4444 %tmp2 = and <8 x i8> %b, < i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0 >
4545 %tmp3 = or <8 x i8> %tmp1, %tmp2
4747 }
4848
4949 define <16 x i8> @bsl16xi8_const(<16 x i8> %a, <16 x i8> %b) {
50 ;CHECK: bsl {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
50 ;CHECK: bsl {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
5151 %tmp1 = and <16 x i8> %a, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
5252 %tmp2 = and <16 x i8> %b, < i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0 >
5353 %tmp3 = or <16 x i8> %tmp1, %tmp2
5555 }
5656
5757 define <8 x i8> @orn8xi8(<8 x i8> %a, <8 x i8> %b) {
58 ;CHECK: orn {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
58 ;CHECK: orn {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
5959 %tmp1 = xor <8 x i8> %b, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
6060 %tmp2 = or <8 x i8> %a, %tmp1
6161 ret <8 x i8> %tmp2
6262 }
6363
6464 define <16 x i8> @orn16xi8(<16 x i8> %a, <16 x i8> %b) {
65 ;CHECK: orn {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
65 ;CHECK: orn {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
6666 %tmp1 = xor <16 x i8> %b, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
6767 %tmp2 = or <16 x i8> %a, %tmp1
6868 ret <16 x i8> %tmp2
6969 }
7070
7171 define <8 x i8> @bic8xi8(<8 x i8> %a, <8 x i8> %b) {
72 ;CHECK: bic {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
72 ;CHECK: bic {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
7373 %tmp1 = xor <8 x i8> %b, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
7474 %tmp2 = and <8 x i8> %a, %tmp1
7575 ret <8 x i8> %tmp2
7676 }
7777
7878 define <16 x i8> @bic16xi8(<16 x i8> %a, <16 x i8> %b) {
79 ;CHECK: bic {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
79 ;CHECK: bic {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
8080 %tmp1 = xor <16 x i8> %b, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
8181 %tmp2 = and <16 x i8> %a, %tmp1
8282 ret <16 x i8> %tmp2
8383 }
8484
8585 define <2 x i32> @orrimm2s_lsl0(<2 x i32> %a) {
86 ;CHECK: orr {{v[0-31]+}}.2s, #0xff
86 ;CHECK: orr {{v[0-9]+}}.2s, #0xff
8787 %tmp1 = or <2 x i32> %a, < i32 255, i32 255>
8888 ret <2 x i32> %tmp1
8989 }
9090
9191 define <2 x i32> @orrimm2s_lsl8(<2 x i32> %a) {
92 ;CHECK: orr {{v[0-31]+}}.2s, #0xff, lsl #8
92 ;CHECK: orr {{v[0-9]+}}.2s, #0xff, lsl #8
9393 %tmp1 = or <2 x i32> %a, < i32 65280, i32 65280>
9494 ret <2 x i32> %tmp1
9595 }
9696
9797 define <2 x i32> @orrimm2s_lsl16(<2 x i32> %a) {
98 ;CHECK: orr {{v[0-31]+}}.2s, #0xff, lsl #16
98 ;CHECK: orr {{v[0-9]+}}.2s, #0xff, lsl #16
9999 %tmp1 = or <2 x i32> %a, < i32 16711680, i32 16711680>
100100 ret <2 x i32> %tmp1
101101 }
102102
103103 define <2 x i32> @orrimm2s_lsl24(<2 x i32> %a) {
104 ;CHECK: orr {{v[0-31]+}}.2s, #0xff, lsl #24
104 ;CHECK: orr {{v[0-9]+}}.2s, #0xff, lsl #24
105105 %tmp1 = or <2 x i32> %a, < i32 4278190080, i32 4278190080>
106106 ret <2 x i32> %tmp1
107107 }
108108
109109 define <4 x i32> @orrimm4s_lsl0(<4 x i32> %a) {
110 ;CHECK: orr {{v[0-31]+}}.4s, #0xff
110 ;CHECK: orr {{v[0-9]+}}.4s, #0xff
111111 %tmp1 = or <4 x i32> %a, < i32 255, i32 255, i32 255, i32 255>
112112 ret <4 x i32> %tmp1
113113 }
114114
115115 define <4 x i32> @orrimm4s_lsl8(<4 x i32> %a) {
116 ;CHECK: orr {{v[0-31]+}}.4s, #0xff, lsl #8
116 ;CHECK: orr {{v[0-9]+}}.4s, #0xff, lsl #8
117117 %tmp1 = or <4 x i32> %a, < i32 65280, i32 65280, i32 65280, i32 65280>
118118 ret <4 x i32> %tmp1
119119 }
120120
121121 define <4 x i32> @orrimm4s_lsl16(<4 x i32> %a) {
122 ;CHECK: orr {{v[0-31]+}}.4s, #0xff, lsl #16
122 ;CHECK: orr {{v[0-9]+}}.4s, #0xff, lsl #16
123123 %tmp1 = or <4 x i32> %a, < i32 16711680, i32 16711680, i32 16711680, i32 16711680>
124124 ret <4 x i32> %tmp1
125125 }
126126
127127 define <4 x i32> @orrimm4s_lsl24(<4 x i32> %a) {
128 ;CHECK: orr {{v[0-31]+}}.4s, #0xff, lsl #24
128 ;CHECK: orr {{v[0-9]+}}.4s, #0xff, lsl #24
129129 %tmp1 = or <4 x i32> %a, < i32 4278190080, i32 4278190080, i32 4278190080, i32 4278190080>
130130 ret <4 x i32> %tmp1
131131 }
132132
133133 define <4 x i16> @orrimm4h_lsl0(<4 x i16> %a) {
134 ;CHECK: orr {{v[0-31]+}}.4h, #0xff
134 ;CHECK: orr {{v[0-9]+}}.4h, #0xff
135135 %tmp1 = or <4 x i16> %a, < i16 255, i16 255, i16 255, i16 255 >
136136 ret <4 x i16> %tmp1
137137 }
138138
139139 define <4 x i16> @orrimm4h_lsl8(<4 x i16> %a) {
140 ;CHECK: orr {{v[0-31]+}}.4h, #0xff, lsl #8
140 ;CHECK: orr {{v[0-9]+}}.4h, #0xff, lsl #8
141141 %tmp1 = or <4 x i16> %a, < i16 65280, i16 65280, i16 65280, i16 65280 >
142142 ret <4 x i16> %tmp1
143143 }
144144
145145 define <8 x i16> @orrimm8h_lsl0(<8 x i16> %a) {
146 ;CHECK: orr {{v[0-31]+}}.8h, #0xff
146 ;CHECK: orr {{v[0-9]+}}.8h, #0xff
147147 %tmp1 = or <8 x i16> %a, < i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255 >
148148 ret <8 x i16> %tmp1
149149 }
150150
151151 define <8 x i16> @orrimm8h_lsl8(<8 x i16> %a) {
152 ;CHECK: orr {{v[0-31]+}}.8h, #0xff, lsl #8
152 ;CHECK: orr {{v[0-9]+}}.8h, #0xff, lsl #8
153153 %tmp1 = or <8 x i16> %a, < i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280 >
154154 ret <8 x i16> %tmp1
155155 }
156156
157157 define <2 x i32> @bicimm2s_lsl0(<2 x i32> %a) {
158 ;CHECK: bic {{v[0-31]+}}.2s, #0x10
158 ;CHECK: bic {{v[0-9]+}}.2s, #0x10
159159 %tmp1 = and <2 x i32> %a, < i32 4294967279, i32 4294967279 >
160160 ret <2 x i32> %tmp1
161161 }
162162
163163 define <2 x i32> @bicimm2s_lsl8(<2 x i32> %a) {
164 ;CHECK: bic {{v[0-31]+}}.2s, #0x10, lsl #8
164 ;CHECK: bic {{v[0-9]+}}.2s, #0x10, lsl #8
165165 %tmp1 = and <2 x i32> %a, < i32 18446744073709547519, i32 18446744073709547519 >
166166 ret <2 x i32> %tmp1
167167 }
168168
169169 define <2 x i32> @bicimm2s_lsl16(<2 x i32> %a) {
170 ;CHECK: bic {{v[0-31]+}}.2s, #0x10, lsl #16
170 ;CHECK: bic {{v[0-9]+}}.2s, #0x10, lsl #16
171171 %tmp1 = and <2 x i32> %a, < i32 18446744073708503039, i32 18446744073708503039 >
172172 ret <2 x i32> %tmp1
173173 }
174174
175175 define <2 x i32> @bicimm2s_lsl124(<2 x i32> %a) {
176 ;CHECK: bic {{v[0-31]+}}.2s, #0x10, lsl #24
176 ;CHECK: bic {{v[0-9]+}}.2s, #0x10, lsl #24
177177 %tmp1 = and <2 x i32> %a, < i32 18446744073441116159, i32 18446744073441116159>
178178 ret <2 x i32> %tmp1
179179 }
180180
181181 define <4 x i32> @bicimm4s_lsl0(<4 x i32> %a) {
182 ;CHECK: bic {{v[0-31]+}}.4s, #0x10
182 ;CHECK: bic {{v[0-9]+}}.4s, #0x10
183183 %tmp1 = and <4 x i32> %a, < i32 4294967279, i32 4294967279, i32 4294967279, i32 4294967279 >
184184 ret <4 x i32> %tmp1
185185 }
186186
187187 define <4 x i32> @bicimm4s_lsl8(<4 x i32> %a) {
188 ;CHECK: bic {{v[0-31]+}}.4s, #0x10, lsl #8
188 ;CHECK: bic {{v[0-9]+}}.4s, #0x10, lsl #8
189189 %tmp1 = and <4 x i32> %a, < i32 18446744073709547519, i32 18446744073709547519, i32 18446744073709547519, i32 18446744073709547519 >
190190 ret <4 x i32> %tmp1
191191 }
192192
193193 define <4 x i32> @bicimm4s_lsl16(<4 x i32> %a) {
194 ;CHECK: bic {{v[0-31]+}}.4s, #0x10, lsl #16
194 ;CHECK: bic {{v[0-9]+}}.4s, #0x10, lsl #16
195195 %tmp1 = and <4 x i32> %a, < i32 18446744073708503039, i32 18446744073708503039, i32 18446744073708503039, i32 18446744073708503039 >
196196 ret <4 x i32> %tmp1
197197 }
198198
199199 define <4 x i32> @bicimm4s_lsl124(<4 x i32> %a) {
200 ;CHECK: bic {{v[0-31]+}}.4s, #0x10, lsl #24
200 ;CHECK: bic {{v[0-9]+}}.4s, #0x10, lsl #24
201201 %tmp1 = and <4 x i32> %a, < i32 18446744073441116159, i32 18446744073441116159, i32 18446744073441116159, i32 18446744073441116159>
202202 ret <4 x i32> %tmp1
203203 }
204204
205205 define <4 x i16> @bicimm4h_lsl0_a(<4 x i16> %a) {
206 ;CHECK: bic {{v[0-31]+}}.4h, #0x10
206 ;CHECK: bic {{v[0-9]+}}.4h, #0x10
207207 %tmp1 = and <4 x i16> %a, < i16 18446744073709551599, i16 18446744073709551599, i16 18446744073709551599, i16 18446744073709551599 >
208208 ret <4 x i16> %tmp1
209209 }
210210
211211 define <4 x i16> @bicimm4h_lsl0_b(<4 x i16> %a) {
212 ;CHECK: bic {{v[0-31]+}}.4h, #0x0
212 ;CHECK: bic {{v[0-9]+}}.4h, #0x0
213213 %tmp1 = and <4 x i16> %a, < i16 65280, i16 65280, i16 65280, i16 65280 >
214214 ret <4 x i16> %tmp1
215215 }
216216
217217 define <4 x i16> @bicimm4h_lsl8_a(<4 x i16> %a) {
218 ;CHECK: bic {{v[0-31]+}}.4h, #0x10, lsl #8
218 ;CHECK: bic {{v[0-9]+}}.4h, #0x10, lsl #8
219219 %tmp1 = and <4 x i16> %a, < i16 18446744073709547519, i16 18446744073709547519, i16 18446744073709547519, i16 18446744073709547519>
220220 ret <4 x i16> %tmp1
221221 }
222222
223223 define <4 x i16> @bicimm4h_lsl8_b(<4 x i16> %a) {
224 ;CHECK: bic {{v[0-31]+}}.4h, #0x0, lsl #8
224 ;CHECK: bic {{v[0-9]+}}.4h, #0x0, lsl #8
225225 %tmp1 = and <4 x i16> %a, < i16 255, i16 255, i16 255, i16 255>
226226 ret <4 x i16> %tmp1
227227 }
228228
229229 define <8 x i16> @bicimm8h_lsl0_a(<8 x i16> %a) {
230 ;CHECK: bic {{v[0-31]+}}.8h, #0x10
230 ;CHECK: bic {{v[0-9]+}}.8h, #0x10
231231 %tmp1 = and <8 x i16> %a, < i16 18446744073709551599, i16 18446744073709551599, i16 18446744073709551599, i16 18446744073709551599,
232232 i16 18446744073709551599, i16 18446744073709551599, i16 18446744073709551599, i16 18446744073709551599 >
233233 ret <8 x i16> %tmp1
234234 }
235235
236236 define <8 x i16> @bicimm8h_lsl0_b(<8 x i16> %a) {
237 ;CHECK: bic {{v[0-31]+}}.8h, #0x0
237 ;CHECK: bic {{v[0-9]+}}.8h, #0x0
238238 %tmp1 = and <8 x i16> %a, < i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280 >
239239 ret <8 x i16> %tmp1
240240 }
241241
242242 define <8 x i16> @bicimm8h_lsl8_a(<8 x i16> %a) {
243 ;CHECK: bic {{v[0-31]+}}.8h, #0x10, lsl #8
243 ;CHECK: bic {{v[0-9]+}}.8h, #0x10, lsl #8
244244 %tmp1 = and <8 x i16> %a, < i16 18446744073709547519, i16 18446744073709547519, i16 18446744073709547519, i16 18446744073709547519,
245245 i16 18446744073709547519, i16 18446744073709547519, i16 18446744073709547519, i16 18446744073709547519>
246246 ret <8 x i16> %tmp1
247247 }
248248
249249 define <8 x i16> @bicimm8h_lsl8_b(<8 x i16> %a) {
250 ;CHECK: bic {{v[0-31]+}}.8h, #0x0, lsl #8
250 ;CHECK: bic {{v[0-9]+}}.8h, #0x0, lsl #8
251251 %tmp1 = and <8 x i16> %a, < i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
252252 ret <8 x i16> %tmp1
253253 }
254254
255255 define <2 x i32> @and2xi32(<2 x i32> %a, <2 x i32> %b) {
256 ;CHECK: and {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
256 ;CHECK: and {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
257257 %tmp1 = and <2 x i32> %a, %b;
258258 ret <2 x i32> %tmp1
259259 }
260260
261261 define <4 x i16> @and4xi16(<4 x i16> %a, <4 x i16> %b) {
262 ;CHECK: and {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
262 ;CHECK: and {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
263263 %tmp1 = and <4 x i16> %a, %b;
264264 ret <4 x i16> %tmp1
265265 }
266266
267267 define <1 x i64> @and1xi64(<1 x i64> %a, <1 x i64> %b) {
268 ;CHECK: and {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
268 ;CHECK: and {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
269269 %tmp1 = and <1 x i64> %a, %b;
270270 ret <1 x i64> %tmp1
271271 }
272272
273273 define <4 x i32> @and4xi32(<4 x i32> %a, <4 x i32> %b) {
274 ;CHECK: and {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
274 ;CHECK: and {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
275275 %tmp1 = and <4 x i32> %a, %b;
276276 ret <4 x i32> %tmp1
277277 }
278278
279279 define <8 x i16> @and8xi16(<8 x i16> %a, <8 x i16> %b) {
280 ;CHECK: and {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
280 ;CHECK: and {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
281281 %tmp1 = and <8 x i16> %a, %b;
282282 ret <8 x i16> %tmp1
283283 }
284284
285285 define <2 x i64> @and2xi64(<2 x i64> %a, <2 x i64> %b) {
286 ;CHECK: and {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
286 ;CHECK: and {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
287287 %tmp1 = and <2 x i64> %a, %b;
288288 ret <2 x i64> %tmp1
289289 }
290290
291291 define <2 x i32> @orr2xi32(<2 x i32> %a, <2 x i32> %b) {
292 ;CHECK: orr {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
292 ;CHECK: orr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
293293 %tmp1 = or <2 x i32> %a, %b;
294294 ret <2 x i32> %tmp1
295295 }
296296
297297 define <4 x i16> @orr4xi16(<4 x i16> %a, <4 x i16> %b) {
298 ;CHECK: orr {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
298 ;CHECK: orr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
299299 %tmp1 = or <4 x i16> %a, %b;
300300 ret <4 x i16> %tmp1
301301 }
302302
303303 define <1 x i64> @orr1xi64(<1 x i64> %a, <1 x i64> %b) {
304 ;CHECK: orr {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
304 ;CHECK: orr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
305305 %tmp1 = or <1 x i64> %a, %b;
306306 ret <1 x i64> %tmp1
307307 }
308308
309309 define <4 x i32> @orr4xi32(<4 x i32> %a, <4 x i32> %b) {
310 ;CHECK: orr {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
310 ;CHECK: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
311311 %tmp1 = or <4 x i32> %a, %b;
312312 ret <4 x i32> %tmp1
313313 }
314314
315315 define <8 x i16> @orr8xi16(<8 x i16> %a, <8 x i16> %b) {
316 ;CHECK: orr {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
316 ;CHECK: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
317317 %tmp1 = or <8 x i16> %a, %b;
318318 ret <8 x i16> %tmp1
319319 }
320320
321321 define <2 x i64> @orr2xi64(<2 x i64> %a, <2 x i64> %b) {
322 ;CHECK: orr {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
322 ;CHECK: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
323323 %tmp1 = or <2 x i64> %a, %b;
324324 ret <2 x i64> %tmp1
325325 }
326326
327327 define <2 x i32> @eor2xi32(<2 x i32> %a, <2 x i32> %b) {
328 ;CHECK: eor {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
328 ;CHECK: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
329329 %tmp1 = xor <2 x i32> %a, %b;
330330 ret <2 x i32> %tmp1
331331 }
332332
333333 define <4 x i16> @eor4xi16(<4 x i16> %a, <4 x i16> %b) {
334 ;CHECK: eor {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
334 ;CHECK: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
335335 %tmp1 = xor <4 x i16> %a, %b;
336336 ret <4 x i16> %tmp1
337337 }
338338
339339 define <1 x i64> @eor1xi64(<1 x i64> %a, <1 x i64> %b) {
340 ;CHECK: eor {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
340 ;CHECK: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
341341 %tmp1 = xor <1 x i64> %a, %b;
342342 ret <1 x i64> %tmp1
343343 }
344344
345345 define <4 x i32> @eor4xi32(<4 x i32> %a, <4 x i32> %b) {
346 ;CHECK: eor {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
346 ;CHECK: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
347347 %tmp1 = xor <4 x i32> %a, %b;
348348 ret <4 x i32> %tmp1
349349 }
350350
351351 define <8 x i16> @eor8xi16(<8 x i16> %a, <8 x i16> %b) {
352 ;CHECK: eor {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
352 ;CHECK: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
353353 %tmp1 = xor <8 x i16> %a, %b;
354354 ret <8 x i16> %tmp1
355355 }
356356
357357 define <2 x i64> @eor2xi64(<2 x i64> %a, <2 x i64> %b) {
358 ;CHECK: eor {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
358 ;CHECK: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
359359 %tmp1 = xor <2 x i64> %a, %b;
360360 ret <2 x i64> %tmp1
361361 }
362362
363363
364364 define <2 x i32> @bic2xi32(<2 x i32> %a, <2 x i32> %b) {
365 ;CHECK: bic {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
365 ;CHECK: bic {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
366366 %tmp1 = xor <2 x i32> %b, < i32 -1, i32 -1 >
367367 %tmp2 = and <2 x i32> %a, %tmp1
368368 ret <2 x i32> %tmp2
369369 }
370370
371371 define <4 x i16> @bic4xi16(<4 x i16> %a, <4 x i16> %b) {
372 ;CHECK: bic {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
372 ;CHECK: bic {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
373373 %tmp1 = xor <4 x i16> %b, < i16 -1, i16 -1, i16 -1, i16-1 >
374374 %tmp2 = and <4 x i16> %a, %tmp1
375375 ret <4 x i16> %tmp2
376376 }
377377
378378 define <1 x i64> @bic1xi64(<1 x i64> %a, <1 x i64> %b) {
379 ;CHECK: bic {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
379 ;CHECK: bic {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
380380 %tmp1 = xor <1 x i64> %b, < i64 -1>
381381 %tmp2 = and <1 x i64> %a, %tmp1
382382 ret <1 x i64> %tmp2
383383 }
384384
385385 define <4 x i32> @bic4xi32(<4 x i32> %a, <4 x i32> %b) {
386 ;CHECK: bic {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
386 ;CHECK: bic {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
387387 %tmp1 = xor <4 x i32> %b, < i32 -1, i32 -1, i32 -1, i32 -1>
388388 %tmp2 = and <4 x i32> %a, %tmp1
389389 ret <4 x i32> %tmp2
390390 }
391391
392392 define <8 x i16> @bic8xi16(<8 x i16> %a, <8 x i16> %b) {
393 ;CHECK: bic {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
393 ;CHECK: bic {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
394394 %tmp1 = xor <8 x i16> %b, < i16 -1, i16 -1, i16 -1, i16-1, i16 -1, i16 -1, i16 -1, i16 -1 >
395395 %tmp2 = and <8 x i16> %a, %tmp1
396396 ret <8 x i16> %tmp2
397397 }
398398
399399 define <2 x i64> @bic2xi64(<2 x i64> %a, <2 x i64> %b) {
400 ;CHECK: bic {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
400 ;CHECK: bic {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
401401 %tmp1 = xor <2 x i64> %b, < i64 -1, i64 -1>
402402 %tmp2 = and <2 x i64> %a, %tmp1
403403 ret <2 x i64> %tmp2
404404 }
405405
406406 define <2 x i32> @orn2xi32(<2 x i32> %a, <2 x i32> %b) {
407 ;CHECK: orn {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
407 ;CHECK: orn {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
408408 %tmp1 = xor <2 x i32> %b, < i32 -1, i32 -1 >
409409 %tmp2 = or <2 x i32> %a, %tmp1
410410 ret <2 x i32> %tmp2
411411 }
412412
413413 define <4 x i16> @orn4xi16(<4 x i16> %a, <4 x i16> %b) {
414 ;CHECK: orn {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
414 ;CHECK: orn {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
415415 %tmp1 = xor <4 x i16> %b, < i16 -1, i16 -1, i16 -1, i16-1 >
416416 %tmp2 = or <4 x i16> %a, %tmp1
417417 ret <4 x i16> %tmp2
418418 }
419419
420420 define <1 x i64> @orn1xi64(<1 x i64> %a, <1 x i64> %b) {
421 ;CHECK: orn {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
421 ;CHECK: orn {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
422422 %tmp1 = xor <1 x i64> %b, < i64 -1>
423423 %tmp2 = or <1 x i64> %a, %tmp1
424424 ret <1 x i64> %tmp2
425425 }
426426
427427 define <4 x i32> @orn4xi32(<4 x i32> %a, <4 x i32> %b) {
428 ;CHECK: orn {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
428 ;CHECK: orn {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
429429 %tmp1 = xor <4 x i32> %b, < i32 -1, i32 -1, i32 -1, i32 -1>
430430 %tmp2 = or <4 x i32> %a, %tmp1
431431 ret <4 x i32> %tmp2
432432 }
433433
434434 define <8 x i16> @orn8xi16(<8 x i16> %a, <8 x i16> %b) {
435 ;CHECK: orn {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
435 ;CHECK: orn {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
436436 %tmp1 = xor <8 x i16> %b, < i16 -1, i16 -1, i16 -1, i16-1, i16 -1, i16 -1, i16 -1, i16 -1 >
437437 %tmp2 = or <8 x i16> %a, %tmp1
438438 ret <8 x i16> %tmp2
439439 }
440440
441441 define <2 x i64> @orn2xi64(<2 x i64> %a, <2 x i64> %b) {
442 ;CHECK: orn {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
442 ;CHECK: orn {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
443443 %tmp1 = xor <2 x i64> %b, < i64 -1, i64 -1>
444444 %tmp2 = or <2 x i64> %a, %tmp1
445445 ret <2 x i64> %tmp2
446446 }
447447 define <2 x i32> @bsl2xi32_const(<2 x i32> %a, <2 x i32> %b) {
448 ;CHECK: bsl {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
448 ;CHECK: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
449449 %tmp1 = and <2 x i32> %a, < i32 -1, i32 -1 >
450450 %tmp2 = and <2 x i32> %b, < i32 0, i32 0 >
451451 %tmp3 = or <2 x i32> %tmp1, %tmp2
454454
455455
456456 define <4 x i16> @bsl4xi16_const(<4 x i16> %a, <4 x i16> %b) {
457 ;CHECK: bsl {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
457 ;CHECK: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
458458 %tmp1 = and <4 x i16> %a, < i16 -1, i16 -1, i16 -1,i16 -1 >
459459 %tmp2 = and <4 x i16> %b, < i16 0, i16 0,i16 0, i16 0 >
460460 %tmp3 = or <4 x i16> %tmp1, %tmp2
462462 }
463463
464464 define <1 x i64> @bsl1xi64_const(<1 x i64> %a, <1 x i64> %b) {
465 ;CHECK: bsl {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
465 ;CHECK: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
466466 %tmp1 = and <1 x i64> %a, < i64 -1 >
467467 %tmp2 = and <1 x i64> %b, < i64 0 >
468468 %tmp3 = or <1 x i64> %tmp1, %tmp2
470470 }
471471
472472 define <4 x i32> @bsl4xi32_const(<4 x i32> %a, <4 x i32> %b) {
473 ;CHECK: bsl {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
473 ;CHECK: bsl {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
474474 %tmp1 = and <4 x i32> %a, < i32 -1, i32 -1, i32 -1, i32 -1 >
475475 %tmp2 = and <4 x i32> %b, < i32 0, i32 0, i32 0, i32 0 >
476476 %tmp3 = or <4 x i32> %tmp1, %tmp2
478478 }
479479
480480 define <8 x i16> @bsl8xi16_const(<8 x i16> %a, <8 x i16> %b) {
481 ;CHECK: bsl {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
481 ;CHECK: bsl {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
482482 %tmp1 = and <8 x i16> %a, < i16 -1, i16 -1, i16 -1,i16 -1, i16 -1, i16 -1, i16 -1,i16 -1 >
483483 %tmp2 = and <8 x i16> %b, < i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0 >
484484 %tmp3 = or <8 x i16> %tmp1, %tmp2
486486 }
487487
488488 define <2 x i64> @bsl2xi64_const(<2 x i64> %a, <2 x i64> %b) {
489 ;CHECK: bsl {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
489 ;CHECK: bsl {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
490490 %tmp1 = and <2 x i64> %a, < i64 -1, i64 -1 >
491491 %tmp2 = and <2 x i64> %b, < i64 0, i64 0 >
492492 %tmp3 = or <2 x i64> %tmp1, %tmp2
495495
496496
497497 define <8 x i8> @bsl8xi8(<8 x i8> %v1, <8 x i8> %v2, <8 x i8> %v3) {
498 ;CHECK: bsl {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
498 ;CHECK: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
499499 %1 = and <8 x i8> %v1, %v2
500500 %2 = xor <8 x i8> %v1,
501501 %3 = and <8 x i8> %2, %v3
504504 }
505505
506506 define <4 x i16> @bsl4xi16(<4 x i16> %v1, <4 x i16> %v2, <4 x i16> %v3) {
507 ;CHECK: bsl {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
507 ;CHECK: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
508508 %1 = and <4 x i16> %v1, %v2
509509 %2 = xor <4 x i16> %v1,
510510 %3 = and <4 x i16> %2, %v3
513513 }
514514
515515 define <2 x i32> @bsl2xi32(<2 x i32> %v1, <2 x i32> %v2, <2 x i32> %v3) {
516 ;CHECK: bsl {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
516 ;CHECK: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
517517 %1 = and <2 x i32> %v1, %v2
518518 %2 = xor <2 x i32> %v1,
519519 %3 = and <2 x i32> %2, %v3
522522 }
523523
524524 define <1 x i64> @bsl1xi64(<1 x i64> %v1, <1 x i64> %v2, <1 x i64> %v3) {
525 ;CHECK: bsl {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
525 ;CHECK: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
526526 %1 = and <1 x i64> %v1, %v2
527527 %2 = xor <1 x i64> %v1,
528528 %3 = and <1 x i64> %2, %v3
531531 }
532532
533533 define <16 x i8> @bsl16xi8(<16 x i8> %v1, <16 x i8> %v2, <16 x i8> %v3) {
534 ;CHECK: bsl {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
534 ;CHECK: bsl {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
535535 %1 = and <16 x i8> %v1, %v2
536536 %2 = xor <16 x i8> %v1,
537537 %3 = and <16 x i8> %2, %v3
540540 }
541541
542542 define <8 x i16> @bsl8xi16(<8 x i16> %v1, <8 x i16> %v2, <8 x i16> %v3) {
543 ;CHECK: bsl {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
543 ;CHECK: bsl {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
544544 %1 = and <8 x i16> %v1, %v2
545545 %2 = xor <8 x i16> %v1,
546546 %3 = and <8 x i16> %2, %v3
549549 }
550550
551551 define <4 x i32> @bsl4xi32(<4 x i32> %v1, <4 x i32> %v2, <4 x i32> %v3) {
552 ;CHECK: bsl {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
552 ;CHECK: bsl {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
553553 %1 = and <4 x i32> %v1, %v2
554554 %2 = xor <4 x i32> %v1,
555555 %3 = and <4 x i32> %2, %v3
558558 }
559559
560560 define <2 x i64> @bsl2xi64(<2 x i64> %v1, <2 x i64> %v2, <2 x i64> %v3) {
561 ;CHECK: bsl {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
561 ;CHECK: bsl {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
562562 %1 = and <2 x i64> %v1, %v2
563563 %2 = xor <2 x i64> %v1,
564564 %3 = and <2 x i64> %2, %v3
567567 }
568568
569569 define <8 x i8> @orrimm8b_as_orrimm4h_lsl0(<8 x i8> %a) {
570 ;CHECK: orr {{v[0-31]+}}.4h, #0xff
570 ;CHECK: orr {{v[0-9]+}}.4h, #0xff
571571 %val = or <8 x i8> %a,
572572 ret <8 x i8> %val
573573 }
574574
575575 define <8 x i8> @orrimm8b_as_orimm4h_lsl8(<8 x i8> %a) {
576 ;CHECK: orr {{v[0-31]+}}.4h, #0xff, lsl #8
576 ;CHECK: orr {{v[0-9]+}}.4h, #0xff, lsl #8
577577 %val = or <8 x i8> %a,
578578 ret <8 x i8> %val
579579 }
580580
581581 define <16 x i8> @orimm16b_as_orrimm8h_lsl0(<16 x i8> %a) {
582 ;CHECK: orr {{v[0-31]+}}.8h, #0xff
582 ;CHECK: orr {{v[0-9]+}}.8h, #0xff
583583 %val = or <16 x i8> %a,
584584 ret <16 x i8> %val
585585 }
586586
587587 define <16 x i8> @orimm16b_as_orrimm8h_lsl8(<16 x i8> %a) {
588 ;CHECK: orr {{v[0-31]+}}.8h, #0xff, lsl #8
588 ;CHECK: orr {{v[0-9]+}}.8h, #0xff, lsl #8
589589 %val = or <16 x i8> %a,
590590 ret <16 x i8> %val
591591 }
11
22
33 define <16 x i8> @ins16bw(<16 x i8> %tmp1, i8 %tmp2) {
4 ;CHECK: ins {{v[0-31]+}}.b[15], {{w[0-31]+}}
4 ;CHECK: ins {{v[0-9]+}}.b[15], {{w[0-9]+}}
55 %tmp3 = insertelement <16 x i8> %tmp1, i8 %tmp2, i32 15
66 ret <16 x i8> %tmp3
77 }
88
99 define <8 x i16> @ins8hw(<8 x i16> %tmp1, i16 %tmp2) {
10 ;CHECK: ins {{v[0-31]+}}.h[6], {{w[0-31]+}}
10 ;CHECK: ins {{v[0-9]+}}.h[6], {{w[0-9]+}}
1111 %tmp3 = insertelement <8 x i16> %tmp1, i16 %tmp2, i32 6
1212 ret <8 x i16> %tmp3
1313 }
1414
1515 define <4 x i32> @ins4sw(<4 x i32> %tmp1, i32 %tmp2) {
16 ;CHECK: ins {{v[0-31]+}}.s[2], {{w[0-31]+}}
16 ;CHECK: ins {{v[0-9]+}}.s[2], {{w[0-9]+}}
1717 %tmp3 = insertelement <4 x i32> %tmp1, i32 %tmp2, i32 2
1818 ret <4 x i32> %tmp3
1919 }
2020
2121 define <2 x i64> @ins2dw(<2 x i64> %tmp1, i64 %tmp2) {
22 ;CHECK: ins {{v[0-31]+}}.d[1], {{x[0-31]+}}
22 ;CHECK: ins {{v[0-9]+}}.d[1], {{x[0-9]+}}
2323 %tmp3 = insertelement <2 x i64> %tmp1, i64 %tmp2, i32 1
2424 ret <2 x i64> %tmp3
2525 }
2626
2727 define <8 x i8> @ins8bw(<8 x i8> %tmp1, i8 %tmp2) {
28 ;CHECK: ins {{v[0-31]+}}.b[5], {{w[0-31]+}}
28 ;CHECK: ins {{v[0-9]+}}.b[5], {{w[0-9]+}}
2929 %tmp3 = insertelement <8 x i8> %tmp1, i8 %tmp2, i32 5
3030 ret <8 x i8> %tmp3
3131 }
3232
3333 define <4 x i16> @ins4hw(<4 x i16> %tmp1, i16 %tmp2) {
34 ;CHECK: ins {{v[0-31]+}}.h[3], {{w[0-31]+}}
34 ;CHECK: ins {{v[0-9]+}}.h[3], {{w[0-9]+}}
3535 %tmp3 = insertelement <4 x i16> %tmp1, i16 %tmp2, i32 3
3636 ret <4 x i16> %tmp3
3737 }
3838
3939 define <2 x i32> @ins2sw(<2 x i32> %tmp1, i32 %tmp2) {
40 ;CHECK: ins {{v[0-31]+}}.s[1], {{w[0-31]+}}
40 ;CHECK: ins {{v[0-9]+}}.s[1], {{w[0-9]+}}
4141 %tmp3 = insertelement <2 x i32> %tmp1, i32 %tmp2, i32 1
4242 ret <2 x i32> %tmp3
4343 }
4444
4545 define <16 x i8> @ins16b16(<16 x i8> %tmp1, <16 x i8> %tmp2) {
46 ;CHECK: ins {{v[0-31]+}}.b[15], {{v[0-31]+}}.b[2]
46 ;CHECK: ins {{v[0-9]+}}.b[15], {{v[0-9]+}}.b[2]
4747 %tmp3 = extractelement <16 x i8> %tmp1, i32 2
4848 %tmp4 = insertelement <16 x i8> %tmp2, i8 %tmp3, i32 15
4949 ret <16 x i8> %tmp4
5050 }
5151
5252 define <8 x i16> @ins8h8(<8 x i16> %tmp1, <8 x i16> %tmp2) {
53 ;CHECK: ins {{v[0-31]+}}.h[7], {{v[0-31]+}}.h[2]
53 ;CHECK: ins {{v[0-9]+}}.h[7], {{v[0-9]+}}.h[2]
5454 %tmp3 = extractelement <8 x i16> %tmp1, i32 2
5555 %tmp4 = insertelement <8 x i16> %tmp2, i16 %tmp3, i32 7
5656 ret <8 x i16> %tmp4
5757 }
5858
5959 define <4 x i32> @ins4s4(<4 x i32> %tmp1, <4 x i32> %tmp2) {
60 ;CHECK: ins {{v[0-31]+}}.s[1], {{v[0-31]+}}.s[2]
60 ;CHECK: ins {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[2]
6161 %tmp3 = extractelement <4 x i32> %tmp1, i32 2
6262 %tmp4 = insertelement <4 x i32> %tmp2, i32 %tmp3, i32 1
6363 ret <4 x i32> %tmp4
6464 }
6565
6666 define <2 x i64> @ins2d2(<2 x i64> %tmp1, <2 x i64> %tmp2) {
67 ;CHECK: ins {{v[0-31]+}}.d[1], {{v[0-31]+}}.d[0]
67 ;CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
6868 %tmp3 = extractelement <2 x i64> %tmp1, i32 0
6969 %tmp4 = insertelement <2 x i64> %tmp2, i64 %tmp3, i32 1
7070 ret <2 x i64> %tmp4
7171 }
7272
7373 define <4 x float> @ins4f4(<4 x float> %tmp1, <4 x float> %tmp2) {
74 ;CHECK: ins {{v[0-31]+}}.s[1], {{v[0-31]+}}.s[2]
74 ;CHECK: ins {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[2]
7575 %tmp3 = extractelement <4 x float> %tmp1, i32 2
7676 %tmp4 = insertelement <4 x float> %tmp2, float %tmp3, i32 1
7777 ret <4 x float> %tmp4
7878 }
7979
8080 define <2 x double> @ins2df2(<2 x double> %tmp1, <2 x double> %tmp2) {
81 ;CHECK: ins {{v[0-31]+}}.d[1], {{v[0-31]+}}.d[0]
81 ;CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
8282 %tmp3 = extractelement <2 x double> %tmp1, i32 0
8383 %tmp4 = insertelement <2 x double> %tmp2, double %tmp3, i32 1
8484 ret <2 x double> %tmp4
8585 }
8686
8787 define <16 x i8> @ins8b16(<8 x i8> %tmp1, <16 x i8> %tmp2) {
88 ;CHECK: ins {{v[0-31]+}}.b[15], {{v[0-31]+}}.b[2]
88 ;CHECK: ins {{v[0-9]+}}.b[15], {{v[0-9]+}}.b[2]
8989 %tmp3 = extractelement <8 x i8> %tmp1, i32 2
9090 %tmp4 = insertelement <16 x i8> %tmp2, i8 %tmp3, i32 15
9191 ret <16 x i8> %tmp4
9292 }
9393
9494 define <8 x i16> @ins4h8(<4 x i16> %tmp1, <8 x i16> %tmp2) {
95 ;CHECK: ins {{v[0-31]+}}.h[7], {{v[0-31]+}}.h[2]
95 ;CHECK: ins {{v[0-9]+}}.h[7], {{v[0-9]+}}.h[2]
9696 %tmp3 = extractelement <4 x i16> %tmp1, i32 2
9797 %tmp4 = insertelement <8 x i16> %tmp2, i16 %tmp3, i32 7
9898 ret <8 x i16> %tmp4
9999 }
100100
101101 define <4 x i32> @ins2s4(<2 x i32> %tmp1, <4 x i32> %tmp2) {
102 ;CHECK: ins {{v[0-31]+}}.s[1], {{v[0-31]+}}.s[1]
102 ;CHECK: ins {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[1]
103103 %tmp3 = extractelement <2 x i32> %tmp1, i32 1
104104 %tmp4 = insertelement <4 x i32> %tmp2, i32 %tmp3, i32 1
105105 ret <4 x i32> %tmp4
106106 }
107107
108108 define <2 x i64> @ins1d2(<1 x i64> %tmp1, <2 x i64> %tmp2) {
109 ;CHECK: ins {{v[0-31]+}}.d[1], {{v[0-31]+}}.d[0]
109 ;CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
110110 %tmp3 = extractelement <1 x i64> %tmp1, i32 0
111111 %tmp4 = insertelement <2 x i64> %tmp2, i64 %tmp3, i32 1
112112 ret <2 x i64> %tmp4
113113 }
114114
115115 define <4 x float> @ins2f4(<2 x float> %tmp1, <4 x float> %tmp2) {
116 ;CHECK: ins {{v[0-31]+}}.s[1], {{v[0-31]+}}.s[1]
116 ;CHECK: ins {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[1]
117117 %tmp3 = extractelement <2 x float> %tmp1, i32 1
118118 %tmp4 = insertelement <4 x float> %tmp2, float %tmp3, i32 1
119119 ret <4 x float> %tmp4
120120 }
121121
122122 define <2 x double> @ins1f2(<1 x double> %tmp1, <2 x double> %tmp2) {
123 ;CHECK: ins {{v[0-31]+}}.d[1], {{v[0-31]+}}.d[0]
123 ;CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
124124 %tmp3 = extractelement <1 x double> %tmp1, i32 0
125125 %tmp4 = insertelement <2 x double> %tmp2, double %tmp3, i32 1
126126 ret <2 x double> %tmp4
127127 }
128128
129129 define <8 x i8> @ins16b8(<16 x i8> %tmp1, <8 x i8> %tmp2) {
130 ;CHECK: ins {{v[0-31]+}}.b[7], {{v[0-31]+}}.b[2]
130 ;CHECK: ins {{v[0-9]+}}.b[7], {{v[0-9]+}}.b[2]
131131 %tmp3 = extractelement <16 x i8> %tmp1, i32 2
132132 %tmp4 = insertelement <8 x i8> %tmp2, i8 %tmp3, i32 7
133133 ret <8 x i8> %tmp4
134134 }
135135
136136 define <4 x i16> @ins8h4(<8 x i16> %tmp1, <4 x i16> %tmp2) {
137 ;CHECK: ins {{v[0-31]+}}.h[3], {{v[0-31]+}}.h[2]
137 ;CHECK: ins {{v[0-9]+}}.h[3], {{v[0-9]+}}.h[2]
138138 %tmp3 = extractelement <8 x i16> %tmp1, i32 2
139139 %tmp4 = insertelement <4 x i16> %tmp2, i16 %tmp3, i32 3
140140 ret <4 x i16> %tmp4
141141 }
142142
143143 define <2 x i32> @ins4s2(<4 x i32> %tmp1, <2 x i32> %tmp2) {
144 ;CHECK: ins {{v[0-31]+}}.s[1], {{v[0-31]+}}.s[2]
144 ;CHECK: ins {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[2]
145145 %tmp3 = extractelement <4 x i32> %tmp1, i32 2
146146 %tmp4 = insertelement <2 x i32> %tmp2, i32 %tmp3, i32 1
147147 ret <2 x i32> %tmp4
148148 }
149149
150150 define <1 x i64> @ins2d1(<2 x i64> %tmp1, <1 x i64> %tmp2) {
151 ;CHECK: ins {{v[0-31]+}}.d[0], {{v[0-31]+}}.d[0]
151 ;CHECK: ins {{v[0-9]+}}.d[0], {{v[0-9]+}}.d[0]
152152 %tmp3 = extractelement <2 x i64> %tmp1, i32 0
153153 %tmp4 = insertelement <1 x i64> %tmp2, i64 %tmp3, i32 0
154154 ret <1 x i64> %tmp4
155155 }
156156
157157 define <2 x float> @ins4f2(<4 x float> %tmp1, <2 x float> %tmp2) {
158 ;CHECK: ins {{v[0-31]+}}.s[1], {{v[0-31]+}}.s[2]
158 ;CHECK: ins {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[2]
159159 %tmp3 = extractelement <4 x float> %tmp1, i32 2
160160 %tmp4 = insertelement <2 x float> %tmp2, float %tmp3, i32 1
161161 ret <2 x float> %tmp4
162162 }
163163
164164 define <1 x double> @ins2f1(<2 x double> %tmp1, <1 x double> %tmp2) {
165 ;CHECK: ins {{v[0-31]+}}.d[0], {{v[0-31]+}}.d[0]
165 ;CHECK: ins {{v[0-9]+}}.d[0], {{v[0-9]+}}.d[0]
166166 %tmp3 = extractelement <2 x double> %tmp1, i32 0
167167 %tmp4 = insertelement <1 x double> %tmp2, double %tmp3, i32 0
168168 ret <1 x double> %tmp4
169169 }
170170
171171 define <8 x i8> @ins8b8(<8 x i8> %tmp1, <8 x i8> %tmp2) {
172 ;CHECK: ins {{v[0-31]+}}.b[4], {{v[0-31]+}}.b[2]
172 ;CHECK: ins {{v[0-9]+}}.b[4], {{v[0-9]+}}.b[2]
173173 %tmp3 = extractelement <8 x i8> %tmp1, i32 2
174174 %tmp4 = insertelement <8 x i8> %tmp2, i8 %tmp3, i32 4
175175 ret <8 x i8> %tmp4
176176 }
177177
178178 define <4 x i16> @ins4h4(<4 x i16> %tmp1, <4 x i16> %tmp2) {
179 ;CHECK: ins {{v[0-31]+}}.h[3], {{v[0-31]+}}.h[2]
179 ;CHECK: ins {{v[0-9]+}}.h[3], {{v[0-9]+}}.h[2]
180180 %tmp3 = extractelement <4 x i16> %tmp1, i32 2
181181 %tmp4 = insertelement <4 x i16> %tmp2, i16 %tmp3, i32 3
182182 ret <4 x i16> %tmp4
183183 }
184184
185185 define <2 x i32> @ins2s2(<2 x i32> %tmp1, <2 x i32> %tmp2) {
186 ;CHECK: ins {{v[0-31]+}}.s[1], {{v[0-31]+}}.s[0]
186 ;CHECK: ins {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[0]
187187 %tmp3 = extractelement <2 x i32> %tmp1, i32 0
188188 %tmp4 = insertelement <2 x i32> %tmp2, i32 %tmp3, i32 1
189189 ret <2 x i32> %tmp4
190190 }
191191
192192 define <1 x i64> @ins1d1(<1 x i64> %tmp1, <1 x i64> %tmp2) {
193 ;CHECK: ins {{v[0-31]+}}.d[0], {{v[0-31]+}}.d[0]
193 ;CHECK: ins {{v[0-9]+}}.d[0], {{v[0-9]+}}.d[0]
194194 %tmp3 = extractelement <1 x i64> %tmp1, i32 0
195195 %tmp4 = insertelement <1 x i64> %tmp2, i64 %tmp3, i32 0
196196 ret <1 x i64> %tmp4
197197 }
198198
199199 define <2 x float> @ins2f2(<2 x float> %tmp1, <2 x float> %tmp2) {
200 ;CHECK: ins {{v[0-31]+}}.s[1], {{v[0-31]+}}.s[0]
200 ;CHECK: ins {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[0]
201201 %tmp3 = extractelement <2 x float> %tmp1, i32 0
202202 %tmp4 = insertelement <2 x float> %tmp2, float %tmp3, i32 1
203203 ret <2 x float> %tmp4
204204 }
205205
206206 define <1 x double> @ins1df1(<1 x double> %tmp1, <1 x double> %tmp2) {
207 ;CHECK: ins {{v[0-31]+}}.d[0], {{v[0-31]+}}.d[0]
207 ;CHECK: ins {{v[0-9]+}}.d[0], {{v[0-9]+}}.d[0]
208208 %tmp3 = extractelement <1 x double> %tmp1, i32 0
209209 %tmp4 = insertelement <1 x double> %tmp2, double %tmp3, i32 0
210210 ret <1 x double> %tmp4
211211 }
212212
213213 define i32 @umovw16b(<16 x i8> %tmp1) {
214 ;CHECK: umov {{w[0-31]+}}, {{v[0-31]+}}.b[8]
214 ;CHECK: umov {{w[0-9]+}}, {{v[0-9]+}}.b[8]
215215 %tmp3 = extractelement <16 x i8> %tmp1, i32 8
216216 %tmp4 = zext i8 %tmp3 to i32
217217 ret i32 %tmp4
218218 }
219219
220220 define i32 @umovw8h(<8 x i16> %tmp1) {
221 ;CHECK: umov {{w[0-31]+}}, {{v[0-31]+}}.h[2]
221 ;CHECK: umov {{w[0-9]+}}, {{v[0-9]+}}.h[2]
222222 %tmp3 = extractelement <8 x i16> %tmp1, i32 2
223223 %tmp4 = zext i16 %tmp3 to i32
224224 ret i32 %tmp4
225225 }
226226
227227 define i32 @umovw4s(<4 x i32> %tmp1) {
228 ;CHECK: umov {{w[0-31]+}}, {{v[0-31]+}}.s[2]
228 ;CHECK: umov {{w[0-9]+}}, {{v[0-9]+}}.s[2]
229229 %tmp3 = extractelement <4 x i32> %tmp1, i32 2
230230 ret i32 %tmp3
231231 }
232232
233233 define i64 @umovx2d(<2 x i64> %tmp1) {
234 ;CHECK: umov {{x[0-31]+}}, {{v[0-31]+}}.d[0]
234 ;CHECK: umov {{x[0-9]+}}, {{v[0-9]+}}.d[0]
235235 %tmp3 = extractelement <2 x i64> %tmp1, i32 0
236236 ret i64 %tmp3
237237 }
238238
239239 define i32 @umovw8b(<8 x i8> %tmp1) {
240 ;CHECK: umov {{w[0-31]+}}, {{v[0-31]+}}.b[7]
240 ;CHECK: umov {{w[0-9]+}}, {{v[0-9]+}}.b[7]
241241 %tmp3 = extractelement <8 x i8> %tmp1, i32 7
242242 %tmp4 = zext i8 %tmp3 to i32
243243 ret i32 %tmp4
244244 }
245245
246246 define i32 @umovw4h(<4 x i16> %tmp1) {
247 ;CHECK: umov {{w[0-31]+}}, {{v[0-31]+}}.h[2]
247 ;CHECK: umov {{w[0-9]+}}, {{v[0-9]+}}.h[2]
248248 %tmp3 = extractelement <4 x i16> %tmp1, i32 2
249249 %tmp4 = zext i16 %tmp3 to i32
250250 ret i32 %tmp4
251251 }
252252
253253 define i32 @umovw2s(<2 x i32> %tmp1) {
254 ;CHECK: umov {{w[0-31]+}}, {{v[0-31]+}}.s[1]
254 ;CHECK: umov {{w[0-9]+}}, {{v[0-9]+}}.s[1]
255255 %tmp3 = extractelement <2 x i32> %tmp1, i32 1
256256 ret i32 %tmp3
257257 }
258258
259259 define i64 @umovx1d(<1 x i64> %tmp1) {
260 ;CHECK: fmov {{x[0-31]+}}, {{d[0-31]+}}
260 ;CHECK: fmov {{x[0-9]+}}, {{d[0-9]+}}
261261 %tmp3 = extractelement <1 x i64> %tmp1, i32 0
262262 ret i64 %tmp3
263263 }
264264
265265 define i32 @smovw16b(<16 x i8> %tmp1) {
266 ;CHECK: smov {{w[0-31]+}}, {{v[0-31]+}}.b[8]
266 ;CHECK: smov {{w[0-9]+}}, {{v[0-9]+}}.b[8]
267267 %tmp3 = extractelement <16 x i8> %tmp1, i32 8
268268 %tmp4 = sext i8 %tmp3 to i32
269269 %tmp5 = add i32 5, %tmp4
271271 }
272272
273273 define i32 @smovw8h(<8 x i16> %tmp1) {
274 ;CHECK: smov {{w[0-31]+}}, {{v[0-31]+}}.h[2]
274 ;CHECK: smov {{w[0-9]+}}, {{v[0-9]+}}.h[2]
275275 %tmp3 = extractelement <8 x i16> %tmp1, i32 2
276276 %tmp4 = sext i16 %tmp3 to i32
277277 %tmp5 = add i32 5, %tmp4
279279 }
280280
281281 define i32 @smovx16b(<16 x i8> %tmp1) {
282 ;CHECK: smov {{x[0-31]+}}, {{v[0-31]+}}.b[8]
282 ;CHECK: smov {{x[0-9]+}}, {{v[0-9]+}}.b[8]
283283 %tmp3 = extractelement <16 x i8> %tmp1, i32 8
284284 %tmp4 = sext i8 %tmp3 to i32
285285 ret i32 %tmp4
286286 }
287287
288288 define i32 @smovx8h(<8 x i16> %tmp1) {
289 ;CHECK: smov {{x[0-31]+}}, {{v[0-31]+}}.h[2]
289 ;CHECK: smov {{x[0-9]+}}, {{v[0-9]+}}.h[2]
290290 %tmp3 = extractelement <8 x i16> %tmp1, i32 2
291291 %tmp4 = sext i16 %tmp3 to i32
292292 ret i32 %tmp4
293293 }
294294
295295 define i64 @smovx4s(<4 x i32> %tmp1) {
296 ;CHECK: smov {{x[0-31]+}}, {{v[0-31]+}}.s[2]
296 ;CHECK: smov {{x[0-9]+}}, {{v[0-9]+}}.s[2]
297297 %tmp3 = extractelement <4 x i32> %tmp1, i32 2
298298 %tmp4 = sext i32 %tmp3 to i64
299299 ret i64 %tmp4
300300 }
301301
302302 define i32 @smovw8b(<8 x i8> %tmp1) {
303 ;CHECK: smov {{w[0-31]+}}, {{v[0-31]+}}.b[4]
303 ;CHECK: smov {{w[0-9]+}}, {{v[0-9]+}}.b[4]
304304 %tmp3 = extractelement <8 x i8> %tmp1, i32 4
305305 %tmp4 = sext i8 %tmp3 to i32
306306 %tmp5 = add i32 5, %tmp4
308308 }
309309
310310 define i32 @smovw4h(<4 x i16> %tmp1) {
311 ;CHECK: smov {{w[0-31]+}}, {{v[0-31]+}}.h[2]
311 ;CHECK: smov {{w[0-9]+}}, {{v[0-9]+}}.h[2]
312312 %tmp3 = extractelement <4 x i16> %tmp1, i32 2
313313 %tmp4 = sext i16 %tmp3 to i32
314314 %tmp5 = add i32 5, %tmp4
316316 }
317317
318318 define i32 @smovx8b(<8 x i8> %tmp1) {
319 ;CHECK: smov {{x[0-31]+}}, {{v[0-31]+}}.b[6]
319 ;CHECK: smov {{x[0-9]+}}, {{v[0-9]+}}.b[6]
320320 %tmp3 = extractelement <8 x i8> %tmp1, i32 6
321321 %tmp4 = sext i8 %tmp3 to i32
322322 ret i32 %tmp4
323323 }
324324
325325 define i32 @smovx4h(<4 x i16> %tmp1) {
326 ;CHECK: smov {{x[0-31]+}}, {{v[0-31]+}}.h[2]
326 ;CHECK: smov {{x[0-9]+}}, {{v[0-9]+}}.h[2]
327327 %tmp3 = extractelement <4 x i16> %tmp1, i32 2
328328 %tmp4 = sext i16 %tmp3 to i32
329329 ret i32 %tmp4
330330 }
331331
332332 define i64 @smovx2s(<2 x i32> %tmp1) {
333 ;CHECK: smov {{x[0-31]+}}, {{v[0-31]+}}.s[1]
333 ;CHECK: smov {{x[0-9]+}}, {{v[0-9]+}}.s[1]
334334 %tmp3 = extractelement <2 x i32> %tmp1, i32 1
335335 %tmp4 = sext i32 %tmp3 to i64
336336 ret i64 %tmp4
0 ; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon -fp-contract=fast | FileCheck %s
11
22 define <2 x float> @fmla2xfloat(<2 x float> %A, <2 x float> %B, <2 x float> %C) {
3 ;CHECK: fmla {{v[0-31]+}}.2s, {{v[0-31]+}}.2s, {{v[0-31]+}}.2s
3 ;CHECK: fmla {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
44 %tmp1 = fmul <2 x float> %A, %B;
55 %tmp2 = fadd <2 x float> %C, %tmp1;
66 ret <2 x float> %tmp2
77 }
88
99 define <4 x float> @fmla4xfloat(<4 x float> %A, <4 x float> %B, <4 x float> %C) {
10 ;CHECK: fmla {{v[0-31]+}}.4s, {{v[0-31]+}}.4s, {{v[0-31]+}}.4s
10 ;CHECK: fmla {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
1111 %tmp1 = fmul <4 x float> %A, %B;
1212 %tmp2 = fadd <4 x float> %C, %tmp1;
1313 ret <4 x float> %tmp2
1414 }
1515
1616 define <2 x double> @fmla2xdouble(<2 x double> %A, <2 x double> %B, <2 x double> %C) {
17 ;CHECK: fmla {{v[0-31]+}}.2d, {{v[0-31]+}}.2d, {{v[0-31]+}}.2d
17 ;CHECK: fmla {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
1818 %tmp1 = fmul <2 x double> %A, %B;
1919 %tmp2 = fadd <2 x double> %C, %tmp1;
2020 ret <2 x double> %tmp2
2222
2323
2424 define <2 x float> @fmls2xfloat(<2 x float> %A, <2 x float> %B, <2 x float> %C) {
25 ;CHECK: fmls {{v[0-31]+}}.2s, {{v[0-31]+}}.2s, {{v[0-31]+}}.2s
25 ;CHECK: fmls {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
2626 %tmp1 = fmul <2 x float> %A, %B;
2727 %tmp2 = fsub <2 x float> %C, %tmp1;
2828 ret <2 x float> %tmp2
2929 }
3030
3131 define <4 x float> @fmls4xfloat(<4 x float> %A, <4 x float> %B, <4 x float> %C) {
32 ;CHECK: fmls {{v[0-31]+}}.4s, {{v[0-31]+}}.4s, {{v[0-31]+}}.4s
32 ;CHECK: fmls {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
3333 %tmp1 = fmul <4 x float> %A, %B;
3434 %tmp2 = fsub <4 x float> %C, %tmp1;
3535 ret <4 x float> %tmp2
3636 }
3737
3838 define <2 x double> @fmls2xdouble(<2 x double> %A, <2 x double> %B, <2 x double> %C) {
39 ;CHECK: fmls {{v[0-31]+}}.2d, {{v[0-31]+}}.2d, {{v[0-31]+}}.2d
39 ;CHECK: fmls {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
4040 %tmp1 = fmul <2 x double> %A, %B;
4141 %tmp2 = fsub <2 x double> %C, %tmp1;
4242 ret <2 x double> %tmp2
5050 declare <2 x double> @llvm.fma.v2f64(<2 x double>, <2 x double>, <2 x double>)
5151
5252 define <2 x float> @fmla2xfloat_fused(<2 x float> %A, <2 x float> %B, <2 x float> %C) {
53 ;CHECK: fmla {{v[0-31]+}}.2s, {{v[0-31]+}}.2s, {{v[0-31]+}}.2s
53 ;CHECK: fmla {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
5454 %val = call <2 x float> @llvm.fma.v2f32(<2 x float> %A, <2 x float> %B, <2 x float> %C)
5555 ret <2 x float> %val
5656 }
5757
5858 define <4 x float> @fmla4xfloat_fused(<4 x float> %A, <4 x float> %B, <4 x float> %C) {
59 ;CHECK: fmla {{v[0-31]+}}.4s, {{v[0-31]+}}.4s, {{v[0-31]+}}.4s
59 ;CHECK: fmla {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
6060 %val = call <4 x float> @llvm.fma.v4f32(<4 x float> %A, <4 x float> %B, <4 x float> %C)
6161 ret <4 x float> %val
6262 }
6363
6464 define <2 x double> @fmla2xdouble_fused(<2 x double> %A, <2 x double> %B, <2 x double> %C) {
65 ;CHECK: fmla {{v[0-31]+}}.2d, {{v[0-31]+}}.2d, {{v[0-31]+}}.2d
65 ;CHECK: fmla {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
6666 %val = call <2 x double> @llvm.fma.v2f64(<2 x double> %A, <2 x double> %B, <2 x double> %C)
6767 ret <2 x double> %val
6868 }
6969
7070 define <2 x float> @fmls2xfloat_fused(<2 x float> %A, <2 x float> %B, <2 x float> %C) {
71 ;CHECK: fmls {{v[0-31]+}}.2s, {{v[0-31]+}}.2s, {{v[0-31]+}}.2s
71 ;CHECK: fmls {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
7272 %negA = fsub <2 x float> , %A
7373 %val = call <2 x float> @llvm.fma.v2f32(<2 x float> %negA, <2 x float> %B, <2 x float> %C)
7474 ret <2 x float> %val
7575 }
7676
7777 define <4 x float> @fmls4xfloat_fused(<4 x float> %A, <4 x float> %B, <4 x float> %C) {
78 ;CHECK: fmls {{v[0-31]+}}.4s, {{v[0-31]+}}.4s, {{v[0-31]+}}.4s
78 ;CHECK: fmls {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
7979 %negA = fsub <4 x float> , %A
8080 %val = call <4 x float> @llvm.fma.v4f32(<4 x float> %negA, <4 x float> %B, <4 x float> %C)
8181 ret <4 x float> %val
8282 }
8383
8484 define <2 x double> @fmls2xdouble_fused(<2 x double> %A, <2 x double> %B, <2 x double> %C) {
85 ;CHECK: fmls {{v[0-31]+}}.2d, {{v[0-31]+}}.2d, {{v[0-31]+}}.2d
85 ;CHECK: fmls {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
8686 %negA = fsub <2 x double> , %A
8787 %val = call <2 x double> @llvm.fma.v2f64(<2 x double> %negA, <2 x double> %B, <2 x double> %C)
8888 ret <2 x double> %val
9393 declare <2 x double> @llvm.fmuladd.v2f64(<2 x double>, <2 x double>, <2 x double>)
9494
9595 define <2 x float> @fmuladd2xfloat(<2 x float> %A, <2 x float> %B, <2 x float> %C) {
96 ;CHECK: fmla {{v[0-31]+}}.2s, {{v[0-31]+}}.2s, {{v[0-31]+}}.2s
96 ;CHECK: fmla {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
9797 %val = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %A, <2 x float> %B, <2 x float> %C)
9898 ret <2 x float> %val
9999 }
100100
101101 define <4 x float> @fmuladd4xfloat_fused(<4 x float> %A, <4 x float> %B, <4 x float> %C) {
102 ;CHECK: fmla {{v[0-31]+}}.4s, {{v[0-31]+}}.4s, {{v[0-31]+}}.4s
102 ;CHECK: fmla {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
103103 %val = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %A, <4 x float> %B, <4 x float> %C)
104104 ret <4 x float> %val
105105 }
106106
107107 define <2 x double> @fmuladd2xdouble_fused(<2 x double> %A, <2 x double> %B, <2 x double> %C) {
108 ;CHECK: fmla {{v[0-31]+}}.2d, {{v[0-31]+}}.2d, {{v[0-31]+}}.2d
108 ;CHECK: fmla {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
109109 %val = call <2 x double> @llvm.fmuladd.v2f64(<2 x double> %A, <2 x double> %B, <2 x double> %C)
110110 ret <2 x double> %val
111111 }
11
22
33 define <8 x i8> @mla8xi8(<8 x i8> %A, <8 x i8> %B, <8 x i8> %C) {
4 ;CHECK: mla {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
4 ;CHECK: mla {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
55 %tmp1 = mul <8 x i8> %A, %B;
66 %tmp2 = add <8 x i8> %C, %tmp1;
77 ret <8 x i8> %tmp2
88 }
99
1010 define <16 x i8> @mla16xi8(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C) {
11 ;CHECK: mla {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
11 ;CHECK: mla {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1212 %tmp1 = mul <16 x i8> %A, %B;
1313 %tmp2 = add <16 x i8> %C, %tmp1;
1414 ret <16 x i8> %tmp2
1515 }
1616
1717 define <4 x i16> @mla4xi16(<4 x i16> %A, <4 x i16> %B, <4 x i16> %C) {
18 ;CHECK: mla {{v[0-31]+}}.4h, {{v[0-31]+}}.4h, {{v[0-31]+}}.4h
18 ;CHECK: mla {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
1919 %tmp1 = mul <4 x i16> %A, %B;
2020 %tmp2 = add <4 x i16> %C, %tmp1;
2121 ret <4 x i16> %tmp2
2222 }
2323
2424 define <8 x i16> @mla8xi16(<8 x i16> %A, <8 x i16> %B, <8 x i16> %C) {
25 ;CHECK: mla {{v[0-31]+}}.8h, {{v[0-31]+}}.8h, {{v[0-31]+}}.8h
25 ;CHECK: mla {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
2626 %tmp1 = mul <8 x i16> %A, %B;
2727 %tmp2 = add <8 x i16> %C, %tmp1;
2828 ret <8 x i16> %tmp2
2929 }
3030
3131 define <2 x i32> @mla2xi32(<2 x i32> %A, <2 x i32> %B, <2 x i32> %C) {
32 ;CHECK: mla {{v[0-31]+}}.2s, {{v[0-31]+}}.2s, {{v[0-31]+}}.2s
32 ;CHECK: mla {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
3333 %tmp1 = mul <2 x i32> %A, %B;
3434 %tmp2 = add <2 x i32> %C, %tmp1;
3535 ret <2 x i32> %tmp2
3636 }
3737
3838 define <4 x i32> @mla4xi32(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) {
39 ;CHECK: mla {{v[0-31]+}}.4s, {{v[0-31]+}}.4s, {{v[0-31]+}}.4s
39 ;CHECK: mla {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
4040 %tmp1 = mul <4 x i32> %A, %B;
4141 %tmp2 = add <4 x i32> %C, %tmp1;
4242 ret <4 x i32> %tmp2
4343 }
4444
4545 define <8 x i8> @mls8xi8(<8 x i8> %A, <8 x i8> %B, <8 x i8> %C) {
46 ;CHECK: mls {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
46 ;CHECK: mls {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
4747 %tmp1 = mul <8 x i8> %A, %B;
4848 %tmp2 = sub <8 x i8> %C, %tmp1;
4949 ret <8 x i8> %tmp2
5050 }
5151
5252 define <16 x i8> @mls16xi8(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C) {
53 ;CHECK: mls {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
53 ;CHECK: mls {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
5454 %tmp1 = mul <16 x i8> %A, %B;
5555 %tmp2 = sub <16 x i8> %C, %tmp1;
5656 ret <16 x i8> %tmp2
5757 }
5858
5959 define <4 x i16> @mls4xi16(<4 x i16> %A, <4 x i16> %B, <4 x i16> %C) {
60 ;CHECK: mls {{v[0-31]+}}.4h, {{v[0-31]+}}.4h, {{v[0-31]+}}.4h
60 ;CHECK: mls {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
6161 %tmp1 = mul <4 x i16> %A, %B;
6262 %tmp2 = sub <4 x i16> %C, %tmp1;
6363 ret <4 x i16> %tmp2
6464 }
6565
6666 define <8 x i16> @mls8xi16(<8 x i16> %A, <8 x i16> %B, <8 x i16> %C) {
67 ;CHECK: mls {{v[0-31]+}}.8h, {{v[0-31]+}}.8h, {{v[0-31]+}}.8h
67 ;CHECK: mls {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
6868 %tmp1 = mul <8 x i16> %A, %B;
6969 %tmp2 = sub <8 x i16> %C, %tmp1;
7070 ret <8 x i16> %tmp2
7171 }
7272
7373 define <2 x i32> @mls2xi32(<2 x i32> %A, <2 x i32> %B, <2 x i32> %C) {
74 ;CHECK: mls {{v[0-31]+}}.2s, {{v[0-31]+}}.2s, {{v[0-31]+}}.2s
74 ;CHECK: mls {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
7575 %tmp1 = mul <2 x i32> %A, %B;
7676 %tmp2 = sub <2 x i32> %C, %tmp1;
7777 ret <2 x i32> %tmp2
7878 }
7979
8080 define <4 x i32> @mls4xi32(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) {
81 ;CHECK: mls {{v[0-31]+}}.4s, {{v[0-31]+}}.4s, {{v[0-31]+}}.4s
81 ;CHECK: mls {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
8282 %tmp1 = mul <4 x i32> %A, %B;
8383 %tmp2 = sub <4 x i32> %C, %tmp1;
8484 ret <4 x i32> %tmp2
0 ; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s
11
22 define <8 x i8> @movi8b() {
3 ;CHECK: movi {{v[0-31]+}}.8b, #0x8
3 ;CHECK: movi {{v[0-9]+}}.8b, #0x8
44 ret <8 x i8> < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
55 }
66
77 define <16 x i8> @movi16b() {
8 ;CHECK: movi {{v[0-31]+}}.16b, #0x8
8 ;CHECK: movi {{v[0-9]+}}.16b, #0x8
99 ret <16 x i8> < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
1010 }
1111
1212 define <2 x i32> @movi2s_lsl0() {
13 ;CHECK: movi {{v[0-31]+}}.2s, #0xff
13 ;CHECK: movi {{v[0-9]+}}.2s, #0xff
1414 ret <2 x i32> < i32 255, i32 255 >
1515 }
1616
1717 define <2 x i32> @movi2s_lsl8() {
18 ;CHECK: movi {{v[0-31]+}}.2s, #0xff, lsl #8
18 ;CHECK: movi {{v[0-9]+}}.2s, #0xff, lsl #8
1919 ret <2 x i32> < i32 65280, i32 65280 >
2020 }
2121
2222 define <2 x i32> @movi2s_lsl16() {
23 ;CHECK: movi {{v[0-31]+}}.2s, #0xff, lsl #16
23 ;CHECK: movi {{v[0-9]+}}.2s, #0xff, lsl #16
2424 ret <2 x i32> < i32 16711680, i32 16711680 >
2525
2626 }
2727
2828 define <2 x i32> @movi2s_lsl24() {
29 ;CHECK: movi {{v[0-31]+}}.2s, #0xff, lsl #24
29 ;CHECK: movi {{v[0-9]+}}.2s, #0xff, lsl #24
3030 ret <2 x i32> < i32 4278190080, i32 4278190080 >
3131 }
3232
3333 define <4 x i32> @movi4s_lsl0() {
34 ;CHECK: movi {{v[0-31]+}}.4s, #0xff
34 ;CHECK: movi {{v[0-9]+}}.4s, #0xff
3535 ret <4 x i32> < i32 255, i32 255, i32 255, i32 255 >
3636 }
3737
3838 define <4 x i32> @movi4s_lsl8() {
39 ;CHECK: movi {{v[0-31]+}}.4s, #0xff, lsl #8
39 ;CHECK: movi {{v[0-9]+}}.4s, #0xff, lsl #8
4040 ret <4 x i32> < i32 65280, i32 65280, i32 65280, i32 65280 >
4141 }
4242
4343 define <4 x i32> @movi4s_lsl16() {
44 ;CHECK: movi {{v[0-31]+}}.4s, #0xff, lsl #16
44 ;CHECK: movi {{v[0-9]+}}.4s, #0xff, lsl #16
4545 ret <4 x i32> < i32 16711680, i32 16711680, i32 16711680, i32 16711680 >
4646
4747 }
4848
4949 define <4 x i32> @movi4s_lsl24() {
50 ;CHECK: movi {{v[0-31]+}}.4s, #0xff, lsl #24
50 ;CHECK: movi {{v[0-9]+}}.4s, #0xff, lsl #24
5151 ret <4 x i32> < i32 4278190080, i32 4278190080, i32 4278190080, i32 4278190080 >
5252 }
5353
5454 define <4 x i16> @movi4h_lsl0() {
55 ;CHECK: movi {{v[0-31]+}}.4h, #0xff
55 ;CHECK: movi {{v[0-9]+}}.4h, #0xff
5656 ret <4 x i16> < i16 255, i16 255, i16 255, i16 255 >
5757 }
5858
5959 define <4 x i16> @movi4h_lsl8() {
60 ;CHECK: movi {{v[0-31]+}}.4h, #0xff, lsl #8
60 ;CHECK: movi {{v[0-9]+}}.4h, #0xff, lsl #8
6161 ret <4 x i16> < i16 65280, i16 65280, i16 65280, i16 65280 >
6262 }
6363
6464 define <8 x i16> @movi8h_lsl0() {
65 ;CHECK: movi {{v[0-31]+}}.8h, #0xff
65 ;CHECK: movi {{v[0-9]+}}.8h, #0xff
6666 ret <8 x i16> < i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255 >
6767 }
6868
6969 define <8 x i16> @movi8h_lsl8() {
70 ;CHECK: movi {{v[0-31]+}}.8h, #0xff, lsl #8
70 ;CHECK: movi {{v[0-9]+}}.8h, #0xff, lsl #8
7171 ret <8 x i16> < i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280 >
7272 }
7373
7474
7575 define <2 x i32> @mvni2s_lsl0() {
76 ;CHECK: mvni {{v[0-31]+}}.2s, #0x10
76 ;CHECK: mvni {{v[0-9]+}}.2s, #0x10
7777 ret <2 x i32> < i32 4294967279, i32 4294967279 >
7878 }
7979
8080 define <2 x i32> @mvni2s_lsl8() {
81 ;CHECK: mvni {{v[0-31]+}}.2s, #0x10, lsl #8
81 ;CHECK: mvni {{v[0-9]+}}.2s, #0x10, lsl #8
8282 ret <2 x i32> < i32 4294963199, i32 4294963199 >
8383 }
8484
8585 define <2 x i32> @mvni2s_lsl16() {
86 ;CHECK: mvni {{v[0-31]+}}.2s, #0x10, lsl #16
86 ;CHECK: mvni {{v[0-9]+}}.2s, #0x10, lsl #16
8787 ret <2 x i32> < i32 4293918719, i32 4293918719 >
8888 }
8989
9090 define <2 x i32> @mvni2s_lsl24() {
91 ;CHECK: mvni {{v[0-31]+}}.2s, #0x10, lsl #24
91 ;CHECK: mvni {{v[0-9]+}}.2s, #0x10, lsl #24
9292 ret <2 x i32> < i32 4026531839, i32 4026531839 >
9393 }
9494
9595 define <4 x i32> @mvni4s_lsl0() {
96 ;CHECK: mvni {{v[0-31]+}}.4s, #0x10
96 ;CHECK: mvni {{v[0-9]+}}.4s, #0x10
9797 ret <4 x i32> < i32 4294967279, i32 4294967279, i32 4294967279, i32 4294967279 >
9898 }
9999
100100 define <4 x i32> @mvni4s_lsl8() {
101 ;CHECK: mvni {{v[0-31]+}}.4s, #0x10, lsl #8
101 ;CHECK: mvni {{v[0-9]+}}.4s, #0x10, lsl #8
102102 ret <4 x i32> < i32 4294963199, i32 4294963199, i32 4294963199, i32 4294963199 >
103103 }
104104
105105 define <4 x i32> @mvni4s_lsl16() {
106 ;CHECK: mvni {{v[0-31]+}}.4s, #0x10, lsl #16
106 ;CHECK: mvni {{v[0-9]+}}.4s, #0x10, lsl #16
107107 ret <4 x i32> < i32 4293918719, i32 4293918719, i32 4293918719, i32 4293918719 >
108108
109109 }
110110
111111 define <4 x i32> @mvni4s_lsl24() {
112 ;CHECK: mvni {{v[0-31]+}}.4s, #0x10, lsl #24
112 ;CHECK: mvni {{v[0-9]+}}.4s, #0x10, lsl #24
113113 ret <4 x i32> < i32 4026531839, i32 4026531839, i32 4026531839, i32 4026531839 >
114114 }
115115
116116
117117 define <4 x i16> @mvni4h_lsl0() {
118 ;CHECK: mvni {{v[0-31]+}}.4h, #0x10
118 ;CHECK: mvni {{v[0-9]+}}.4h, #0x10
119119 ret <4 x i16> < i16 65519, i16 65519, i16 65519, i16 65519 >
120120 }
121121
122122 define <4 x i16> @mvni4h_lsl8() {
123 ;CHECK: mvni {{v[0-31]+}}.4h, #0x10, lsl #8
123 ;CHECK: mvni {{v[0-9]+}}.4h, #0x10, lsl #8
124124 ret <4 x i16> < i16 61439, i16 61439, i16 61439, i16 61439 >
125125 }
126126
127127 define <8 x i16> @mvni8h_lsl0() {
128 ;CHECK: mvni {{v[0-31]+}}.8h, #0x10
128 ;CHECK: mvni {{v[0-9]+}}.8h, #0x10
129129 ret <8 x i16> < i16 65519, i16 65519, i16 65519, i16 65519, i16 65519, i16 65519, i16 65519, i16 65519 >
130130 }
131131
132132 define <8 x i16> @mvni8h_lsl8() {
133 ;CHECK: mvni {{v[0-31]+}}.8h, #0x10, lsl #8
133 ;CHECK: mvni {{v[0-9]+}}.8h, #0x10, lsl #8
134134 ret <8 x i16> < i16 61439, i16 61439, i16 61439, i16 61439, i16 61439, i16 61439, i16 61439, i16 61439 >
135135 }
136136
137137
138138 define <2 x i32> @movi2s_msl8(<2 x i32> %a) {
139 ;CHECK: movi {{v[0-31]+}}.2s, #0xff, msl #8
139 ;CHECK: movi {{v[0-9]+}}.2s, #0xff, msl #8
140140 ret <2 x i32> < i32 65535, i32 65535 >
141141 }
142142
143143 define <2 x i32> @movi2s_msl16() {
144 ;CHECK: movi {{v[0-31]+}}.2s, #0xff, msl #16
144 ;CHECK: movi {{v[0-9]+}}.2s, #0xff, msl #16
145145 ret <2 x i32> < i32 16777215, i32 16777215 >
146146 }
147147
148148
149149 define <4 x i32> @movi4s_msl8() {
150 ;CHECK: movi {{v[0-31]+}}.4s, #0xff, msl #8
150 ;CHECK: movi {{v[0-9]+}}.4s, #0xff, msl #8
151151 ret <4 x i32> < i32 65535, i32 65535, i32 65535, i32 65535 >
152152 }
153153
154154 define <4 x i32> @movi4s_msl16() {
155 ;CHECK: movi {{v[0-31]+}}.4s, #0xff, msl #16
155 ;CHECK: movi {{v[0-9]+}}.4s, #0xff, msl #16
156156 ret <4 x i32> < i32 16777215, i32 16777215, i32 16777215, i32 16777215 >
157157 }
158158
159159 define <2 x i32> @mvni2s_msl8() {
160 ;CHECK: mvni {{v[0-31]+}}.2s, #0x10, msl #8
160 ;CHECK: mvni {{v[0-9]+}}.2s, #0x10, msl #8
161161 ret <2 x i32> < i32 18446744073709547264, i32 18446744073709547264>
162162 }
163163
164164 define <2 x i32> @mvni2s_msl16() {
165 ;CHECK: mvni {{v[0-31]+}}.2s, #0x10, msl #16
165 ;CHECK: mvni {{v[0-9]+}}.2s, #0x10, msl #16
166166 ret <2 x i32> < i32 18446744073708437504, i32 18446744073708437504>
167167 }
168168
169169 define <4 x i32> @mvni4s_msl8() {
170 ;CHECK: mvni {{v[0-31]+}}.4s, #0x10, msl #8
170 ;CHECK: mvni {{v[0-9]+}}.4s, #0x10, msl #8
171171 ret <4 x i32> < i32 18446744073709547264, i32 18446744073709547264, i32 18446744073709547264, i32 18446744073709547264>
172172 }
173173
174174 define <4 x i32> @mvni4s_msl16() {
175 ;CHECK: mvni {{v[0-31]+}}.4s, #0x10, msl #16
175 ;CHECK: mvni {{v[0-9]+}}.4s, #0x10, msl #16
176176 ret <4 x i32> < i32 18446744073708437504, i32 18446744073708437504, i32 18446744073708437504, i32 18446744073708437504>
177177 }
178178
179179 define <2 x i64> @movi2d() {
180 ;CHECK: movi {{v[0-31]+}}.2d, #0xff0000ff0000ffff
180 ;CHECK: movi {{v[0-9]+}}.2d, #0xff0000ff0000ffff
181181 ret <2 x i64> < i64 18374687574888349695, i64 18374687574888349695 >
182182 }
183183
184184 define <1 x i64> @movid() {
185 ;CHECK: movi {{d[0-31]+}}, #0xff0000ff0000ffff
185 ;CHECK: movi {{d[0-9]+}}, #0xff0000ff0000ffff
186186 ret <1 x i64> < i64 18374687574888349695 >
187187 }
188188
189189 define <2 x float> @fmov2s() {
190 ;CHECK: fmov {{v[0-31]+}}.2s, #-12.00000000
190 ;CHECK: fmov {{v[0-9]+}}.2s, #-12.00000000
191191 ret <2 x float> < float -1.2e1, float -1.2e1>
192192 }
193193
194194 define <4 x float> @fmov4s() {
195 ;CHECK: fmov {{v[0-31]+}}.4s, #-12.00000000
195 ;CHECK: fmov {{v[0-9]+}}.4s, #-12.00000000
196196 ret <4 x float> < float -1.2e1, float -1.2e1, float -1.2e1, float -1.2e1>
197197 }
198198
199199 define <2 x double> @fmov2d() {
200 ;CHECK: fmov {{v[0-31]+}}.2d, #-12.00000000
200 ;CHECK: fmov {{v[0-9]+}}.2d, #-12.00000000
201201 ret <2 x double> < double -1.2e1, double -1.2e1>
202202 }
203203
11
22
33 define <8 x i8> @mul8xi8(<8 x i8> %A, <8 x i8> %B) {
4 ;CHECK: mul {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
4 ;CHECK: mul {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
55 %tmp3 = mul <8 x i8> %A, %B;
66 ret <8 x i8> %tmp3
77 }
88
99 define <16 x i8> @mul16xi8(<16 x i8> %A, <16 x i8> %B) {
10 ;CHECK: mul {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
10 ;CHECK: mul {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
1111 %tmp3 = mul <16 x i8> %A, %B;
1212 ret <16 x i8> %tmp3
1313 }
1414
1515 define <4 x i16> @mul4xi16(<4 x i16> %A, <4 x i16> %B) {
16 ;CHECK: mul {{v[0-31]+}}.4h, {{v[0-31]+}}.4h, {{v[0-31]+}}.4h
16 ;CHECK: mul {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
1717 %tmp3 = mul <4 x i16> %A, %B;
1818 ret <4 x i16> %tmp3
1919 }
2020
2121 define <8 x i16> @mul8xi16(<8 x i16> %A, <8 x i16> %B) {
22 ;CHECK: mul {{v[0-31]+}}.8h, {{v[0-31]+}}.8h, {{v[0-31]+}}.8h
22 ;CHECK: mul {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
2323 %tmp3 = mul <8 x i16> %A, %B;
2424 ret <8 x i16> %tmp3
2525 }
2626
2727 define <2 x i32> @mul2xi32(<2 x i32> %A, <2 x i32> %B) {
28 ;CHECK: mul {{v[0-31]+}}.2s, {{v[0-31]+}}.2s, {{v[0-31]+}}.2s
28 ;CHECK: mul {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
2929 %tmp3 = mul <2 x i32> %A, %B;
3030 ret <2 x i32> %tmp3
3131 }
3232
3333 define <4 x i32> @mul4x32(<4 x i32> %A, <4 x i32> %B) {
34 ;CHECK: mul {{v[0-31]+}}.4s, {{v[0-31]+}}.4s, {{v[0-31]+}}.4s
34 ;CHECK: mul {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
3535 %tmp3 = mul <4 x i32> %A, %B;
3636 ret <4 x i32> %tmp3
3737 }
3838
3939 define <2 x float> @mul2xfloat(<2 x float> %A, <2 x float> %B) {
40 ;CHECK: fmul {{v[0-31]+}}.2s, {{v[0-31]+}}.2s, {{v[0-31]+}}.2s
40 ;CHECK: fmul {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
4141 %tmp3 = fmul <2 x float> %A, %B;
4242 ret <2 x float> %tmp3
4343 }
4444
4545 define <4 x float> @mul4xfloat(<4 x float> %A, <4 x float> %B) {
46 ;CHECK: fmul {{v[0-31]+}}.4s, {{v[0-31]+}}.4s, {{v[0-31]+}}.4s
46 ;CHECK: fmul {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
4747 %tmp3 = fmul <4 x float> %A, %B;
4848 ret <4 x float> %tmp3
4949 }
5050 define <2 x double> @mul2xdouble(<2 x double> %A, <2 x double> %B) {
51 ;CHECK: fmul {{v[0-31]+}}.2d, {{v[0-31]+}}.2d, {{v[0-31]+}}.2d
51 ;CHECK: fmul {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
5252 %tmp3 = fmul <2 x double> %A, %B;
5353 ret <2 x double> %tmp3
5454 }
5555
5656
5757 define <2 x float> @div2xfloat(<2 x float> %A, <2 x float> %B) {
58 ;CHECK: fdiv {{v[0-31]+}}.2s, {{v[0-31]+}}.2s, {{v[0-31]+}}.2s
58 ;CHECK: fdiv {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
5959 %tmp3 = fdiv <2 x float> %A, %B;
6060 ret <2 x float> %tmp3
6161 }
6262
6363 define <4 x float> @div4xfloat(<4 x float> %A, <4 x float> %B) {
64 ;CHECK: fdiv {{v[0-31]+}}.4s, {{v[0-31]+}}.4s, {{v[0-31]+}}.4s
64 ;CHECK: fdiv {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
6565 %tmp3 = fdiv <4 x float> %A, %B;
6666 ret <4 x float> %tmp3
6767 }
6868 define <2 x double> @div2xdouble(<2 x double> %A, <2 x double> %B) {
69 ;CHECK: fdiv {{v[0-31]+}}.2d, {{v[0-31]+}}.2d, {{v[0-31]+}}.2d
69 ;CHECK: fdiv {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
7070 %tmp3 = fdiv <2 x double> %A, %B;
7171 ret <2 x double> %tmp3
7272 }
0 ; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s
11
22 define <1 x i64> @add1xi64(<1 x i64> %A, <1 x i64> %B) {
3 ;CHECK: add {{d[0-31]+}}, {{d[0-31]+}}, {{d[0-31]+}}
3 ;CHECK: add {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
44 %tmp3 = add <1 x i64> %A, %B;
55 ret <1 x i64> %tmp3
66 }
77
88 define <1 x i64> @sub1xi64(<1 x i64> %A, <1 x i64> %B) {
9 ;CHECK: sub {{d[0-31]+}}, {{d[0-31]+}}, {{d[0-31]+}}
9 ;CHECK: sub {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
1010 %tmp3 = sub <1 x i64> %A, %B;
1111 ret <1 x i64> %tmp3
1212 }
1717 define <1 x i64> @test_add_v1i64(<1 x i64> %lhs, <1 x i64> %rhs) {
1818 ; CHECK: test_add_v1i64:
1919 %tmp1 = call <1 x i64> @llvm.aarch64.neon.vaddds(<1 x i64> %lhs, <1 x i64> %rhs)
20 ; CHECK: add {{d[0-31]+}}, {{d[0-31]+}}, {{d[0-31]+}}
20 ; CHECK: add {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
2121 ret <1 x i64> %tmp1
2222 }
2323
2424 define <1 x i64> @test_uadd_v1i64(<1 x i64> %lhs, <1 x i64> %rhs) {
2525 ; CHECK: test_uadd_v1i64:
2626 %tmp1 = call <1 x i64> @llvm.aarch64.neon.vadddu(<1 x i64> %lhs, <1 x i64> %rhs)
27 ;CHECK: add {{d[0-31]+}}, {{d[0-31]+}}, {{d[0-31]+}}
27 ;CHECK: add {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
2828 ret <1 x i64> %tmp1
2929 }
3030
3434 define <1 x i64> @test_sub_v1i64(<1 x i64> %lhs, <1 x i64> %rhs) {
3535 ; CHECK: test_sub_v1i64:
3636 %tmp1 = call <1 x i64> @llvm.aarch64.neon.vsubds(<1 x i64> %lhs, <1 x i64> %rhs)
37 ; CHECK: sub {{d[0-31]+}}, {{d[0-31]+}}, {{d[0-31]+}}
37 ; CHECK: sub {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
3838 ret <1 x i64> %tmp1
3939 }
4040
4141 define <1 x i64> @test_usub_v1i64(<1 x i64> %lhs, <1 x i64> %rhs) {
4242 ; CHECK: test_usub_v1i64:
4343 %tmp1 = call <1 x i64> @llvm.aarch64.neon.vsubdu(<1 x i64> %lhs, <1 x i64> %rhs)
44 ;CHECK: sub {{d[0-31]+}}, {{d[0-31]+}}, {{d[0-31]+}}
44 ;CHECK: sub {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
4545 ret <1 x i64> %tmp1
4646 }
4747
44
55 define float @test_fmla_ss4S(float %a, float %b, <4 x float> %v) {
66 ; CHECK: test_fmla_ss4S
7 ; CHECK: fmla {{s[0-9]+}}, {{s[0-9]+}}, {{v[0-31]+}}.s[3]
7 ; CHECK: fmla {{s[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}.s[3]
88 %tmp1 = extractelement <4 x float> %v, i32 3
99 %tmp2 = call float @llvm.fma.f32(float %b, float %tmp1, float %a)
1010 ret float %tmp2
1212
1313 define float @test_fmla_ss4S_swap(float %a, float %b, <4 x float> %v) {
1414 ; CHECK: test_fmla_ss4S_swap
15 ; CHECK: fmla {{s[0-9]+}}, {{s[0-9]+}}, {{v[0-31]+}}.s[3]
15 ; CHECK: fmla {{s[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}.s[3]
1616 %tmp1 = extractelement <4 x float> %v, i32 3
1717 %tmp2 = call float @llvm.fma.f32(float %tmp1, float %a, float %a)
1818 ret float %tmp2
2020
2121 define float @test_fmla_ss2S(float %a, float %b, <2 x float> %v) {
2222 ; CHECK: test_fmla_ss2S
23 ; CHECK: fmla {{s[0-9]+}}, {{s[0-9]+}}, {{v[0-31]+}}.s[1]
23 ; CHECK: fmla {{s[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}.s[1]
2424 %tmp1 = extractelement <2 x float> %v, i32 1
2525 %tmp2 = call float @llvm.fma.f32(float %b, float %tmp1, float %a)
2626 ret float %tmp2
2828
2929 define double @test_fmla_ddD(double %a, double %b, <1 x double> %v) {
3030 ; CHECK: test_fmla_ddD
31 ; CHECK: fmla {{d[0-9]+}}, {{d[0-9]+}}, {{v[0-31]+}}.d[0]
31 ; CHECK: fmla {{d[0-9]+}}, {{d[0-9]+}}, {{v[0-9]+}}.d[0]
3232 %tmp1 = extractelement <1 x double> %v, i32 0
3333 %tmp2 = call double @llvm.fma.f64(double %b, double %tmp1, double %a)
3434 ret double %tmp2
3636
3737 define double @test_fmla_dd2D(double %a, double %b, <2 x double> %v) {
3838 ; CHECK: test_fmla_dd2D
39 ; CHECK: fmla {{d[0-9]+}}, {{d[0-9]+}}, {{v[0-31]+}}.d[1]
39 ; CHECK: fmla {{d[0-9]+}}, {{d[0-9]+}}, {{v[0-9]+}}.d[1]
4040 %tmp1 = extractelement <2 x double> %v, i32 1
4141 %tmp2 = call double @llvm.fma.f64(double %b, double %tmp1, double %a)
4242 ret double %tmp2
4444
4545 define double @test_fmla_dd2D_swap(double %a, double %b, <2 x double> %v) {
4646 ; CHECK: test_fmla_dd2D_swap
47 ; CHECK: fmla {{d[0-9]+}}, {{d[0-9]+}}, {{v[0-31]+}}.d[1]
47 ; CHECK: fmla {{d[0-9]+}}, {{d[0-9]+}}, {{v[0-9]+}}.d[1]
4848 %tmp1 = extractelement <2 x double> %v, i32 1
4949 %tmp2 = call double @llvm.fma.f64(double %tmp1, double %b, double %a)
5050 ret double %tmp2
5252
5353 define float @test_fmls_ss4S(float %a, float %b, <4 x float> %v) {
5454 ; CHECK: test_fmls_ss4S
55 ; CHECK: fmls {{s[0-9]+}}, {{s[0-9]+}}, {{v[0-31]+}}.s[3]
55 ; CHECK: fmls {{s[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}.s[3]
5656 %tmp1 = extractelement <4 x float> %v, i32 3
5757 %tmp2 = fsub float -0.0, %tmp1
5858 %tmp3 = call float @llvm.fma.f32(float %tmp2, float %tmp1, float %a)
6161
6262 define float @test_fmls_ss4S_swap(float %a, float %b, <4 x float> %v) {
6363 ; CHECK: test_fmls_ss4S_swap
64 ; CHECK: fmls {{s[0-9]+}}, {{s[0-9]+}}, {{v[0-31]+}}.s[3]
64 ; CHECK: fmls {{s[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}.s[3]
6565 %tmp1 = extractelement <4 x float> %v, i32 3
6666 %tmp2 = fsub float -0.0, %tmp1
6767 %tmp3 = call float @llvm.fma.f32(float %tmp1, float %tmp2, float %a)
7171
7272 define float @test_fmls_ss2S(float %a, float %b, <2 x float> %v) {
7373 ; CHECK: test_fmls_ss2S
74 ; CHECK: fmls {{s[0-9]+}}, {{s[0-9]+}}, {{v[0-31]+}}.s[1]
74 ; CHECK: fmls {{s[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}.s[1]
7575 %tmp1 = extractelement <2 x float> %v, i32 1
7676 %tmp2 = fsub float -0.0, %tmp1
7777 %tmp3 = call float @llvm.fma.f32(float %tmp2, float %tmp1, float %a)
8080
8181 define double @test_fmls_ddD(double %a, double %b, <1 x double> %v) {
8282 ; CHECK: test_fmls_ddD
83 ; CHECK: fmls {{d[0-9]+}}, {{d[0-9]+}}, {{v[0-31]+}}.d[0]
83 ; CHECK: fmls {{d[0-9]+}}, {{d[0-9]+}}, {{v[0-9]+}}.d[0]
8484 %tmp1 = extractelement <1 x double> %v, i32 0
8585 %tmp2 = fsub double -0.0, %tmp1
8686 %tmp3 = call double @llvm.fma.f64(double %tmp2, double %tmp1, double %a)
8989
9090 define double @test_fmls_dd2D(double %a, double %b, <2 x double> %v) {
9191 ; CHECK: test_fmls_dd2D
92 ; CHECK: fmls {{d[0-9]+}}, {{d[0-9]+}}, {{v[0-31]+}}.d[1]
92 ; CHECK: fmls {{d[0-9]+}}, {{d[0-9]+}}, {{v[0-9]+}}.d[1]
9393 %tmp1 = extractelement <2 x double> %v, i32 1
9494 %tmp2 = fsub double -0.0, %tmp1
9595 %tmp3 = call double @llvm.fma.f64(double %tmp2, double %tmp1, double %a)
9898
9999 define double @test_fmls_dd2D_swap(double %a, double %b, <2 x double> %v) {
100100 ; CHECK: test_fmls_dd2D_swap
101 ; CHECK: fmls {{d[0-9]+}}, {{d[0-9]+}}, {{v[0-31]+}}.d[1]
101 ; CHECK: fmls {{d[0-9]+}}, {{d[0-9]+}}, {{v[0-9]+}}.d[1]
102102 %tmp1 = extractelement <2 x double> %v, i32 1
103103 %tmp2 = fsub double -0.0, %tmp1
104104 %tmp3 = call double @llvm.fma.f64(double %tmp1, double %tmp2, double %a)
11
22 define float @test_fmul_lane_ss2S(float %a, <2 x float> %v) {
33 ; CHECK: test_fmul_lane_ss2S
4 ; CHECK: fmul {{s[0-31]+}}, {{s[0-31]+}}, {{v[0-31]+}}.s[1]
4 ; CHECK: fmul {{s[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}.s[1]
55 %tmp1 = extractelement <2 x float> %v, i32 1
66 %tmp2 = fmul float %a, %tmp1;
77 ret float %tmp2;
99
1010 define float @test_fmul_lane_ss2S_swap(float %a, <2 x float> %v) {
1111 ; CHECK: test_fmul_lane_ss2S_swap
12 ; CHECK: fmul {{s[0-31]+}}, {{s[0-31]+}}, {{v[0-31]+}}.s[1]
12 ; CHECK: fmul {{s[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}.s[1]
1313 %tmp1 = extractelement <2 x float> %v, i32 1
1414 %tmp2 = fmul float %tmp1, %a;
1515 ret float %tmp2;
1818
1919 define float @test_fmul_lane_ss4S(float %a, <4 x float> %v) {
2020 ; CHECK: test_fmul_lane_ss4S
21 ; CHECK: fmul {{s[0-31]+}}, {{s[0-31]+}}, {{v[0-31]+}}.s[3]
21 ; CHECK: fmul {{s[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}.s[3]
2222 %tmp1 = extractelement <4 x float> %v, i32 3
2323 %tmp2 = fmul float %a, %tmp1;
2424 ret float %tmp2;
2626
2727 define float @test_fmul_lane_ss4S_swap(float %a, <4 x float> %v) {
2828 ; CHECK: test_fmul_lane_ss4S_swap
29 ; CHECK: fmul {{s[0-31]+}}, {{s[0-31]+}}, {{v[0-31]+}}.s[3]
29 ; CHECK: fmul {{s[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}.s[3]
3030 %tmp1 = extractelement <4 x float> %v, i32 3
3131 %tmp2 = fmul float %tmp1, %a;
3232 ret float %tmp2;
3535
3636 define double @test_fmul_lane_ddD(double %a, <1 x double> %v) {
3737 ; CHECK: test_fmul_lane_ddD
38 ; CHECK: fmul {{d[0-31]+}}, {{d[0-31]+}}, {{v[0-31]+}}.d[0]
38 ; CHECK: fmul {{d[0-9]+}}, {{d[0-9]+}}, {{v[0-9]+}}.d[0]
3939 %tmp1 = extractelement <1 x double> %v, i32 0
4040 %tmp2 = fmul double %a, %tmp1;
4141 ret double %tmp2;
4545
4646 define double @test_fmul_lane_dd2D(double %a, <2 x double> %v) {
4747 ; CHECK: test_fmul_lane_dd2D
48 ; CHECK: fmul {{d[0-31]+}}, {{d[0-31]+}}, {{v[0-31]+}}.d[1]
48 ; CHECK: fmul {{d[0-9]+}}, {{d[0-9]+}}, {{v[0-9]+}}.d[1]
4949 %tmp1 = extractelement <2 x double> %v, i32 1
5050 %tmp2 = fmul double %a, %tmp1;
5151 ret double %tmp2;
5454
5555 define double @test_fmul_lane_dd2D_swap(double %a, <2 x double> %v) {
5656 ; CHECK: test_fmul_lane_dd2D_swap
57 ; CHECK: fmul {{d[0-31]+}}, {{d[0-31]+}}, {{v[0-31]+}}.d[1]
57 ; CHECK: fmul {{d[0-9]+}}, {{d[0-9]+}}, {{v[0-9]+}}.d[1]
5858 %tmp1 = extractelement <2 x double> %v, i32 1
5959 %tmp2 = fmul double %tmp1, %a;
6060 ret double %tmp2;
6464
6565 define float @test_fmulx_lane_f32(float %a, <2 x float> %v) {
6666 ; CHECK: test_fmulx_lane_f32
67 ; CHECK: fmulx {{s[0-31]+}}, {{s[0-31]+}}, {{v[0-31]+}}.s[1]
67 ; CHECK: fmulx {{s[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}.s[1]
6868 %tmp1 = extractelement <2 x float> %v, i32 1
6969 %tmp2 = call float @llvm.aarch64.neon.vmulx.f32(float %a, float %tmp1)
7070 ret float %tmp2;
7272
7373 define float @test_fmulx_laneq_f32(float %a, <4 x float> %v) {
7474 ; CHECK: test_fmulx_laneq_f32
75 ; CHECK: fmulx {{s[0-31]+}}, {{s[0-31]+}}, {{v[0-31]+}}.s[3]
75 ; CHECK: fmulx {{s[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}.s[3]
7676 %tmp1 = extractelement <4 x float> %v, i32 3
7777 %tmp2 = call float @llvm.aarch64.neon.vmulx.f32(float %a, float %tmp1)
7878 ret float %tmp2;
8080
8181 define float @test_fmulx_laneq_f32_swap(float %a, <4 x float> %v) {
8282 ; CHECK: test_fmulx_laneq_f32_swap
83 ; CHECK: fmulx {{s[0-31]+}}, {{s[0-31]+}}, {{v[0-31]+}}.s[3]
83 ; CHECK: fmulx {{s[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}.s[3]
8484 %tmp1 = extractelement <4 x float> %v, i32 3
8585 %tmp2 = call float @llvm.aarch64.neon.vmulx.f32(float %tmp1, float %a)
8686 ret float %tmp2;
9090
9191 define double @test_fmulx_lane_f64(double %a, <1 x double> %v) {
9292 ; CHECK: test_fmulx_lane_f64
93 ; CHECK: fmulx {{d[0-31]+}}, {{d[0-31]+}}, {{v[0-31]+}}.d[0]
93 ; CHECK: fmulx {{d[0-9]+}}, {{d[0-9]+}}, {{v[0-9]+}}.d[0]
9494 %tmp1 = extractelement <1 x double> %v, i32 0
9595 %tmp2 = call double @llvm.aarch64.neon.vmulx.f64(double %a, double %tmp1)
9696 ret double %tmp2;
9898
9999 define double @test_fmulx_laneq_f64_0(double %a, <2 x double> %v) {
100100 ; CHECK: test_fmulx_laneq_f64_0
101 ; CHECK: fmulx {{d[0-31]+}}, {{d[0-31]+}}, {{v[0-31]+}}.d[0]
101 ; CHECK: fmulx {{d[0-9]+}}, {{d[0-9]+}}, {{v[0-9]+}}.d[0]
102102 %tmp1 = extractelement <2 x double> %v, i32 0
103103 %tmp2 = call double @llvm.aarch64.neon.vmulx.f64(double %a, double %tmp1)
104104 ret double %tmp2;
107107
108108 define double @test_fmulx_laneq_f64_1(double %a, <2 x double> %v) {
109109 ; CHECK: test_fmulx_laneq_f64_1
110 ; CHECK: fmulx {{d[0-31]+}}, {{d[0-31]+}}, {{v[0-31]+}}.d[1]
110 ; CHECK: fmulx {{d[0-9]+}}, {{d[0-9]+}}, {{v[0-9]+}}.d[1]
111111 %tmp1 = extractelement <2 x double> %v, i32 1
112112 %tmp2 = call double @llvm.aarch64.neon.vmulx.f64(double %a, double %tmp1)
113113 ret double %tmp2;
115115
116116 define double @test_fmulx_laneq_f64_1_swap(double %a, <2 x double> %v) {
117117 ; CHECK: test_fmulx_laneq_f64_1_swap
118 ; CHECK: fmulx {{d[0-31]+}}, {{d[0-31]+}}, {{v[0-31]+}}.d[1]
118 ; CHECK: fmulx {{d[0-9]+}}, {{d[0-9]+}}, {{v[0-9]+}}.d[1]
119119 %tmp1 = extractelement <2 x double> %v, i32 1
120120 %tmp2 = call double @llvm.aarch64.neon.vmulx.f64(double %tmp1, double %a)
121121 ret double %tmp2;
11
22 define float @test_dup_sv2S(<2 x float> %v) {
33 ;CHECK: test_dup_sv2S
4 ;CHECK: dup {{s[0-31]+}}, {{v[0-31]+}}.s[1]
4 ;CHECK: dup {{s[0-9]+}}, {{v[0-9]+}}.s[1]
55 %tmp1 = extractelement <2 x float> %v, i32 1
66 ret float %tmp1
77 }
88
99 define float @test_dup_sv4S(<4 x float> %v) {
1010 ;CHECK: test_dup_sv4S
11 ;CHECK: dup {{s[0-31]+}}, {{v[0-31]+}}.s[0]
11 ;CHECK: dup {{s[0-9]+}}, {{v[0-9]+}}.s[0]
1212 %tmp1 = extractelement <4 x float> %v, i32 0
1313 ret float %tmp1
1414 }
1515
1616 define double @test_dup_dvD(<1 x double> %v) {
1717 ;CHECK: test_dup_dvD
18 ;CHECK-NOT: dup {{d[0-31]+}}, {{v[0-31]+}}.d[0]
18 ;CHECK-NOT: dup {{d[0-9]+}}, {{v[0-9]+}}.d[0]
1919 ;CHECK: ret
2020 %tmp1 = extractelement <1 x double> %v, i32 0
2121 ret double %tmp1
2323
2424 define double @test_dup_dv2D(<2 x double> %v) {
2525 ;CHECK: test_dup_dv2D
26 ;CHECK: dup {{d[0-31]+}}, {{v[0-31]+}}.d[1]
26 ;CHECK: dup {{d[0-9]+}}, {{v[0-9]+}}.d[1]
2727 %tmp1 = extractelement <2 x double> %v, i32 1
2828 ret double %tmp1
2929 }
3030
3131 define <1 x i8> @test_vector_dup_bv16B(<16 x i8> %v1) {
3232 ;CHECK: test_vector_dup_bv16B
33 ;CHECK: dup {{b[0-31]+}}, {{v[0-31]+}}.b[14]
33 ;CHECK: dup {{b[0-9]+}}, {{v[0-9]+}}.b[14]
3434 %shuffle.i = shufflevector <16 x i8> %v1, <16 x i8> undef, <1 x i32>
3535 ret <1 x i8> %shuffle.i
3636 }
3737
3838 define <1 x i8> @test_vector_dup_bv8B(<8 x i8> %v1) {
3939 ;CHECK: test_vector_dup_bv8B
40 ;CHECK: dup {{b[0-31]+}}, {{v[0-31]+}}.b[7]
40 ;CHECK: dup {{b[0-9]+}}, {{v[0-9]+}}.b[7]
4141 %shuffle.i = shufflevector <8 x i8> %v1, <8 x i8> undef, <1 x i32>
4242 ret <1 x i8> %shuffle.i
4343 }
4444
4545 define <1 x i16> @test_vector_dup_hv8H(<8 x i16> %v1) {
4646 ;CHECK: test_vector_dup_hv8H
47 ;CHECK: dup {{h[0-31]+}}, {{v[0-31]+}}.h[7]
47 ;CHECK: dup {{h[0-9]+}}, {{v[0-9]+}}.h[7]
4848 %shuffle.i = shufflevector <8 x i16> %v1, <8 x i16> undef, <1 x i32>
4949 ret <1 x i16> %shuffle.i
5050 }
5151
5252 define <1 x i16> @test_vector_dup_hv4H(<4 x i16> %v1) {
5353 ;CHECK: test_vector_dup_hv4H
54 ;CHECK: dup {{h[0-31]+}}, {{v[0-31]+}}.h[3]
54 ;CHECK: dup {{h[0-9]+}}, {{v[0-9]+}}.h[3]
5555 %shuffle.i = shufflevector <4 x i16> %v1, <4 x i16> undef, <1 x i32>
5656 ret <1 x i16> %shuffle.i
5757 }
5858
5959 define <1 x i32> @test_vector_dup_sv4S(<4 x i32> %v1) {
6060 ;CHECK: test_vector_dup_sv4S
61 ;CHECK: dup {{s[0-31]+}}, {{v[0-31]+}}.s[3]
61 ;CHECK: dup {{s[0-9]+}}, {{v[0-9]+}}.s[3]
6262 %shuffle = shufflevector <4 x i32> %v1, <4 x i32> undef, <1 x i32>
6363 ret <1 x i32> %shuffle
6464 }
6565
6666 define <1 x i32> @test_vector_dup_sv2S(<2 x i32> %v1) {
6767 ;CHECK: test_vector_dup_sv2S
68 ;CHECK: dup {{s[0-31]+}}, {{v[0-31]+}}.s[1]
68 ;CHECK: dup {{s[0-9]+}}, {{v[0-9]+}}.s[1]
6969 %shuffle = shufflevector <2 x i32> %v1, <2 x i32> undef, <1 x i32>
7070 ret <1 x i32> %shuffle
7171 }
7272
7373 define <1 x i64> @test_vector_dup_dv2D(<2 x i64> %v1) {
7474 ;CHECK: test_vector_dup_dv2D
75 ;CHECK: dup {{d[0-31]+}}, {{v[0-31]+}}.d[1]
75 ;CHECK: dup {{d[0-9]+}}, {{v[0-9]+}}.d[1]
7676 %shuffle.i = shufflevector <2 x i64> %v1, <2 x i64> undef, <1 x i32>
7777 ret <1 x i64> %shuffle.i
7878 }
7979
8080 define <1 x i64> @test_vector_copy_dup_dv2D(<1 x i64> %a, <2 x i64> %c) {
8181 ;CHECK: test_vector_copy_dup_dv2D
82 ;CHECK: dup {{d[0-31]+}}, {{v[0-31]+}}.d[1]
82 ;CHECK: dup {{d[0-9]+}}, {{v[0-9]+}}.d[1]
8383 %vget_lane = extractelement <2 x i64> %c, i32 1
8484 %vset_lane = insertelement <1 x i64> undef, i64 %vget_lane, i32 0
8585 ret <1 x i64> %vset_lane
66 define <1 x i64> @test_urshl_v1i64(<1 x i64> %lhs, <1 x i64> %rhs) {
77 ; CHECK: test_urshl_v1i64:
88 %tmp1 = call <1 x i64> @llvm.arm.neon.vrshiftu.v1i64(<1 x i64> %lhs, <1 x i64> %rhs)
9 ;CHECK: urshl {{d[0-31]+}}, {{d[0-31]+}}, {{d[0-31]+}}
9 ;CHECK: urshl {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
1010 ret <1 x i64> %tmp1
1111 }
1212
1313 define <1 x i64> @test_srshl_v1i64(<1 x i64> %lhs, <1 x i64> %rhs) {
1414 ; CHECK: test_srshl_v1i64:
1515 %tmp1 = call <1 x i64> @llvm.arm.neon.vrshifts.v1i64(<1 x i64> %lhs, <1 x i64> %rhs)
16 ;CHECK: srshl {{d[0-31]+}}, {{d[0-31]+}}, {{d[0-31]+}}
16 ;CHECK: srshl {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
1717 ret <1 x i64> %tmp1
1818 }
1919
2323 define <1 x i64> @test_urshl_v1i64_aarch64(<1 x i64> %lhs, <1 x i64> %rhs) {
2424 ; CHECK: test_urshl_v1i64_aarch64:
2525 %tmp1 = call <1 x i64> @llvm.aarch64.neon.vrshldu(<1 x i64> %lhs, <1 x i64> %rhs)
26 ;CHECK: urshl {{d[0-31]+}}, {{d[0-31]+}}, {{d[0-31]+}}
26 ;CHECK: urshl {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
2727 ret <1 x i64> %tmp1
2828 }
2929
3030 define <1 x i64> @test_srshl_v1i64_aarch64(<1 x i64> %lhs, <1 x i64> %rhs) {
3131 ; CHECK: test_srshl_v1i64_aarch64:
3232 %tmp1 = call <1 x i64> @llvm.aarch64.neon.vrshlds(<1 x i64> %lhs, <1 x i64> %rhs)
33 ;CHECK: srshl {{d[0-31]+}}, {{d[0-31]+}}, {{d[0-31]+}}
33 ;CHECK: srshl {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
3434 ret <1 x i64> %tmp1
3535 }
3636
55 define <1 x i8> @test_uqadd_v1i8_aarch64(<1 x i8> %lhs, <1 x i8> %rhs) {
66 ; CHECK: test_uqadd_v1i8_aarch64:
77 %tmp1 = call <1 x i8> @llvm.arm.neon.vqaddu.v1i8(<1 x i8> %lhs, <1 x i8> %rhs)
8 ;CHECK: uqadd {{b[0-31]+}}, {{b[0-31]+}}, {{b[0-31]+}}
8 ;CHECK: uqadd {{b[0-9]+}}, {{b[0-9]+}}, {{b[0-9]+}}
99 ret <1 x i8> %tmp1
1010 }
1111
1212 define <1 x i8> @test_sqadd_v1i8_aarch64(<1 x i8> %lhs, <1 x i8> %rhs) {
1313 ; CHECK: test_sqadd_v1i8_aarch64:
1414 %tmp1 = call <1 x i8> @llvm.arm.neon.vqadds.v1i8(<1 x i8> %lhs, <1 x i8> %rhs)
15 ;CHECK: sqadd {{b[0-31]+}}, {{b[0-31]+}}, {{b[0-31]+}}
15 ;CHECK: sqadd {{b[0-9]+}}, {{b[0-9]+}}, {{b[0-9]+}}
1616 ret <1 x i8> %tmp1
1717 }
1818
2222 define <1 x i8> @test_uqsub_v1i8_aarch64(<1 x i8> %lhs, <1 x i8> %rhs) {
2323 ; CHECK: test_uqsub_v1i8_aarch64:
2424 %tmp1 = call <1 x i8> @llvm.arm.neon.vqsubu.v1i8(<1 x i8> %lhs, <1 x i8> %rhs)
25 ;CHECK: uqsub {{b[0-31]+}}, {{b[0-31]+}}, {{b[0-31]+}}
25 ;CHECK: uqsub {{b[0-9]+}}, {{b[0-9]+}}, {{b[0-9]+}}
2626 ret <1 x i8> %tmp1
2727 }
2828
2929 define <1 x i8> @test_sqsub_v1i8_aarch64(<1 x i8> %lhs, <1 x i8> %rhs) {
3030 ; CHECK: test_sqsub_v1i8_aarch64:
3131 %tmp1 = call <1 x i8> @llvm.arm.neon.vqsubs.v1i8(<1 x i8> %lhs, <1 x i8> %rhs)
32 ;CHECK: sqsub {{b[0-31]+}}, {{b[0-31]+}}, {{b[0-31]+}}
32 ;CHECK: sqsub {{b[0-9]+}}, {{b[0-9]+}}, {{b[0-9]+}}
3333 ret <1 x i8> %tmp1
3434 }
3535
3939 define <1 x i16> @test_uqadd_v1i16_aarch64(<1 x i16> %lhs, <1 x i16> %rhs) {
4040 ; CHECK: test_uqadd_v1i16_aarch64:
4141 %tmp1 = call <1 x i16> @llvm.arm.neon.vqaddu.v1i16(<1 x i16> %lhs, <1 x i16> %rhs)
42 ;CHECK: uqadd {{h[0-31]+}}, {{h[0-31]+}}, {{h[0-31]+}}
42 ;CHECK: uqadd {{h[0-9]+}}, {{h[0-9]+}}, {{h[0-9]+}}
4343 ret <1 x i16> %tmp1
4444 }
4545
4646 define <1 x i16> @test_sqadd_v1i16_aarch64(<1 x i16> %lhs, <1 x i16> %rhs) {
4747 ; CHECK: test_sqadd_v1i16_aarch64:
4848 %tmp1 = call <1 x i16> @llvm.arm.neon.vqadds.v1i16(<1 x i16> %lhs, <1 x i16> %rhs)
49 ;CHECK: sqadd {{h[0-31]+}}, {{h[0-31]+}}, {{h[0-31]+}}
49 ;CHECK: sqadd {{h[0-9]+}}, {{h[0-9]+}}, {{h[0-9]+}}
5050 ret <1 x i16> %tmp1
5151 }
5252
5656 define <1 x i16> @test_uqsub_v1i16_aarch64(<1 x i16> %lhs, <1 x i16> %rhs) {
5757 ; CHECK: test_uqsub_v1i16_aarch64:
5858 %tmp1 = call <1 x i16> @llvm.arm.neon.vqsubu.v1i16(<1 x i16> %lhs, <1 x i16> %rhs)
59 ;CHECK: uqsub {{h[0-31]+}}, {{h[0-31]+}}, {{h[0-31]+}}
59 ;CHECK: uqsub {{h[0-9]+}}, {{h[0-9]+}}, {{h[0-9]+}}
6060 ret <1 x i16> %tmp1
6161 }
6262
6363 define <1 x i16> @test_sqsub_v1i16_aarch64(<1 x i16> %lhs, <1 x i16> %rhs) {
6464 ; CHECK: test_sqsub_v1i16_aarch64:
6565 %tmp1 = call <1 x i16> @llvm.arm.neon.vqsubs.v1i16(<1 x i16> %lhs, <1 x i16> %rhs)
66 ;CHECK: sqsub {{h[0-31]+}}, {{h[0-31]+}}, {{h[0-31]+}}
66 ;CHECK: sqsub {{h[0-9]+}}, {{h[0-9]+}}, {{h[0-9]+}}
6767 ret <1 x i16> %tmp1
6868 }
6969
7373 define <1 x i32> @test_uqadd_v1i32_aarch64(<1 x i32> %lhs, <1 x i32> %rhs) {
7474 ; CHECK: test_uqadd_v1i32_aarch64:
7575 %tmp1 = call <1 x i32> @llvm.arm.neon.vqaddu.v1i32(<1 x i32> %lhs, <1 x i32> %rhs)
76 ;CHECK: uqadd {{s[0-31]+}}, {{s[0-31]+}}, {{s[0-31]+}}
76 ;CHECK: uqadd {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
7777 ret <1 x i32> %tmp1
7878 }
7979
8080 define <1 x i32> @test_sqadd_v1i32_aarch64(<1 x i32> %lhs, <1 x i32> %rhs) {
8181 ; CHECK: test_sqadd_v1i32_aarch64:
8282 %tmp1 = call <1 x i32> @llvm.arm.neon.vqadds.v1i32(<1 x i32> %lhs, <1 x i32> %rhs)
83 ;CHECK: sqadd {{s[0-31]+}}, {{s[0-31]+}}, {{s[0-31]+}}
83 ;CHECK: sqadd {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
8484 ret <1 x i32> %tmp1
8585 }
8686
9090 define <1 x i32> @test_uqsub_v1i32_aarch64(<1 x i32> %lhs, <1 x i32> %rhs) {
9191 ; CHECK: test_uqsub_v1i32_aarch64:
9292 %tmp1 = call <1 x i32> @llvm.arm.neon.vqsubu.v1i32(<1 x i32> %lhs, <1 x i32> %rhs)
93 ;CHECK: uqsub {{s[0-31]+}}, {{s[0-31]+}}, {{s[0-31]+}}
93 ;CHECK: uqsub {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
9494 ret <1 x i32> %tmp1
9595 }
9696
9898 define <1 x i32> @test_sqsub_v1i32_aarch64(<1 x i32> %lhs, <1 x i32> %rhs) {
9999 ; CHECK: test_sqsub_v1i32_aarch64:
100100 %tmp1 = call <1 x i32> @llvm.arm.neon.vqsubs.v1i32(<1 x i32> %lhs, <1 x i32> %rhs)
101 ;CHECK: sqsub {{s[0-31]+}}, {{s[0-31]+}}, {{s[0-31]+}}
101 ;CHECK: sqsub {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
102102 ret <1 x i32> %tmp1
103103 }
104104
108108 define <1 x i64> @test_uqadd_v1i64_aarch64(<1 x i64> %lhs, <1 x i64> %rhs) {
109109 ; CHECK: test_uqadd_v1i64_aarch64:
110110 %tmp1 = call <1 x i64> @llvm.arm.neon.vqaddu.v1i64(<1 x i64> %lhs, <1 x i64> %rhs)
111 ;CHECK: uqadd {{d[0-31]+}}, {{d[0-31]+}}, {{d[0-31]+}}
111 ;CHECK: uqadd {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
112112 ret <1 x i64> %tmp1
113113 }
114114
115115 define <1 x i64> @test_sqadd_v1i64_aarch64(<1 x i64> %lhs, <1 x i64> %rhs) {
116116 ; CHECK: test_sqadd_v1i64_aarch64:
117117 %tmp1 = call <1 x i64> @llvm.arm.neon.vqadds.v1i64(<1 x i64> %lhs, <1 x i64> %rhs)
118 ;CHECK: sqadd {{d[0-31]+}}, {{d[0-31]+}}, {{d[0-31]+}}
118 ;CHECK: sqadd {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
119119 ret <1 x i64> %tmp1
120120 }
121121
125125 define <1 x i64> @test_uqsub_v1i64_aarch64(<1 x i64> %lhs, <1 x i64> %rhs) {
126126 ; CHECK: test_uqsub_v1i64_aarch64:
127127 %tmp1 = call <1 x i64> @llvm.arm.neon.vqsubu.v1i64(<1 x i64> %lhs, <1 x i64> %rhs)
128 ;CHECK: uqsub {{d[0-31]+}}, {{d[0-31]+}}, {{d[0-31]+}}
128 ;CHECK: uqsub {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
129129 ret <1 x i64> %tmp1
130130 }
131131
132132 define <1 x i64> @test_sqsub_v1i64_aarch64(<1 x i64> %lhs, <1 x i64> %rhs) {
133133 ; CHECK: test_sqsub_v1i64_aarch64:
134134 %tmp1 = call <1 x i64> @llvm.arm.neon.vqsubs.v1i64(<1 x i64> %lhs, <1 x i64> %rhs)
135 ;CHECK: sqsub {{d[0-31]+}}, {{d[0-31]+}}, {{d[0-31]+}}
135 ;CHECK: sqsub {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
136136 ret <1 x i64> %tmp1
137137 }
138138
55 define <1 x i64> @test_uqrshl_v1i64(<1 x i64> %lhs, <1 x i64> %rhs) {
66 ; CHECK: test_uqrshl_v1i64:
77 %tmp1 = call <1 x i64> @llvm.arm.neon.vqrshiftu.v1i64(<1 x i64> %lhs, <1 x i64> %rhs)
8 ;CHECK: uqrshl {{d[0-31]+}}, {{d[0-31]+}}, {{d[0-31]+}}
8 ;CHECK: uqrshl {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
99
1010 ret <1 x i64> %tmp1
1111 }
1313 define <1 x i64> @test_sqrshl_v1i64(<1 x i64> %lhs, <1 x i64> %rhs) {
1414 ; CHECK: test_sqrshl_v1i64:
1515 %tmp1 = call <1 x i64> @llvm.arm.neon.vqrshifts.v1i64(<1 x i64> %lhs, <1 x i64> %rhs)
16 ;CHECK: sqrshl {{d[0-31]+}}, {{d[0-31]+}}, {{d[0-31]+}}
16 ;CHECK: sqrshl {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
1717 ret <1 x i64> %tmp1
1818 }
1919
2323 define <1 x i8> @test_uqrshl_v1i8_aarch64(<1 x i8> %lhs, <1 x i8> %rhs) {
2424 ; CHECK: test_uqrshl_v1i8_aarch64:
2525 %tmp1 = call <1 x i8> @llvm.aarch64.neon.vqrshlu.v1i8(<1 x i8> %lhs, <1 x i8> %rhs)
26 ;CHECK: uqrshl {{b[0-31]+}}, {{b[0-31]+}}, {{b[0-31]+}}
26 ;CHECK: uqrshl {{b[0-9]+}}, {{b[0-9]+}}, {{b[0-9]+}}
2727
2828 ret <1 x i8> %tmp1
2929 }
3131 define <1 x i8> @test_sqrshl_v1i8_aarch64(<1 x i8> %lhs, <1 x i8> %rhs) {
3232 ; CHECK: test_sqrshl_v1i8_aarch64:
3333 %tmp1 = call <1 x i8> @llvm.aarch64.neon.vqrshls.v1i8(<1 x i8> %lhs, <1 x i8> %rhs)
34 ;CHECK: sqrshl {{b[0-31]+}}, {{b[0-31]+}}, {{b[0-31]+}}
34 ;CHECK: sqrshl {{b[0-9]+}}, {{b[0-9]+}}, {{b[0-9]+}}
3535 ret <1 x i8> %tmp1
3636 }
3737
4141 define <1 x i16> @test_uqrshl_v1i16_aarch64(<1 x i16> %lhs, <1 x i16> %rhs) {
4242 ; CHECK: test_uqrshl_v1i16_aarch64:
4343 %tmp1 = call <1 x i16> @llvm.aarch64.neon.vqrshlu.v1i16(<1 x i16> %lhs, <1 x i16> %rhs)
44 ;CHECK: uqrshl {{h[0-31]+}}, {{h[0-31]+}}, {{h[0-31]+}}
44 ;CHECK: uqrshl {{h[0-9]+}}, {{h[0-9]+}}, {{h[0-9]+}}
4545
4646 ret <1 x i16> %tmp1
4747 }
4949 define <1 x i16> @test_sqrshl_v1i16_aarch64(<1 x i16> %lhs, <1 x i16> %rhs) {
5050 ; CHECK: test_sqrshl_v1i16_aarch64:
5151 %tmp1 = call <1 x i16> @llvm.aarch64.neon.vqrshls.v1i16(<1 x i16> %lhs, <1 x i16> %rhs)
52 ;CHECK: sqrshl {{h[0-31]+}}, {{h[0-31]+}}, {{h[0-31]+}}
52 ;CHECK: sqrshl {{h[0-9]+}}, {{h[0-9]+}}, {{h[0-9]+}}
5353 ret <1 x i16> %tmp1
5454 }
5555
5959 define <1 x i32> @test_uqrshl_v1i32_aarch64(<1 x i32> %lhs, <1 x i32> %rhs) {
6060 ; CHECK: test_uqrshl_v1i32_aarch64:
6161 %tmp1 = call <1 x i32> @llvm.aarch64.neon.vqrshlu.v1i32(<1 x i32> %lhs, <1 x i32> %rhs)
62 ;CHECK: uqrshl {{s[0-31]+}}, {{s[0-31]+}}, {{s[0-31]+}}
62 ;CHECK: uqrshl {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
6363
6464 ret <1 x i32> %tmp1
6565 }
6767 define <1 x i32> @test_sqrshl_v1i32_aarch64(<1 x i32> %lhs, <1 x i32> %rhs) {
6868 ; CHECK: test_sqrshl_v1i32_aarch64:
6969 %tmp1 = call <1 x i32> @llvm.aarch64.neon.vqrshls.v1i32(<1 x i32> %lhs, <1 x i32> %rhs)
70 ;CHECK: sqrshl {{s[0-31]+}}, {{s[0-31]+}}, {{s[0-31]+}}
70 ;CHECK: sqrshl {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
7171 ret <1 x i32> %tmp1
7272 }
7373
7777 define <1 x i64> @test_uqrshl_v1i64_aarch64(<1 x i64> %lhs, <1 x i64> %rhs) {
7878 ; CHECK: test_uqrshl_v1i64_aarch64:
7979 %tmp1 = call <1 x i64> @llvm.aarch64.neon.vqrshlu.v1i64(<1 x i64> %lhs, <1 x i64> %rhs)
80 ;CHECK: uqrshl {{d[0-31]+}}, {{d[0-31]+}}, {{d[0-31]+}}
80 ;CHECK: uqrshl {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
8181
8282 ret <1 x i64> %tmp1
8383 }
8585 define <1 x i64> @test_sqrshl_v1i64_aarch64(<1 x i64> %lhs, <1 x i64> %rhs) {
8686 ; CHECK: test_sqrshl_v1i64_aarch64:
8787 %tmp1 = call <1 x i64> @llvm.aarch64.neon.vqrshls.v1i64(<1 x i64> %lhs, <1 x i64> %rhs)
88 ;CHECK: sqrshl {{d[0-31]+}}, {{d[0-31]+}}, {{d[0-31]+}}
88 ;CHECK: sqrshl {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
8989 ret <1 x i64> %tmp1
9090 }
9191
55 define <1 x i64> @test_uqshl_v1i64(<1 x i64> %lhs, <1 x i64> %rhs) {
66 ; CHECK: test_uqshl_v1i64:
77 %tmp1 = call <1 x i64> @llvm.arm.neon.vqshiftu.v1i64(<1 x i64> %lhs, <1 x i64> %rhs)
8 ;CHECK: uqshl {{d[0-31]+}}, {{d[0-31]+}}, {{d[0-31]+}}
8 ;CHECK: uqshl {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
99 ret <1 x i64> %tmp1
1010 }
1111
1212 define <1 x i64> @test_sqshl_v1i64(<1 x i64> %lhs, <1 x i64> %rhs) {
1313 ; CHECK: test_sqshl_v1i64:
1414 %tmp1 = call <1 x i64> @llvm.arm.neon.vqshifts.v1i64(<1 x i64> %lhs, <1 x i64> %rhs)
15 ;CHECK: sqshl {{d[0-31]+}}, {{d[0-31]+}}, {{d[0-31]+}}
15 ;CHECK: sqshl {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
1616 ret <1 x i64> %tmp1
1717 }
1818
2222 define <1 x i8> @test_uqshl_v1i8_aarch64(<1 x i8> %lhs, <1 x i8> %rhs) {
2323 ; CHECK: test_uqshl_v1i8_aarch64:
2424 %tmp1 = call <1 x i8> @llvm.aarch64.neon.vqshlu.v1i8(<1 x i8> %lhs, <1 x i8> %rhs)
25 ;CHECK: uqshl {{b[0-31]+}}, {{b[0-31]+}}, {{b[0-31]+}}
25 ;CHECK: uqshl {{b[0-9]+}}, {{b[0-9]+}}, {{b[0-9]+}}
2626 ret <1 x i8> %tmp1
2727 }
2828
2929 define <1 x i8> @test_sqshl_v1i8_aarch64(<1 x i8> %lhs, <1 x i8> %rhs) {
3030 ; CHECK: test_sqshl_v1i8_aarch64:
3131 %tmp1 = call <1 x i8> @llvm.aarch64.neon.vqshls.v1i8(<1 x i8> %lhs, <1 x i8> %rhs)
32 ;CHECK: sqshl {{b[0-31]+}}, {{b[0-31]+}}, {{b[0-31]+}}
32 ;CHECK: sqshl {{b[0-9]+}}, {{b[0-9]+}}, {{b[0-9]+}}
3333 ret <1 x i8> %tmp1
3434 }
3535
3939 define <1 x i16> @test_uqshl_v1i16_aarch64(<1 x i16> %lhs, <1 x i16> %rhs) {
4040 ; CHECK: test_uqshl_v1i16_aarch64:
4141 %tmp1 = call <1 x i16> @llvm.aarch64.neon.vqshlu.v1i16(<1 x i16> %lhs, <1 x i16> %rhs)
42 ;CHECK: uqshl {{h[0-31]+}}, {{h[0-31]+}}, {{h[0-31]+}}
42 ;CHECK: uqshl {{h[0-9]+}}, {{h[0-9]+}}, {{h[0-9]+}}
4343 ret <1 x i16> %tmp1
4444 }
4545
4646 define <1 x i16> @test_sqshl_v1i16_aarch64(<1 x i16> %lhs, <1 x i16> %rhs) {
4747 ; CHECK: test_sqshl_v1i16_aarch64:
4848 %tmp1 = call <1 x i16> @llvm.aarch64.neon.vqshls.v1i16(<1 x i16> %lhs, <1 x i16> %rhs)
49 ;CHECK: sqshl {{h[0-31]+}}, {{h[0-31]+}}, {{h[0-31]+}}
49 ;CHECK: sqshl {{h[0-9]+}}, {{h[0-9]+}}, {{h[0-9]+}}
5050 ret <1 x i16> %tmp1
5151 }
5252
5656 define <1 x i32> @test_uqshl_v1i32_aarch64(<1 x i32> %lhs, <1 x i32> %rhs) {
5757 ; CHECK: test_uqshl_v1i32_aarch64:
5858 %tmp1 = call <1 x i32> @llvm.aarch64.neon.vqshlu.v1i32(<1 x i32> %lhs, <1 x i32> %rhs)
59 ;CHECK: uqshl {{s[0-31]+}}, {{s[0-31]+}}, {{s[0-31]+}}
59 ;CHECK: uqshl {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
6060 ret <1 x i32> %tmp1
6161 }
6262
6363 define <1 x i32> @test_sqshl_v1i32_aarch64(<1 x i32> %lhs, <1 x i32> %rhs) {
6464 ; CHECK: test_sqshl_v1i32_aarch64:
6565 %tmp1 = call <1 x i32> @llvm.aarch64.neon.vqshls.v1i32(<1 x i32> %lhs, <1 x i32> %rhs)
66 ;CHECK: sqshl {{s[0-31]+}}, {{s[0-31]+}}, {{s[0-31]+}}
66 ;CHECK: sqshl {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
6767 ret <1 x i32> %tmp1
6868 }
6969
7373 define <1 x i64> @test_uqshl_v1i64_aarch64(<1 x i64> %lhs, <1 x i64> %rhs) {
7474 ; CHECK: test_uqshl_v1i64_aarch64:
7575 %tmp1 = call <1 x i64> @llvm.aarch64.neon.vqshlu.v1i64(<1 x i64> %lhs, <1 x i64> %rhs)
76 ;CHECK: uqshl {{d[0-31]+}}, {{d[0-31]+}}, {{d[0-31]+}}
76 ;CHECK: uqshl {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
7777 ret <1 x i64> %tmp1
7878 }
7979
8080 define <1 x i64> @test_sqshl_v1i64_aarch64(<1 x i64> %lhs, <1 x i64> %rhs) {
8181 ; CHECK: test_sqshl_v1i64_aarch64:
8282 %tmp1 = call <1 x i64> @llvm.aarch64.neon.vqshls.v1i64(<1 x i64> %lhs, <1 x i64> %rhs)
83 ;CHECK: sqshl {{d[0-31]+}}, {{d[0-31]+}}, {{d[0-31]+}}
83 ;CHECK: sqshl {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
8484 ret <1 x i64> %tmp1
8585 }
8686
55 define <1 x i64> @test_ushl_v1i64(<1 x i64> %lhs, <1 x i64> %rhs) {
66 ; CHECK: test_ushl_v1i64:
77 %tmp1 = call <1 x i64> @llvm.arm.neon.vshiftu.v1i64(<1 x i64> %lhs, <1 x i64> %rhs)
8 ; CHECK: ushl {{d[0-31]+}}, {{d[0-31]+}}, {{d[0-31]+}}
8 ; CHECK: ushl {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
99
1010 ret <1 x i64> %tmp1
1111 }
1313 define <1 x i64> @test_sshl_v1i64(<1 x i64> %lhs, <1 x i64> %rhs) {
1414 ; CHECK: test_sshl_v1i64:
1515 %tmp1 = call <1 x i64> @llvm.arm.neon.vshifts.v1i64(<1 x i64> %lhs, <1 x i64> %rhs)
16 ; CHECK: sshl {{d[0-31]+}}, {{d[0-31]+}}, {{d[0-31]+}}
16 ; CHECK: sshl {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
1717 ret <1 x i64> %tmp1
1818 }
1919
2323 define <1 x i64> @test_ushl_v1i64_aarch64(<1 x i64> %lhs, <1 x i64> %rhs) {
2424 ; CHECK: test_ushl_v1i64_aarch64:
2525 %tmp1 = call <1 x i64> @llvm.aarch64.neon.vshldu(<1 x i64> %lhs, <1 x i64> %rhs)
26 ; CHECK: ushl {{d[0-31]+}}, {{d[0-31]+}}, {{d[0-31]+}}
26 ; CHECK: ushl {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
2727 ret <1 x i64> %tmp1
2828 }
2929
3030 define <1 x i64> @test_sshl_v1i64_aarch64(<1 x i64> %lhs, <1 x i64> %rhs) {
3131 ; CHECK: test_sshl_v1i64_aarch64:
3232 %tmp1 = call <1 x i64> @llvm.aarch64.neon.vshlds(<1 x i64> %lhs, <1 x i64> %rhs)
33 ; CHECK: sshl {{d[0-31]+}}, {{d[0-31]+}}, {{d[0-31]+}}
33 ; CHECK: sshl {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
3434 ret <1 x i64> %tmp1
3535 }
3636