llvm.org GIT mirror llvm / 2464810
Add a base class for Mips TargetMachines and add Mips64 TargetMachines. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140233 91177308-0d34-0410-b5e6-96231b3b80d8 Akira Hatanaka 9 years ago
7 changed file(s) with 93 addition(s) and 8 deletion(s). Raw diff Collapse all Expand all
1717
1818 MipsMCAsmInfo::MipsMCAsmInfo(const Target &T, StringRef TT) {
1919 Triple TheTriple(TT);
20 if (TheTriple.getArch() == Triple::mips)
20 if ((TheTriple.getArch() == Triple::mips) ||
21 (TheTriple.getArch() == Triple::mips64))
2122 IsLittleEndian = false;
2223
2324 AlignmentIsInBytes = false;
8080 // Register the MC asm info.
8181 RegisterMCAsmInfoFn X(TheMipsTarget, createMipsMCAsmInfo);
8282 RegisterMCAsmInfoFn Y(TheMipselTarget, createMipsMCAsmInfo);
83 RegisterMCAsmInfoFn A(TheMips64Target, createMipsMCAsmInfo);
84 RegisterMCAsmInfoFn B(TheMips64elTarget, createMipsMCAsmInfo);
8385
8486 // Register the MC codegen info.
8587 TargetRegistry::RegisterMCCodeGenInfo(TheMipsTarget,
8688 createMipsMCCodeGenInfo);
8789 TargetRegistry::RegisterMCCodeGenInfo(TheMipselTarget,
8890 createMipsMCCodeGenInfo);
91 TargetRegistry::RegisterMCCodeGenInfo(TheMips64Target,
92 createMipsMCCodeGenInfo);
93 TargetRegistry::RegisterMCCodeGenInfo(TheMips64elTarget,
94 createMipsMCCodeGenInfo);
8995
9096 // Register the MC instruction info.
9197 TargetRegistry::RegisterMCInstrInfo(TheMipsTarget, createMipsMCInstrInfo);
98 TargetRegistry::RegisterMCInstrInfo(TheMipselTarget, createMipsMCInstrInfo);
99 TargetRegistry::RegisterMCInstrInfo(TheMips64Target, createMipsMCInstrInfo);
100 TargetRegistry::RegisterMCInstrInfo(TheMips64elTarget, createMipsMCInstrInfo);
92101
93102 // Register the MC register info.
94103 TargetRegistry::RegisterMCRegInfo(TheMipsTarget, createMipsMCRegisterInfo);
95104 TargetRegistry::RegisterMCRegInfo(TheMipselTarget, createMipsMCRegisterInfo);
105 TargetRegistry::RegisterMCRegInfo(TheMips64Target, createMipsMCRegisterInfo);
106 TargetRegistry::RegisterMCRegInfo(TheMips64elTarget,
107 createMipsMCRegisterInfo);
96108
97109 // Register the MC subtarget info.
98110 TargetRegistry::RegisterMCSubtargetInfo(TheMipsTarget,
111 createMipsMCSubtargetInfo);
112 TargetRegistry::RegisterMCSubtargetInfo(TheMipselTarget,
113 createMipsMCSubtargetInfo);
114 TargetRegistry::RegisterMCSubtargetInfo(TheMips64Target,
115 createMipsMCSubtargetInfo);
116 TargetRegistry::RegisterMCSubtargetInfo(TheMips64elTarget,
99117 createMipsMCSubtargetInfo);
100118
101119 // Register the MCInstPrinter.
103121 createMipsMCInstPrinter);
104122 TargetRegistry::RegisterMCInstPrinter(TheMipselTarget,
105123 createMipsMCInstPrinter);
124 TargetRegistry::RegisterMCInstPrinter(TheMips64Target,
125 createMipsMCInstPrinter);
126 TargetRegistry::RegisterMCInstPrinter(TheMips64elTarget,
127 createMipsMCInstPrinter);
106128 }
2020
2121 extern Target TheMipsTarget;
2222 extern Target TheMipselTarget;
23 extern Target TheMips64Target;
24 extern Target TheMips64elTarget;
2325
2426 } // End llvm namespace
2527
454454 extern "C" void LLVMInitializeMipsAsmPrinter() {
455455 RegisterAsmPrinter X(TheMipsTarget);
456456 RegisterAsmPrinter Y(TheMipselTarget);
457 }
457 RegisterAsmPrinter A(TheMips64Target);
458 RegisterAsmPrinter B(TheMips64elTarget);
459 }
1818
1919 extern "C" void LLVMInitializeMipsTarget() {
2020 // Register the target.
21 RegisterTargetMachineTargetMachine> X(TheMipsTarget);
21 RegisterTargetMachineebTargetMachine> X(TheMipsTarget);
2222 RegisterTargetMachine Y(TheMipselTarget);
23 RegisterTargetMachine A(TheMips64Target);
24 RegisterTargetMachine B(TheMips64elTarget);
2325 }
2426
2527 // DataLayout --> Big-endian, 32-bit pointer/ABI/alignment
3335 MipsTargetMachine(const Target &T, StringRef TT,
3436 StringRef CPU, StringRef FS,
3537 Reloc::Model RM, CodeModel::Model CM,
36 bool isLittle=false):
38 bool isLittle):
3739 LLVMTargetMachine(T, TT, CPU, FS, RM, CM),
3840 Subtarget(TT, CPU, FS, isLittle),
39 DataLayout(isLittle ?
40 std::string("e-p:32:32:32-i8:8:32-i16:16:32-i64:64:64-n32") :
41 std::string("E-p:32:32:32-i8:8:32-i16:16:32-i64:64:64-n32")),
41 DataLayout(isLittle ?
42 (Subtarget.isABI_N64() ?
43 "e-p:64:64:64-i8:8:32-i16:16:32-i64:64:64-n32" :
44 "e-p:32:32:32-i8:8:32-i16:16:32-i64:64:64-n32") :
45 (Subtarget.isABI_N64() ?
46 "E-p:64:64:64-i8:8:32-i16:16:32-i64:64:64-n32" :
47 "E-p:32:32:32-i8:8:32-i16:16:32-i64:64:64-n32")),
4248 InstrInfo(*this),
4349 FrameLowering(Subtarget),
4450 TLInfo(*this), TSInfo(*this), JITInfo() {
4551 }
4652
53 MipsebTargetMachine::
54 MipsebTargetMachine(const Target &T, StringRef TT,
55 StringRef CPU, StringRef FS,
56 Reloc::Model RM, CodeModel::Model CM) :
57 MipsTargetMachine(T, TT, CPU, FS, RM, CM, false) {}
58
4759 MipselTargetMachine::
4860 MipselTargetMachine(const Target &T, StringRef TT,
4961 StringRef CPU, StringRef FS,
5062 Reloc::Model RM, CodeModel::Model CM) :
63 MipsTargetMachine(T, TT, CPU, FS, RM, CM, true) {}
64
65 Mips64ebTargetMachine::
66 Mips64ebTargetMachine(const Target &T, StringRef TT,
67 StringRef CPU, StringRef FS,
68 Reloc::Model RM, CodeModel::Model CM) :
69 MipsTargetMachine(T, TT, CPU, FS, RM, CM, false) {}
70
71 Mips64elTargetMachine::
72 Mips64elTargetMachine(const Target &T, StringRef TT,
73 StringRef CPU, StringRef FS,
74 Reloc::Model RM, CodeModel::Model CM) :
5175 MipsTargetMachine(T, TT, CPU, FS, RM, CM, true) {}
5276
5377 // Install an instruction selector pass using
7979
8080 };
8181
82 /// MipselTargetMachine - Mipsel target machine.
82 /// MipsebTargetMachine - Mips32 big endian target machine.
83 ///
84 class MipsebTargetMachine : public MipsTargetMachine {
85 public:
86 MipsebTargetMachine(const Target &T, StringRef TT,
87 StringRef CPU, StringRef FS,
88 Reloc::Model RM, CodeModel::Model CM);
89 };
90
91 /// MipselTargetMachine - Mips32 little endian target machine.
8392 ///
8493 class MipselTargetMachine : public MipsTargetMachine {
8594 public:
8897 Reloc::Model RM, CodeModel::Model CM);
8998 };
9099
100 /// MipsebTargetMachine - Mips32 big endian target machine.
101 ///
102 class Mips64ebTargetMachine : public MipsTargetMachine {
103 public:
104 Mips64ebTargetMachine(const Target &T, StringRef TT,
105 StringRef CPU, StringRef FS,
106 Reloc::Model RM, CodeModel::Model CM);
107 };
108
109 /// MipselTargetMachine - Mips32 little endian target machine.
110 ///
111 class Mips64elTargetMachine : public MipsTargetMachine {
112 public:
113 Mips64elTargetMachine(const Target &T, StringRef TT,
114 StringRef CPU, StringRef FS,
115 Reloc::Model RM, CodeModel::Model CM);
116 };
91117 } // End llvm namespace
92118
93119 #endif
1212 using namespace llvm;
1313
1414 Target llvm::TheMipsTarget, llvm::TheMipselTarget;
15 Target llvm::TheMips64Target, llvm::TheMips64elTarget;
1516
1617 extern "C" void LLVMInitializeMipsTargetInfo() {
1718 RegisterTarget
1920
2021 RegisterTarget
2122 /*HasJIT=*/true> Y(TheMipselTarget, "mipsel", "Mipsel");
23
24 RegisterTarget
25 /*HasJIT=*/false> A(TheMips64Target, "mips64", "Mips64 [experimental]");
26
27 RegisterTarget
28 /*HasJIT=*/false> B(TheMips64elTarget,
29 "mips64el", "Mips64el [experimental]");
2230 }