llvm.org GIT mirror llvm / 2457f2c
Implement @llvm.returnaddress. rdar://8015977. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104421 91177308-0d34-0410-b5e6-96231b3b80d8 Evan Cheng 10 years ago
22 changed file(s) with 185 addition(s) and 32 deletion(s). Raw diff Collapse all Expand all
124124 /// to builtin \@llvm.frameaddress.
125125 bool FrameAddressTaken;
126126
127 /// ReturnAddressTaken - This boolean keeps track of whether there is a call
128 /// to builtin \@llvm.returnaddress.
129 bool ReturnAddressTaken;
130
127131 /// StackSize - The prolog/epilog code inserter calculates the final stack
128132 /// offsets for all of the fixed size objects, updating the Objects list
129133 /// above. It then updates StackSize to contain the number of bytes that need
192196 StackSize = NumFixedObjects = OffsetAdjustment = MaxAlignment = 0;
193197 HasVarSizedObjects = false;
194198 FrameAddressTaken = false;
199 ReturnAddressTaken = false;
195200 AdjustsStack = false;
196201 HasCalls = false;
197202 StackProtectorIdx = -1;
221226 /// \@llvm.frameaddress in this function.
222227 bool isFrameAddressTaken() const { return FrameAddressTaken; }
223228 void setFrameAddressIsTaken(bool T) { FrameAddressTaken = T; }
229
230 /// isReturnAddressTaken - This method may be called any time after instruction
231 /// selection is complete to determine if there is a call to
232 /// \@llvm.returnaddress in this function.
233 bool isReturnAddressTaken() const { return ReturnAddressTaken; }
234 void setReturnAddressIsTaken(bool s) { ReturnAddressTaken = s; }
224235
225236 /// getObjectIndexBegin - Return the minimum frame object index.
226237 ///
351351 /// storeRegToStackSlot(). Returns false otherwise.
352352 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
353353 MachineBasicBlock::iterator MI,
354 const std::vector &CSI) const {
354 const std::vector &CSI,
355 const TargetRegisterInfo *TRI) const {
355356 return false;
356357 }
357358
361362 /// Returns false otherwise.
362363 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
363364 MachineBasicBlock::iterator MI,
364 const std::vector &CSI) const {
365 const std::vector &CSI,
366 const TargetRegisterInfo *TRI) const {
365367 return false;
366368 }
367369
295295 if (! ShrinkWrapThisFunction) {
296296 // Spill using target interface.
297297 I = EntryBlock->begin();
298 if (!TII.spillCalleeSavedRegisters(*EntryBlock, I, CSI)) {
298 if (!TII.spillCalleeSavedRegisters(*EntryBlock, I, CSI, TRI)) {
299299 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
300300 // Add the callee-saved register as live-in.
301301 // It's killed at the spill.
325325
326326 // Restore all registers immediately before the return and any
327327 // terminators that preceed it.
328 if (!TII.restoreCalleeSavedRegisters(*MBB, I, CSI)) {
328 if (!TII.restoreCalleeSavedRegisters(*MBB, I, CSI, TRI)) {
329329 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
330330 TII.loadRegFromStackSlot(*MBB, I, CSI[i].getReg(),
331331 CSI[i].getFrameIdx(),
2727 #include "llvm/CodeGen/MachineInstrBuilder.h"
2828 #include "llvm/CodeGen/MachineJumpTableInfo.h"
2929 #include "llvm/CodeGen/MachineMemOperand.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
3031 #include "llvm/CodeGen/PseudoSourceValue.h"
3132 #include "llvm/MC/MCAsmInfo.h"
3233 #include "llvm/Support/CommandLine.h"
193194 MFI->insert(MBBI, NewMIs[1]);
194195 MFI->insert(MBBI, NewMIs[0]);
195196 return NewMIs[0];
197 }
198
199 bool
200 ARMBaseInstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
201 MachineBasicBlock::iterator MI,
202 const std::vector &CSI,
203 const TargetRegisterInfo *TRI) const {
204 if (CSI.empty())
205 return false;
206
207 DebugLoc DL;
208 if (MI != MBB.end()) DL = MI->getDebugLoc();
209
210 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
211 unsigned Reg = CSI[i].getReg();
212 bool isKill = true;
213
214 // Add the callee-saved register as live-in unless it's LR and
215 // @llvm.returnaddress is called. If LR is returned for @llvm.returnaddress
216 // then it's already added to the function and entry block live-in sets.
217 if (Reg == ARM::LR) {
218 MachineFunction &MF = *MBB.getParent();
219 if (MF.getFrameInfo()->isReturnAddressTaken() &&
220 MF.getRegInfo().isLiveIn(Reg))
221 isKill = false;
222 }
223
224 if (isKill)
225 MBB.addLiveIn(Reg);
226
227 // Insert the spill to the stack frame. The register is killed at the spill
228 //
229 storeRegToStackSlot(MBB, MI, Reg, isKill,
230 CSI[i].getFrameIdx(), CSI[i].getRegClass(), TRI);
231 }
232 return true;
196233 }
197234
198235 // Branch analysis.
199199 virtual const ARMBaseRegisterInfo &getRegisterInfo() const =0;
200200 const ARMSubtarget &getSubtarget() const { return Subtarget; }
201201
202 bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
203 MachineBasicBlock::iterator MI,
204 const std::vector &CSI,
205 const TargetRegisterInfo *TRI) const;
206
202207 // Branch analysis.
203208 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
204209 MachineBasicBlock *&FBB,
17001700 RC = ARM::GPRRegisterClass;
17011701
17021702 // Transform the arguments stored in physical registers into virtual ones.
1703 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1703 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
17041704 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
17051705
17061706 SDValue ArgValue2;
21402140 return DAG.getNode(ARMISD::CNEG, dl, VT, AbsVal, AbsVal, ARMCC, CCR, Cmp);
21412141 }
21422142
2143 SDValue ARMTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{
2144 MachineFunction &MF = DAG.getMachineFunction();
2145 MachineFrameInfo *MFI = MF.getFrameInfo();
2146 MFI->setReturnAddressIsTaken(true);
2147
2148 EVT VT = Op.getValueType();
2149 DebugLoc dl = Op.getDebugLoc();
2150 unsigned Depth = cast(Op.getOperand(0))->getZExtValue();
2151 if (Depth) {
2152 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
2153 SDValue Offset = DAG.getConstant(4, MVT::i32);
2154 return DAG.getLoad(VT, dl, DAG.getEntryNode(),
2155 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
2156 NULL, 0, false, false, 0);
2157 }
2158
2159 // Return LR, which contains the return address. Mark it an implicit live-in.
2160 ARMFunctionInfo *AFI = MF.getInfo();
2161 TargetRegisterClass *RC = AFI->isThumb1OnlyFunction()
2162 ? ARM::tGPRRegisterClass : ARM::GPRRegisterClass;
2163 unsigned Reg = MF.addLiveIn(ARM::LR, RC);
2164 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
2165 }
2166
21432167 SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
21442168 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
21452169 MFI->setFrameAddressIsTaken(true);
2170
21462171 EVT VT = Op.getValueType();
21472172 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
21482173 unsigned Depth = cast(Op.getOperand(0))->getZExtValue();
31573182 case ISD::FP_TO_SINT:
31583183 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG);
31593184 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
3160 case ISD::RETURNADDR: break;
3185 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
31613186 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
31623187 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
31633188 case ISD::EH_SJLJ_LONGJMP: return LowerEH_SJLJ_LONGJMP(Op, DAG);
301301 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
302302 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
303303 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
304 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
304305 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
305306 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
306307 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
1616 #include "ARMMachineFunctionInfo.h"
1717 #include "llvm/CodeGen/MachineFrameInfo.h"
1818 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
1920 #include "llvm/CodeGen/MachineMemOperand.h"
2021 #include "llvm/CodeGen/PseudoSourceValue.h"
2122 #include "llvm/ADT/SmallVector.h"
149150 bool Thumb1InstrInfo::
150151 spillCalleeSavedRegisters(MachineBasicBlock &MBB,
151152 MachineBasicBlock::iterator MI,
152 const std::vector &CSI) const {
153 const std::vector &CSI,
154 const TargetRegisterInfo *TRI) const {
153155 if (CSI.empty())
154156 return false;
155157
160162 AddDefaultPred(MIB);
161163 for (unsigned i = CSI.size(); i != 0; --i) {
162164 unsigned Reg = CSI[i-1].getReg();
163 // Add the callee-saved register as live-in. It's killed at the spill.
164 MBB.addLiveIn(Reg);
165 MIB.addReg(Reg, RegState::Kill);
165 bool isKill = true;
166
167 // Add the callee-saved register as live-in unless it's LR and
168 // @llvm.returnaddress is called. If LR is returned for @llvm.returnaddress
169 // then it's already added to the function and entry block live-in sets.
170 if (Reg == ARM::LR) {
171 MachineFunction &MF = *MBB.getParent();
172 if (MF.getFrameInfo()->isReturnAddressTaken() &&
173 MF.getRegInfo().isLiveIn(Reg))
174 isKill = false;
175 }
176
177 if (isKill) {
178 MBB.addLiveIn(Reg);
179 MIB.addReg(Reg, RegState::Kill);
180 }
166181 }
167182 return true;
168183 }
170185 bool Thumb1InstrInfo::
171186 restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
172187 MachineBasicBlock::iterator MI,
173 const std::vector &CSI) const {
188 const std::vector &CSI,
189 const TargetRegisterInfo *TRI) const {
174190 MachineFunction &MF = *MBB.getParent();
175191 ARMFunctionInfo *AFI = MF.getInfo();
176192 if (CSI.empty())
3838
3939 bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
4040 MachineBasicBlock::iterator MI,
41 const std::vector &CSI) const;
41 const std::vector &CSI,
42 const TargetRegisterInfo *TRI) const;
4243 bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
4344 MachineBasicBlock::iterator MI,
44 const std::vector &CSI) const;
45 const std::vector &CSI,
46 const TargetRegisterInfo *TRI) const;
4547
4648 bool copyRegToReg(MachineBasicBlock &MBB,
4749 MachineBasicBlock::iterator I,
896896
897897 SDValue MSP430TargetLowering::LowerRETURNADDR(SDValue Op,
898898 SelectionDAG &DAG) const {
899 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
900 MFI->setReturnAddressIsTaken(true);
901
899902 unsigned Depth = cast(Op.getOperand(0))->getZExtValue();
900903 DebugLoc dl = Op.getDebugLoc();
901904
919922 SelectionDAG &DAG) const {
920923 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
921924 MFI->setFrameAddressIsTaken(true);
925
922926 EVT VT = Op.getValueType();
923927 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
924928 unsigned Depth = cast(Op.getOperand(0))->getZExtValue();
129129 bool
130130 MSP430InstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
131131 MachineBasicBlock::iterator MI,
132 const std::vector &CSI) const {
132 const std::vector &CSI,
133 const TargetRegisterInfo *TRI) const {
133134 if (CSI.empty())
134135 return false;
135136
153154 bool
154155 MSP430InstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
155156 MachineBasicBlock::iterator MI,
156 const std::vector &CSI) const {
157 const std::vector &CSI,
158 const TargetRegisterInfo *TRI) const {
157159 if (CSI.empty())
158160 return false;
159161
7272
7373 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
7474 MachineBasicBlock::iterator MI,
75 const std::vector &CSI) const;
75 const std::vector &CSI,
76 const TargetRegisterInfo *TRI) const;
7677 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
7778 MachineBasicBlock::iterator MI,
78 const std::vector &CSI) const;
79 const std::vector &CSI,
80 const TargetRegisterInfo *TRI) const;
7981
8082 unsigned GetInstSizeInBytes(const MachineInstr *MI) const;
8183
54955495
54965496 SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op,
54975497 SelectionDAG &DAG) const {
5498 MachineFunction &MF = DAG.getMachineFunction();
5499 MachineFrameInfo *MFI = MF.getFrameInfo();
5500 MFI->setReturnAddressIsTaken(true);
5501
54985502 DebugLoc dl = Op.getDebugLoc();
54995503 unsigned Depth = cast(Op.getOperand(0))->getZExtValue();
55005504
55015505 // Make sure the function does not optimize away the store of the RA to
55025506 // the stack.
5503 MachineFunction &MF = DAG.getMachineFunction();
55045507 PPCFunctionInfo *FuncInfo = MF.getInfo();
55055508 FuncInfo->setLRStoreRequired();
55065509 bool isPPC64 = PPCSubTarget.isPPC64();
269269 bool
270270 SystemZInstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
271271 MachineBasicBlock::iterator MI,
272 const std::vector &CSI) const {
272 const std::vector &CSI,
273 const TargetRegisterInfo *TRI) const {
273274 if (CSI.empty())
274275 return false;
275276
344345 bool
345346 SystemZInstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
346347 MachineBasicBlock::iterator MI,
347 const std::vector &CSI) const {
348 const std::vector &CSI,
349 const TargetRegisterInfo *TRI) const {
348350 if (CSI.empty())
349351 return false;
350352
8585
8686 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
8787 MachineBasicBlock::iterator MI,
88 const std::vector &CSI) const;
88 const std::vector &CSI,
89 const TargetRegisterInfo *TRI) const;
8990 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
9091 MachineBasicBlock::iterator MI,
91 const std::vector &CSI) const;
92 const std::vector &CSI,
93 const TargetRegisterInfo *TRI) const;
9294
9395 bool ReverseBranchCondition(SmallVectorImpl &Cond) const;
9496 virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const;
69806980
69816981 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
69826982 SelectionDAG &DAG) const {
6983 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
6984 MFI->setReturnAddressIsTaken(true);
6985
69836986 unsigned Depth = cast(Op.getOperand(0))->getZExtValue();
69846987 DebugLoc dl = Op.getDebugLoc();
69856988
70037006 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
70047007 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
70057008 MFI->setFrameAddressIsTaken(true);
7009
70067010 EVT VT = Op.getValueType();
70077011 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
70087012 unsigned Depth = cast(Op.getOperand(0))->getZExtValue();
22572257
22582258 bool X86InstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
22592259 MachineBasicBlock::iterator MI,
2260 const std::vector &CSI) const {
2260 const std::vector &CSI,
2261 const TargetRegisterInfo *TRI) const {
22612262 if (CSI.empty())
22622263 return false;
22632264
22962297
22972298 bool X86InstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
22982299 MachineBasicBlock::iterator MI,
2299 const std::vector &CSI) const {
2300 const std::vector &CSI,
2301 const TargetRegisterInfo *TRI) const {
23002302 if (CSI.empty())
23012303 return false;
23022304
619619
620620 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
621621 MachineBasicBlock::iterator MI,
622 const std::vector &CSI) const;
622 const std::vector &CSI,
623 const TargetRegisterInfo *TRI) const;
623624
624625 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
625626 MachineBasicBlock::iterator MI,
626 const std::vector &CSI) const;
627 const std::vector &CSI,
628 const TargetRegisterInfo *TRI) const;
627629
628630 virtual
629631 MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF,
419419
420420 bool XCoreInstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
421421 MachineBasicBlock::iterator MI,
422 const std::vector &CSI) const {
422 const std::vector &CSI,
423 const TargetRegisterInfo *TRI) const {
423424 if (CSI.empty()) {
424425 return true;
425426 }
449450
450451 bool XCoreInstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
451452 MachineBasicBlock::iterator MI,
452 const std::vector &CSI) const
453 const std::vector &CSI,
454 const TargetRegisterInfo *TRI) const
453455 {
454456 bool AtStart = MI == MBB.begin();
455457 MachineBasicBlock::iterator BeforeI = MI;
8383
8484 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
8585 MachineBasicBlock::iterator MI,
86 const std::vector &CSI) const;
86 const std::vector &CSI,
87 const TargetRegisterInfo *TRI) const;
8788
8889 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
8990 MachineBasicBlock::iterator MI,
90 const std::vector &CSI) const;
91 const std::vector &CSI,
92 const TargetRegisterInfo *TRI) const;
9193
9294 virtual bool ReverseBranchCondition(
9395 SmallVectorImpl &Cond) const;
None ; RUN: llc < %s -mtriple=arm-apple-darwin | grep mov | grep r7
1 ; RUN: llc < %s -mtriple=arm-linux-gnueabi | grep mov | grep r11
0 ; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s -check-prefix=DARWIN
1 ; RUN: llc < %s -mtriple=arm-linux-gnueabi | FileCheck %s -check-prefix=LINUX
22 ; PR4344
33 ; PR4416
44
55 define arm_aapcscc i8* @t() nounwind {
66 entry:
7 ; DARWIN: t:
8 ; DARWIN: mov r0, r7
9
10 ; LINUX: t:
11 ; LINUX: mov r0, r11
712 %0 = call i8* @llvm.frameaddress(i32 0)
813 ret i8* %0
914 }
0 ; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s
1 ; rdar://8015977
2
3 define arm_apcscc i8* @rt0(i32 %x) nounwind readnone {
4 entry:
5 ; CHECK: rt0:
6 ; CHECK: mov r0, lr
7 %0 = tail call i8* @llvm.returnaddress(i32 0)
8 ret i8* %0
9 }
10
11 define arm_apcscc i8* @rt2() nounwind readnone {
12 entry:
13 ; CHECK: rt2:
14 ; CHECK: ldr r0, [r7]
15 ; CHECK: ldr r0, [r0]
16 ; CHECK: ldr r0, [r0, #4]
17 %0 = tail call i8* @llvm.returnaddress(i32 2)
18 ret i8* %0
19 }
20
21 declare i8* @llvm.returnaddress(i32) nounwind readnone