llvm.org GIT mirror llvm / 23ef105
PR2598: make sure to expand illegal forms of integer/floating-point conversions for x86, like <2 x i32> -> <2 x float> and <4 x i16> -> <4 x float>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72983 91177308-0d34-0410-b5e6-96231b3b80d8 Eli Friedman 10 years ago
2 changed file(s) with 39 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
549549 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
550550 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
551551 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
552 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand);
553 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand);
554 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
555 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
552556 }
553557
554558 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
733737 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
734738 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
735739
740 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
741 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
742 if (!DisableMMX && Subtarget->hasMMX()) {
743 setOperationAction(ISD::FP_TO_SINT, MVT::v2i32, Custom);
744 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
745 }
736746 }
737747
738748 if (Subtarget->hasSSE41()) {
45574567
45584568 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
45594569 MVT SrcVT = Op.getOperand(0).getValueType();
4570
4571 if (SrcVT.isVector()) {
4572 if (SrcVT == MVT::v2i32 && Op.getValueType() == MVT::v2f64) {
4573 return Op;
4574 }
4575 return SDValue();
4576 }
4577
45604578 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
45614579 "Unknown SINT_TO_FP to lower!");
45624580
48484866 }
48494867
48504868 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) {
4869 if (Op.getValueType().isVector()) {
4870 if (Op.getValueType() == MVT::v2i32 &&
4871 Op.getOperand(0).getValueType() == MVT::v2f64) {
4872 return Op;
4873 }
4874 return SDValue();
4875 }
4876
48514877 std::pair Vals = FP_TO_INTHelper(Op, DAG, true);
48524878 SDValue FIST = Vals.first, StackSlot = Vals.second;
48534879 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
0 ; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse
1 ; PR2598
2
3 define <2 x float> @a(<2 x i32> %i) nounwind {
4 %r = sitofp <2 x i32> %i to <2 x float>
5 ret <2 x float> %r
6 }
7
8 define <2 x i32> @b(<2 x float> %i) nounwind {
9 %r = fptosi <2 x float> %i to <2 x i32>
10 ret <2 x i32> %r
11 }
12