llvm.org GIT mirror llvm / 23ce502
Remove the code from CodeGenPrepare that moved getresult instructions to the block that defines their operands. This doesn't work in the case that the operand is an invoke, because invoke is a terminator and must be the last instruction in a block. Replace it with support in SelectionDAGISel for copying struct values into sequences of virtual registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50279 91177308-0d34-0410-b5e6-96231b3b80d8 Dan Gohman 12 years ago
3 changed file(s) with 182 addition(s) and 100 deletion(s). Raw diff Collapse all Expand all
8989 namespace { struct SDISelAsmOperandInfo; }
9090
9191 namespace {
92 /// ComputeValueVTs - Given an LLVM IR type, compute a sequence of
93 /// MVT::ValueTypes that represent all the individual underlying
94 /// non-aggregate types that comprise it.
95 static void ComputeValueVTs(const TargetLowering &TLI,
96 const Type *Ty,
97 SmallVectorImpl &ValueVTs) {
98 // Given a struct type, recursively traverse the elements.
99 if (const StructType *STy = dyn_cast(Ty)) {
100 for (StructType::element_iterator EI = STy->element_begin(),
101 EB = STy->element_end();
102 EI != EB; ++EI)
103 ComputeValueVTs(TLI, *EI, ValueVTs);
104 return;
105 }
106 // Given an array type, recursively traverse the elements.
107 if (const ArrayType *ATy = dyn_cast(Ty)) {
108 const Type *EltTy = ATy->getElementType();
109 for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i)
110 ComputeValueVTs(TLI, EltTy, ValueVTs);
111 return;
112 }
113 // Base case: we can get an MVT::ValueType for this LLVM IR type.
114 MVT::ValueType VT = TLI.getValueType(Ty);
115 ValueVTs.push_back(VT);
116 }
117
92118 /// RegsForValue - This struct represents the physical registers that a
93119 /// particular value is assigned and the type information about the value.
94120 /// This is needed because values can be promoted into larger registers and
95121 /// expanded into multiple smaller registers than the value.
96122 struct VISIBILITY_HIDDEN RegsForValue {
123 /// TLI - The TargetLowering object.
124 const TargetLowering *TLI;
125
97126 /// Regs - This list holds the register (for legal and promoted values)
98127 /// or register set (for expanded values) that the value should be assigned
99128 /// to.
100129 std::vector Regs;
101130
102 /// RegVT - The value type of each register.
131 /// RegVTs - The value types of the registers. This is the same size
132 /// as ValueVTs; every register contributing to a given value must
133 /// have the same type. When Regs contains all virtual registers, the
134 /// contents of RegVTs is redundant with TLI's getRegisterType member
135 /// function, however when Regs contains physical registers, it is
136 /// necessary to have a separate record of the types.
103137 ///
104 MVT::ValueType RegVT;
105
106 /// ValueVT - The value type of the LLVM value, which may be promoted from
107 /// RegVT or made from merging the two expanded parts.
108 MVT::ValueType ValueVT;
109
110 RegsForValue() : RegVT(MVT::Other), ValueVT(MVT::Other) {}
111
112 RegsForValue(unsigned Reg, MVT::ValueType regvt, MVT::ValueType valuevt)
113 : RegVT(regvt), ValueVT(valuevt) {
114 Regs.push_back(Reg);
115 }
116 RegsForValue(const std::vector ®s,
138 SmallVector RegVTs;
139
140 /// ValueVTs - The value types of the values, which may be promoted
141 /// or synthesized from one or more registers.
142 SmallVector ValueVTs;
143
144 RegsForValue() : TLI(0) {}
145
146 RegsForValue(const TargetLowering &tli,
147 unsigned Reg, MVT::ValueType regvt, MVT::ValueType valuevt)
148 : TLI(&tli), Regs(1, Reg), RegVTs(1, regvt), ValueVTs(1, valuevt) {}
149 RegsForValue(const TargetLowering &tli,
150 const std::vector ®s,
117151 MVT::ValueType regvt, MVT::ValueType valuevt)
118 : Regs(regs), RegVT(regvt), ValueVT(valuevt) {
152 : TLI(&tli), Regs(regs), RegVTs(1, regvt), ValueVTs(1, valuevt) {}
153 RegsForValue(const TargetLowering &tli,
154 const std::vector ®s,
155 const SmallVector ®vts,
156 const SmallVector &valuevts)
157 : TLI(&tli), Regs(regs), RegVTs(regvts), ValueVTs(valuevts) {}
158 RegsForValue(const TargetLowering &tli,
159 unsigned Reg, const Type *Ty) : TLI(&tli) {
160 ComputeValueVTs(tli, Ty, ValueVTs);
161
162 for (unsigned Value = 0; Value != ValueVTs.size(); ++Value) {
163 MVT::ValueType ValueVT = ValueVTs[Value];
164 unsigned NumRegs = TLI->getNumRegisters(ValueVT);
165 MVT::ValueType RegisterVT = TLI->getRegisterType(ValueVT);
166 for (unsigned i = 0; i != NumRegs; ++i)
167 Regs.push_back(Reg + i);
168 RegVTs.push_back(RegisterVT);
169 Reg += NumRegs;
170 }
119171 }
120172
121173 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
122 /// this value and returns the result as a ValueVT value. This uses
174 /// this value and returns the result as a ValueVTs value. This uses
123175 /// Chain/Flag as the input and updates them for the output Chain/Flag.
124176 /// If the Flag pointer is NULL, no flag is used.
125177 SDOperand getCopyFromRegs(SelectionDAG &DAG,
309361 /// the correctly promoted or expanded types. Assign these registers
310362 /// consecutive vreg numbers and return the first assigned number.
311363 unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
312 MVT::ValueType VT = TLI.getValueType(V->getType());
313
314 unsigned NumRegisters = TLI.getNumRegisters(VT);
315 MVT::ValueType RegisterVT = TLI.getRegisterType(VT);
316
317 unsigned R = MakeReg(RegisterVT);
318 for (unsigned i = 1; i != NumRegisters; ++i)
319 MakeReg(RegisterVT);
320
321 return R;
364 const Type *Ty = V->getType();
365 SmallVector ValueVTs;
366 ComputeValueVTs(TLI, Ty, ValueVTs);
367
368 unsigned FirstReg = 0;
369 for (unsigned Value = 0; Value != ValueVTs.size(); ++Value) {
370 MVT::ValueType ValueVT = ValueVTs[Value];
371 unsigned NumRegs = TLI.getNumRegisters(ValueVT);
372 MVT::ValueType RegisterVT = TLI.getRegisterType(ValueVT);
373
374 for (unsigned i = 0; i != NumRegs; ++i) {
375 unsigned R = MakeReg(RegisterVT);
376 if (!FirstReg) FirstReg = R;
377 }
378 }
379 return FirstReg;
322380 }
323381
324382 //===----------------------------------------------------------------------===//
9851043 if (N.Val) return N;
9861044
9871045 const Type *VTy = V->getType();
988 MVT::ValueType VT = TLI.getValueType(VTy);
1046 MVT::ValueType VT = TLI.getValueType(VTy, true);
9891047 if (Constant *C = const_cast(dyn_cast(V))) {
9901048 if (ConstantExpr *CE = dyn_cast(C)) {
9911049 visit(CE->getOpcode(), *CE);
10551113 unsigned InReg = FuncInfo.ValueMap[V];
10561114 assert(InReg && "Value not in map!");
10571115
1058 MVT::ValueType RegisterVT = TLI.getRegisterType(VT);
1059 unsigned NumRegs = TLI.getNumRegisters(VT);
1060
1061 std::vector Regs(NumRegs);
1062 for (unsigned i = 0; i != NumRegs; ++i)
1063 Regs[i] = InReg + i;
1064
1065 RegsForValue RFV(Regs, RegisterVT, VT);
1116 RegsForValue RFV(TLI, InReg, VTy);
10661117 SDOperand Chain = DAG.getEntryNode();
10671118
10681119 return RFV.getCopyFromRegs(DAG, Chain, NULL);
33153366 setValue(&I, Undef);
33163367 } else {
33173368 SDOperand Call = getValue(I.getOperand(0));
3369
3370 // To add support for individual return values with aggregate types,
3371 // we'd need a way to take a getresult index and determine which
3372 // values of the Call SDNode are associated with it.
3373 assert(TLI.getValueType(I.getType(), true) != MVT::Other &&
3374 "Individual return values must not be aggregates!");
3375
33183376 setValue(&I, SDOperand(Call.Val, I.getIndex()));
33193377 }
33203378 }
33263384 /// If the Flag pointer is NULL, no flag is used.
33273385 SDOperand RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
33283386 SDOperand &Chain, SDOperand *Flag)const{
3329 // Copy the legal parts from the registers.
3330 unsigned NumParts = Regs.size();
3331 SmallVector Parts(NumParts);
3332 for (unsigned i = 0; i != NumParts; ++i) {
3333 SDOperand Part = Flag ?
3334 DAG.getCopyFromReg(Chain, Regs[i], RegVT, *Flag) :
3335 DAG.getCopyFromReg(Chain, Regs[i], RegVT);
3336 Chain = Part.getValue(1);
3337 if (Flag)
3338 *Flag = Part.getValue(2);
3339 Parts[i] = Part;
3340 }
3341
3342 // Assemble the legal parts into the final value.
3343 return getCopyFromParts(DAG, &Parts[0], NumParts, RegVT, ValueVT);
3387 // Assemble the legal parts into the final values.
3388 SmallVector Values(ValueVTs.size());
3389 for (unsigned Value = 0, Part = 0; Value != ValueVTs.size(); ++Value) {
3390 // Copy the legal parts from the registers.
3391 MVT::ValueType ValueVT = ValueVTs[Value];
3392 unsigned NumRegs = TLI->getNumRegisters(ValueVT);
3393 MVT::ValueType RegisterVT = RegVTs[Value];
3394
3395 SmallVector Parts(NumRegs);
3396 for (unsigned i = 0; i != NumRegs; ++i) {
3397 SDOperand P = Flag ?
3398 DAG.getCopyFromReg(Chain, Regs[Part+i], RegisterVT, *Flag) :
3399 DAG.getCopyFromReg(Chain, Regs[Part+i], RegisterVT);
3400 Chain = P.getValue(1);
3401 if (Flag)
3402 *Flag = P.getValue(2);
3403 Parts[Part+i] = P;
3404 }
3405
3406 Values[Value] = getCopyFromParts(DAG, &Parts[Part], NumRegs, RegisterVT,
3407 ValueVT);
3408 Part += NumRegs;
3409 }
3410 return DAG.getNode(ISD::MERGE_VALUES,
3411 DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
3412 &Values[0], ValueVTs.size());
33443413 }
33453414
33463415 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
33503419 void RegsForValue::getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
33513420 SDOperand &Chain, SDOperand *Flag) const {
33523421 // Get the list of the values's legal parts.
3353 unsigned NumParts = Regs.size();
3354 SmallVector Parts(NumParts);
3355 getCopyToParts(DAG, Val, &Parts[0], NumParts, RegVT);
3422 unsigned NumRegs = Regs.size();
3423 SmallVector Parts(NumRegs);
3424 for (unsigned Value = 0, Part = 0; Value != ValueVTs.size(); ++Value) {
3425 MVT::ValueType ValueVT = ValueVTs[Value];
3426 unsigned NumParts = TLI->getNumRegisters(ValueVT);
3427 MVT::ValueType RegisterVT = RegVTs[Value];
3428
3429 getCopyToParts(DAG, Val.getValue(Val.ResNo + Value),
3430 &Parts[Part], NumParts, RegisterVT);
3431 Part += NumParts;
3432 }
33563433
33573434 // Copy the parts into the registers.
3358 for (unsigned i = 0; i != NumParts; ++i) {
3435 SmallVector Chains(NumRegs);
3436 for (unsigned i = 0; i != NumRegs; ++i) {
33593437 SDOperand Part = Flag ?
33603438 DAG.getCopyToReg(Chain, Regs[i], Parts[i], *Flag) :
33613439 DAG.getCopyToReg(Chain, Regs[i], Parts[i]);
3362 Chain = Part.getValue(0);
3440 Chains[i] = Part.getValue(0);
33633441 if (Flag)
33643442 *Flag = Part.getValue(1);
33653443 }
3444 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Chains[0], NumRegs);
33663445 }
33673446
33683447 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
33723451 std::vector &Ops) const {
33733452 MVT::ValueType IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
33743453 Ops.push_back(DAG.getTargetConstant(Code | (Regs.size() << 3), IntPtrTy));
3375 for (unsigned i = 0, e = Regs.size(); i != e; ++i)
3376 Ops.push_back(DAG.getRegister(Regs[i], RegVT));
3454 for (unsigned Value = 0, Reg = 0; Value != ValueVTs.size(); ++Value) {
3455 MVT::ValueType ValueVT = ValueVTs[Value];
3456 unsigned NumRegs = TLI->getNumRegisters(ValueVT);
3457 MVT::ValueType RegisterVT = RegVTs[Value];
3458 for (unsigned i = 0; i != NumRegs; ++i) {
3459 SDOperand RegOp = DAG.getRegister(Regs[Reg+i], RegisterVT);
3460 Ops.push_back(RegOp);
3461 }
3462 Reg += NumRegs;
3463 }
33773464 }
33783465
33793466 /// isAllocatableRegister - If the specified register is safe to allocate,
34393526 /// contains the set of register corresponding to the operand.
34403527 RegsForValue AssignedRegs;
34413528
3442 SDISelAsmOperandInfo(const InlineAsm::ConstraintInfo &info)
3529 explicit SDISelAsmOperandInfo(const InlineAsm::ConstraintInfo &info)
34433530 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) {
34443531 }
34453532
35573644 Regs.push_back(*I);
35583645 }
35593646 }
3560 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
3647 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
35613648 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
35623649 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
35633650 return;
35863673 for (; NumRegs; --NumRegs)
35873674 Regs.push_back(RegInfo.createVirtualRegister(PhysReg.second));
35883675
3589 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
3676 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
35903677 return;
35913678 }
35923679
36363723 for (unsigned i = RegStart; i != RegEnd; ++i)
36373724 Regs.push_back(RegClassRegs[i]);
36383725
3639 OpInfo.AssignedRegs = RegsForValue(Regs, *RC->vt_begin(),
3726 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, *RC->vt_begin(),
36403727 OpInfo.ConstraintVT);
36413728 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
36423729 return;
38973984 if ((NumOps & 7) == 2 /*REGDEF*/) {
38983985 // Add NumOps>>3 registers to MatchedRegs.
38993986 RegsForValue MatchedRegs;
3900 MatchedRegs.ValueVT = InOperandVal.getValueType();
3901 MatchedRegs.RegVT = AsmNodeOperands[CurOp+1].getValueType();
3987 MatchedRegs.TLI = &TLI;
3988 MatchedRegs.ValueVTs.resize(1, InOperandVal.getValueType());
3989 MatchedRegs.RegVTs.resize(1, AsmNodeOperands[CurOp+1].getValueType());
39023990 for (unsigned i = 0, e = NumOps>>3; i != e; ++i) {
39033991 unsigned Reg =
39043992 cast(AsmNodeOperands[++CurOp])->getReg();
43034391 }
43044392
43054393 // Figure out the result value types. We start by making a list of
4306 // the high-level LLVM return types.
4307 SmallVector LLVMRetTys;
4308 if (const StructType *ST = dyn_cast(RetTy))
4309 // A struct return type in the LLVM IR means we have multiple return values.
4310 LLVMRetTys.insert(LLVMRetTys.end(), ST->element_begin(), ST->element_end());
4311 else
4312 LLVMRetTys.push_back(RetTy);
4313
4314 // Then we translate that to a list of lowered codegen result types.
4394 // the potentially illegal return value types.
43154395 SmallVector LoweredRetTys;
43164396 SmallVector RetTys;
4317 for (unsigned I = 0, E = LLVMRetTys.size(); I != E; ++I) {
4318 MVT::ValueType VT = getValueType(LLVMRetTys[I]);
4319 RetTys.push_back(VT);
4320
4397 ComputeValueVTs(*this, RetTy, RetTys);
4398
4399 // Then we translate that to a list of legal types.
4400 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
4401 MVT::ValueType VT = RetTys[I];
43214402 MVT::ValueType RegisterVT = getRegisterType(VT);
43224403 unsigned NumRegs = getNumRegisters(VT);
43234404 for (unsigned i = 0; i != NumRegs; ++i)
43444425
43454426 SmallVector ReturnValues;
43464427 unsigned RegNo = 0;
4347 for (unsigned I = 0, E = LLVMRetTys.size(); I != E; ++I) {
4348 MVT::ValueType VT = getValueType(LLVMRetTys[I]);
4428 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
4429 MVT::ValueType VT = RetTys[I];
43494430 MVT::ValueType RegisterVT = getRegisterType(VT);
43504431 unsigned NumRegs = getNumRegisters(VT);
43514432 unsigned RegNoEnd = NumRegs + RegNo;
44404521 cast(Op.getOperand(1))->getReg() != Reg) &&
44414522 "Copy from a reg to the same reg!");
44424523 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
4443
4444 MVT::ValueType SrcVT = Op.getValueType();
4445 MVT::ValueType RegisterVT = TLI.getRegisterType(SrcVT);
4446 unsigned NumRegs = TLI.getNumRegisters(SrcVT);
4447 SmallVector Regs(NumRegs);
4448 SmallVector Chains(NumRegs);
4449
4450 // Copy the value by legal parts into sequential virtual registers.
4451 getCopyToParts(DAG, Op, &Regs[0], NumRegs, RegisterVT);
4452 for (unsigned i = 0; i != NumRegs; ++i)
4453 Chains[i] = DAG.getCopyToReg(DAG.getEntryNode(), Reg + i, Regs[i]);
4454 SDOperand Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, &Chains[0], NumRegs);
4455 PendingExports.push_back(Ch);
4524
4525 RegsForValue RFV(TLI, Reg, V->getType());
4526 SDOperand Chain = DAG.getEntryNode();
4527 RFV.getCopyToRegs(Op, DAG, Chain, 0);
4528 PendingExports.push_back(Chain);
44564529 }
44574530
44584531 void SelectionDAGISel::
11261126 // Sink address computing for memory operands into the block.
11271127 MadeChange |= OptimizeInlineAsmInst(I, &(*CI), SunkAddrs);
11281128 }
1129 } else if (GetResultInst *GRI = dyn_cast(I)) {
1130 // Ensure that all getresult instructions live in the same basic block
1131 // as their associated struct-value instructions. Codegen requires
1132 // this, as lowering only works on one basic block at a time.
1133 if (Instruction *Agg = dyn_cast(GRI->getAggregateValue())) {
1134 BasicBlock *AggBB = Agg->getParent();
1135 if (AggBB != GRI->getParent())
1136 GRI->moveBefore(AggBB->getTerminator());
1137 }
11381129 }
11391130 }
11401131
0 ; RUN: llvm-as < %s | llc
1
2 declare { i64, double } @wild()
3
4 define void @foo(i64* %p, double* %q) nounwind {
5 %t = invoke { i64, double } @wild() to label %normal unwind label %handler
6
7 normal:
8 %mrv_gr = getresult { i64, double } %t, 0
9 store i64 %mrv_gr, i64* %p
10 %mrv_gr12681 = getresult { i64, double } %t, 1
11 store double %mrv_gr12681, double* %q
12 ret void
13
14 handler:
15 ret void
16 }
17