llvm.org GIT mirror llvm / 23b9b19
Add contexts to some of the MVT APIs. No functionality change yet, just the infrastructure work needed to get the contexts to where they need to be first. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78759 91177308-0d34-0410-b5e6-96231b3b80d8 Owen Anderson 10 years ago
24 changed file(s) with 435 addition(s) and 356 deletion(s). Raw diff Collapse all Expand all
141141 bool isVector() const {
142142 return (SimpleTy >= MVT::FIRST_VECTOR_VALUETYPE &&
143143 SimpleTy <= MVT::LAST_VECTOR_VALUETYPE);
144 }
145
146 /// isPow2VectorType - Retuns true if the given vector is a power of 2.
147 bool isPow2VectorType() const {
148 unsigned NElts = getVectorNumElements();
149 return !(NElts & (NElts - 1));
150 }
151
152 /// getPow2VectorType - Widens the length of the given vector EVT up to
153 /// the nearest power of 2 and returns that type.
154 MVT getPow2VectorType() const {
155 if (!isPow2VectorType()) {
156 unsigned NElts = getVectorNumElements();
157 unsigned Pow2NElts = 1 << Log2_32_Ceil(NElts);
158 return MVT::getVectorVT(getVectorElementType(), Pow2NElts);
159 }
160 else {
161 return *this;
162 }
144163 }
145164
146165 MVT getVectorElementType() const {
363382
364383 /// getIntegerVT - Returns the EVT that represents an integer with the given
365384 /// number of bits.
366 static EVT getIntegerVT(unsigned BitWidth) {
385 static EVT getIntegerVT(LLVMContext &Context, unsigned BitWidth) {
367386 MVT M = MVT::getIntegerVT(BitWidth);
368387 if (M.SimpleTy == MVT::LastSimpleValueType+1)
369 return getExtendedIntegerVT(BitWidth);
388 return getExtendedIntegerVT(Context, BitWidth);
370389 else
371390 return M;
372391 }
373392
374393 /// getVectorVT - Returns the EVT that represents a vector NumElements in
375394 /// length, where each element is of type VT.
376 static EVT getVectorVT(EVT VT, unsigned NumElements) {
395 static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements) {
377396 MVT M = MVT::getVectorVT(VT.V, NumElements);
378397 if (M.SimpleTy == MVT::LastSimpleValueType+1)
379 return getExtendedVectorVT(VT, NumElements);
398 return getExtendedVectorVT(Context, VT, NumElements);
380399 else
381400 return M;
382401 }
383402
384403 /// getIntVectorWithNumElements - Return any integer vector type that has
385404 /// the specified number of elements.
386 static EVT getIntVectorWithNumElements(unsigned NumElts) {
405 static EVT getIntVectorWithNumElements(LLVMContext &C, unsigned NumElts) {
387406 MVT M = MVT::getIntVectorWithNumElements(NumElts);
388407 if (M.SimpleTy == MVT::LastSimpleValueType+1)
389 return getVectorVT(EVT(MVT::i8), NumElts);
408 return getVectorVT(C, MVT::i8, NumElts);
390409 else
391410 return M;
392411 }
536555 /// getRoundIntegerType - Rounds the bit-width of the given integer EVT up
537556 /// to the nearest power of two (and at least to eight), and returns the
538557 /// integer EVT with that number of bits.
539 EVT getRoundIntegerType() const {
558 EVT getRoundIntegerType(LLVMContext &Context) const {
540559 assert(isInteger() && !isVector() && "Invalid integer type!");
541560 unsigned BitWidth = getSizeInBits();
542561 if (BitWidth <= 8)
543562 return EVT(MVT::i8);
544563 else
545 return getIntegerVT(1 << Log2_32_Ceil(BitWidth));
564 return getIntegerVT(Context, 1 << Log2_32_Ceil(BitWidth));
546565 }
547566
548567 /// isPow2VectorType - Retuns true if the given vector is a power of 2.
553572
554573 /// getPow2VectorType - Widens the length of the given vector EVT up to
555574 /// the nearest power of 2 and returns that type.
556 EVT getPow2VectorType() const {
575 EVT getPow2VectorType(LLVMContext &Context) const {
557576 if (!isPow2VectorType()) {
558577 unsigned NElts = getVectorNumElements();
559578 unsigned Pow2NElts = 1 << Log2_32_Ceil(NElts);
560 return EVT::getVectorVT(getVectorElementType(), Pow2NElts);
579 return EVT::getVectorVT(Context, getVectorElementType(), Pow2NElts);
561580 }
562581 else {
563582 return *this;
571590 /// getTypeForEVT - This method returns an LLVM type corresponding to the
572591 /// specified EVT. For integer types, this returns an unsigned type. Note
573592 /// that this will abort for types that cannot be represented.
574 const Type *getTypeForEVT() const;
593 const Type *getTypeForEVT(LLVMContext &Context) const;
575594
576595 /// getEVT - Return the value type corresponding to the specified type.
577596 /// This returns all pointers as iPTR. If HandleUnknown is true, unknown
600619 // Methods for handling the Extended-type case in functions above.
601620 // These are all out-of-line to prevent users of this header file
602621 // from having a dependency on Type.h.
603 static EVT getExtendedIntegerVT(unsigned BitWidth);
604 static EVT getExtendedVectorVT(EVT VT, unsigned NumElements);
622 static EVT getExtendedIntegerVT(LLVMContext &C, unsigned BitWidth);
623 static EVT getExtendedVectorVT(LLVMContext &C, EVT VT,
624 unsigned NumElements);
605625 bool isExtendedFloatingPoint() const;
606626 bool isExtendedInteger() const;
607627 bool isExtendedVector() const;
185185 ValueTypeActions[3] = RHS.ValueTypeActions[3];
186186 }
187187
188 LegalizeAction getTypeAction(EVT VT) const {
188 LegalizeAction getTypeAction(LLVMContext &Context, EVT VT) const {
189189 if (VT.isExtended()) {
190190 if (VT.isVector()) {
191191 return VT.isPow2VectorType() ? Expand : Promote;
192192 }
193193 if (VT.isInteger())
194194 // First promote to a power-of-two size, then expand if necessary.
195 return VT == VT.getRoundIntegerType() ? Expand : Promote;
195 return VT == VT.getRoundIntegerType(Context) ? Expand : Promote;
196196 assert(0 && "Unsupported extended type!");
197197 return Legal;
198198 }
215215 /// it is already legal (return 'Legal') or we need to promote it to a larger
216216 /// type (return 'Promote'), or we need to expand it into multiple registers
217217 /// of smaller integer type (return 'Expand'). 'Custom' is not an option.
218 LegalizeAction getTypeAction(EVT VT) const {
219 return ValueTypeActions.getTypeAction(VT);
218 LegalizeAction getTypeAction(LLVMContext &Context, EVT VT) const {
219 return ValueTypeActions.getTypeAction(Context, VT);
220220 }
221221
222222 /// getTypeToTransformTo - For types supported by the target, this is an
225225 /// than the largest integer register, this contains one step in the expansion
226226 /// to get to the smaller register. For illegal floating point types, this
227227 /// returns the integer type to transform to.
228 EVT getTypeToTransformTo(EVT VT) const {
228 EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const {
229229 if (VT.isSimple()) {
230230 assert((unsigned)VT.getSimpleVT().SimpleTy <
231231 array_lengthof(TransformToType));
232232 EVT NVT = TransformToType[VT.getSimpleVT().SimpleTy];
233 assert(getTypeAction(NVT) != Promote &&
233 assert(getTypeAction(Context, NVT) != Promote &&
234234 "Promote may not follow Expand or Promote");
235235 return NVT;
236236 }
237237
238238 if (VT.isVector()) {
239 EVT NVT = VT.getPow2VectorType();
239 EVT NVT = VT.getPow2VectorType(Context);
240240 if (NVT == VT) {
241241 // Vector length is a power of 2 - split to half the size.
242242 unsigned NumElts = VT.getVectorNumElements();
243243 EVT EltVT = VT.getVectorElementType();
244 return (NumElts == 1) ? EltVT : EVT::getVectorVT(EltVT, NumElts / 2);
244 return (NumElts == 1) ?
245 EltVT : EVT::getVectorVT(Context, EltVT, NumElts / 2);
245246 }
246247 // Promote to a power of two size, avoiding multi-step promotion.
247 return getTypeAction(NVT) == Promote ? getTypeToTransformTo(NVT) : NVT;
248 return getTypeAction(Context, NVT) == Promote ?
249 getTypeToTransformTo(Context, NVT) : NVT;
248250 } else if (VT.isInteger()) {
249 EVT NVT = VT.getRoundIntegerType();
251 EVT NVT = VT.getRoundIntegerType(Context);
250252 if (NVT == VT)
251253 // Size is a power of two - expand to half the size.
252 return EVT::getIntegerVT(VT.getSizeInBits() / 2);
254 return EVT::getIntegerVT(Context, VT.getSizeInBits() / 2);
253255 else
254256 // Promote to a power of two size, avoiding multi-step promotion.
255 return getTypeAction(NVT) == Promote ? getTypeToTransformTo(NVT) : NVT;
257 return getTypeAction(Context, NVT) == Promote ?
258 getTypeToTransformTo(Context, NVT) : NVT;
256259 }
257260 assert(0 && "Unsupported extended type!");
258261 return MVT(MVT::Other); // Not reached
262265 /// identity function. For types that must be expanded (i.e. integer types
263266 /// that are larger than the largest integer register or illegal floating
264267 /// point types), this returns the largest legal type it will be expanded to.
265 EVT getTypeToExpandTo(EVT VT) const {
268 EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const {
266269 assert(!VT.isVector());
267270 while (true) {
268 switch (getTypeAction(VT)) {
271 switch (getTypeAction(Context, VT)) {
269272 case Legal:
270273 return VT;
271274 case Expand:
272 VT = getTypeToTransformTo(VT);
275 VT = getTypeToTransformTo(Context, VT);
273276 break;
274277 default:
275278 assert(false && "Type is not legal nor is it to be expanded!");
288291 /// register. It also returns the VT and quantity of the intermediate values
289292 /// before they are promoted/expanded.
290293 ///
291 unsigned getVectorTypeBreakdown(EVT VT,
294 unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
292295 EVT &IntermediateVT,
293296 unsigned &NumIntermediates,
294297 EVT &RegisterVT) const;
548551
549552 /// getRegisterType - Return the type of registers that this ValueType will
550553 /// eventually require.
551 EVT getRegisterType(EVT VT) const {
554 EVT getRegisterType(MVT VT) const {
555 assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT));
556 return RegisterTypeForVT[VT.SimpleTy];
557 }
558
559 /// getRegisterType - Return the type of registers that this ValueType will
560 /// eventually require.
561 EVT getRegisterType(LLVMContext &Context, EVT VT) const {
552562 if (VT.isSimple()) {
553563 assert((unsigned)VT.getSimpleVT().SimpleTy <
554564 array_lengthof(RegisterTypeForVT));
557567 if (VT.isVector()) {
558568 EVT VT1, RegisterVT;
559569 unsigned NumIntermediates;
560 (void)getVectorTypeBreakdown(VT, VT1, NumIntermediates, RegisterVT);
570 (void)getVectorTypeBreakdown(Context, VT, VT1,
571 NumIntermediates, RegisterVT);
561572 return RegisterVT;
562573 }
563574 if (VT.isInteger()) {
564 return getRegisterType(getTypeToTransformTo(VT));
575 return getRegisterType(Context, getTypeToTransformTo(Context, VT));
565576 }
566577 assert(0 && "Unsupported extended type!");
567578 return EVT(MVT::Other); // Not reached
573584 /// into pieces. For types like i140, which are first promoted then expanded,
574585 /// it is the number of registers needed to hold all the bits of the original
575586 /// type. For an i140 on a 32 bit machine this means 5 registers.
576 unsigned getNumRegisters(EVT VT) const {
587 unsigned getNumRegisters(LLVMContext &Context, EVT VT) const {
577588 if (VT.isSimple()) {
578589 assert((unsigned)VT.getSimpleVT().SimpleTy <
579590 array_lengthof(NumRegistersForVT));
582593 if (VT.isVector()) {
583594 EVT VT1, VT2;
584595 unsigned NumIntermediates;
585 return getVectorTypeBreakdown(VT, VT1, NumIntermediates, VT2);
596 return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2);
586597 }
587598 if (VT.isInteger()) {
588599 unsigned BitWidth = VT.getSizeInBits();
589 unsigned RegWidth = getRegisterType(VT).getSizeInBits();
600 unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits();
590601 return (BitWidth + RegWidth - 1) / RegWidth;
591602 }
592603 assert(0 && "Unsupported extended type!");
18801880 EVT ExtVT = MVT::Other;
18811881 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits();
18821882 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue()))
1883 ExtVT = EVT::getIntegerVT(ActiveBits);
1883 ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits);
18841884
18851885 EVT LoadedVT = LN0->getMemoryVT();
18861886
25382538 // sext_inreg.
25392539 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
25402540 unsigned LowBits = VT.getSizeInBits() - (unsigned)N1C->getZExtValue();
2541 EVT EVT = EVT::getIntegerVT(LowBits);
2541 EVT EVT = EVT::getIntegerVT(*DAG.getContext(), LowBits);
25422542 if ((!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT)))
25432543 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT,
25442544 N0.getOperand(0), DAG.getValueType(EVT));
25662566 // Determine what the truncate's result bitsize and type would be.
25672567 unsigned VTValSize = VT.getSizeInBits();
25682568 EVT TruncVT =
2569 EVT::getIntegerVT(VTValSize - N1C->getZExtValue());
2569 EVT::getIntegerVT(*DAG.getContext(), VTValSize - N1C->getZExtValue());
25702570 // Determine the residual right-shift amount.
25712571 signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue();
25722572
36833683 TLI.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1, MFI)) {
36843684 unsigned Align = LD1->getAlignment();
36853685 unsigned NewAlign = TLI.getTargetData()->
3686 getABITypeAlignment(VT.getTypeForEVT());
3686 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
36873687
36883688 if (NewAlign <= Align &&
36893689 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT)))
37523752 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) {
37533753 LoadSDNode *LN0 = cast(N0);
37543754 unsigned Align = TLI.getTargetData()->
3755 getABITypeAlignment(VT.getTypeForEVT());
3755 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
37563756 unsigned OrigAlign = LN0->getAlignment();
37573757
37583758 if (Align <= OrigAlign) {
37953795 isa(N0.getOperand(0)) &&
37963796 VT.isInteger() && !VT.isVector()) {
37973797 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits();
3798 EVT IntXVT = EVT::getIntegerVT(OrigXWidth);
3798 EVT IntXVT = EVT::getIntegerVT(*DAG.getContext(), OrigXWidth);
37993799 if (TLI.isTypeLegal(IntXVT) || !LegalTypes) {
38003800 SDValue X = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(),
38013801 IntXVT, N0.getOperand(1));
38743874 DstEltVT, Op));
38753875 AddToWorkList(Ops.back().getNode());
38763876 }
3877 EVT VT = EVT::getVectorVT(DstEltVT,
3877 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT,
38783878 BV->getValueType(0).getVectorNumElements());
38793879 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
38803880 &Ops[0], Ops.size());
38873887 // Convert the input float vector to a int vector where the elements are the
38883888 // same sizes.
38893889 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!");
3890 EVT IntVT = EVT::getIntegerVT(SrcEltVT.getSizeInBits());
3890 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), SrcEltVT.getSizeInBits());
38913891 BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).getNode();
38923892 SrcEltVT = IntVT;
38933893 }
38963896 // convert to integer first, then to FP of the right size.
38973897 if (DstEltVT.isFloatingPoint()) {
38983898 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!");
3899 EVT TmpVT = EVT::getIntegerVT(DstEltVT.getSizeInBits());
3899 EVT TmpVT = EVT::getIntegerVT(*DAG.getContext(), DstEltVT.getSizeInBits());
39003900 SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).getNode();
39013901
39023902 // Next, convert to FP elements of the same size.
39323932 Ops.push_back(DAG.getConstant(NewBits, DstEltVT));
39333933 }
39343934
3935 EVT VT = EVT::getVectorVT(DstEltVT, Ops.size());
3935 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, Ops.size());
39363936 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
39373937 &Ops[0], Ops.size());
39383938 }
39413941 // turns into multiple outputs.
39423942 bool isS2V = ISD::isScalarToVector(BV);
39433943 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize;
3944 EVT VT = EVT::getVectorVT(DstEltVT, NumOutputsPerInput*BV->getNumOperands());
3944 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT,
3945 NumOutputsPerInput*BV->getNumOperands());
39453946 SmallVector Ops;
39463947
39473948 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
49964997 unsigned ShAmt = Imm.countTrailingZeros();
49974998 unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1;
49984999 unsigned NewBW = NextPowerOf2(MSB - ShAmt);
4999 EVT NewVT = EVT::getIntegerVT(NewBW);
5000 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW);
50005001 while (NewBW < BitWidth &&
50015002 !(TLI.isOperationLegalOrCustom(Opc, NewVT) &&
50025003 TLI.isNarrowingProfitable(VT, NewVT))) {
50035004 NewBW = NextPowerOf2(NewBW);
5004 NewVT = EVT::getIntegerVT(NewBW);
5005 NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW);
50055006 }
50065007 if (NewBW >= BitWidth)
50075008 return SDValue();
50235024
50245025 unsigned NewAlign = MinAlign(LD->getAlignment(), PtrOff);
50255026 if (NewAlign <
5026 TLI.getTargetData()->getABITypeAlignment(NewVT.getTypeForEVT()))
5027 TLI.getTargetData()->getABITypeAlignment(NewVT.getTypeForEVT(*DAG.getContext())))
50275028 return SDValue();
50285029
50295030 SDValue NewPtr = DAG.getNode(ISD::ADD, LD->getDebugLoc(),
50785079 unsigned OrigAlign = ST->getAlignment();
50795080 EVT SVT = Value.getOperand(0).getValueType();
50805081 unsigned Align = TLI.getTargetData()->
5081 getABITypeAlignment(SVT.getTypeForEVT());
5082 getABITypeAlignment(SVT.getTypeForEVT(*DAG.getContext()));
50825083 if (Align <= OrigAlign &&
50835084 ((!LegalOperations && !ST->isVolatile()) ||
50845085 TLI.isOperationLegalOrCustom(ISD::STORE, SVT)))
53585359 // Check the resultant load doesn't need a higher alignment than the
53595360 // original load.
53605361 unsigned NewAlign =
5361 TLI.getTargetData()->getABITypeAlignment(LVT.getTypeForEVT());
5362 TLI.getTargetData()->getABITypeAlignment(LVT.getTypeForEVT(*DAG.getContext()));
53625363
53635364 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT))
53645365 return SDValue();
6868 if (!TLI.isTypeLegal(VT)) {
6969 // Promote MVT::i1 to a legal type though, because it's common and easy.
7070 if (VT == MVT::i1)
71 VT = TLI.getTypeToTransformTo(VT).getSimpleVT();
71 VT = TLI.getTypeToTransformTo(V->getContext(), VT).getSimpleVT();
7272 else
7373 return 0;
7474 }
201201 if (VT == MVT::i1 &&
202202 (ISDOpcode == ISD::AND || ISDOpcode == ISD::OR ||
203203 ISDOpcode == ISD::XOR))
204 VT = TLI.getTypeToTransformTo(VT);
204 VT = TLI.getTypeToTransformTo(I->getContext(), VT);
205205 else
206206 return false;
207207 }
522522
523523 // If the operand is i1, arrange for the high bits in the register to be zero.
524524 if (SrcVT == MVT::i1) {
525 SrcVT = TLI.getTypeToTransformTo(SrcVT);
525 SrcVT = TLI.getTypeToTransformTo(I->getContext(), SrcVT);
526526 InputReg = FastEmitZExtFromI1(SrcVT.getSimpleVT(), InputReg);
527527 if (!InputReg)
528528 return false;
529529 }
530530 // If the result is i1, truncate to the target's type for i1 first.
531531 if (DstVT == MVT::i1)
532 DstVT = TLI.getTypeToTransformTo(DstVT);
532 DstVT = TLI.getTypeToTransformTo(I->getContext(), DstVT);
533533
534534 unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(),
535535 DstVT.getSimpleVT(),
100100 /// it is already legal or we need to expand it into multiple registers of
101101 /// smaller integer type, or we need to promote it to a larger type.
102102 LegalizeAction getTypeAction(EVT VT) const {
103 return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
103 return
104 (LegalizeAction)ValueTypeActions.getTypeAction(*DAG.getContext(), VT);
104105 }
105106
106107 /// isTypeLegal - Return true if this type is legal on this target.
360361 // smaller type.
361362 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) &&
362363 TLI.ShouldShrinkFPConstant(OrigVT)) {
363 const Type *SType = SVT.getTypeForEVT();
364 const Type *SType = SVT.getTypeForEVT(*DAG.getContext());
364365 LLVMC = cast(ConstantExpr::getFPTrunc(LLVMC, SType));
365366 VT = SVT;
366367 Extend = true;
391392 DebugLoc dl = ST->getDebugLoc();
392393 if (ST->getMemoryVT().isFloatingPoint() ||
393394 ST->getMemoryVT().isVector()) {
394 EVT intVT = EVT::getIntegerVT(VT.getSizeInBits());
395 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
395396 if (TLI.isTypeLegal(intVT)) {
396397 // Expand to a bitconvert of the value to the integer type of the
397398 // same size, then a (misaligned) int store.
404405 // to the final destination using (unaligned) integer loads and stores.
405406 EVT StoredVT = ST->getMemoryVT();
406407 EVT RegVT =
407 TLI.getRegisterType(EVT::getIntegerVT(StoredVT.getSizeInBits()));
408 TLI.getRegisterType(*DAG.getContext(), EVT::getIntegerVT(*DAG.getContext(), StoredVT.getSizeInBits()));
408409 unsigned StoredBytes = StoredVT.getSizeInBits() / 8;
409410 unsigned RegBytes = RegVT.getSizeInBits() / 8;
410411 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes;
438439 // The last store may be partial. Do a truncating store. On big-endian
439440 // machines this requires an extending load from the stack slot to ensure
440441 // that the bits are in the right place.
441 EVT MemVT = EVT::getIntegerVT(8 * (StoredBytes - Offset));
442 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), 8 * (StoredBytes - Offset));
442443
443444 // Load from the stack slot.
444445 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr,
493494 EVT LoadedVT = LD->getMemoryVT();
494495 DebugLoc dl = LD->getDebugLoc();
495496 if (VT.isFloatingPoint() || VT.isVector()) {
496 EVT intVT = EVT::getIntegerVT(LoadedVT.getSizeInBits());
497 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), LoadedVT.getSizeInBits());
497498 if (TLI.isTypeLegal(intVT)) {
498499 // Expand to a (misaligned) integer load of the same size,
499500 // then bitconvert to floating point or vector.
509510 } else {
510511 // Copy the value to a (aligned) stack slot using (unaligned) integer
511512 // loads and stores, then do a (aligned) load from the stack slot.
512 EVT RegVT = TLI.getRegisterType(intVT);
513 EVT RegVT = TLI.getRegisterType(*DAG.getContext(), intVT);
513514 unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8;
514515 unsigned RegBytes = RegVT.getSizeInBits() / 8;
515516 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes;
539540 }
540541
541542 // The last copy may be partial. Do an extending load.
542 EVT MemVT = EVT::getIntegerVT(8 * (LoadedBytes - Offset));
543 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), 8 * (LoadedBytes - Offset));
543544 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr,
544545 LD->getSrcValue(), SVOffset + Offset,
545546 MemVT, LD->isVolatile(),
570571 // integer MVT.
571572 unsigned NumBits = LoadedVT.getSizeInBits();
572573 EVT NewLoadedVT;
573 NewLoadedVT = EVT::getIntegerVT(NumBits/2);
574 NewLoadedVT = EVT::getIntegerVT(*DAG.getContext(), NumBits/2);
574575 NumBits >>= 1;
575576
576577 unsigned Alignment = LD->getAlignment();
10691070 // expand it.
10701071 if (!TLI.allowsUnalignedMemoryAccesses()) {
10711072 unsigned ABIAlignment = TLI.getTargetData()->
1072 getABITypeAlignment(LD->getMemoryVT().getTypeForEVT());
1073 getABITypeAlignment(LD->getMemoryVT().getTypeForEVT(*DAG.getContext()));
10731074 if (LD->getAlignment() < ABIAlignment){
10741075 Result = ExpandUnalignedLoad(cast(Result.getNode()),
10751076 DAG, TLI);
11261127 // Promote to a byte-sized load if not loading an integral number of
11271128 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
11281129 unsigned NewWidth = SrcVT.getStoreSizeInBits();
1129 EVT NVT = EVT::getIntegerVT(NewWidth);
1130 EVT NVT = EVT::getIntegerVT(*DAG.getContext(), NewWidth);
11301131 SDValue Ch;
11311132
11321133 // The extra bits are guaranteed to be zero, since we stored them that
11641165 assert(ExtraWidth < RoundWidth);
11651166 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
11661167 "Load size not an integral number of bytes!");
1167 EVT RoundVT = EVT::getIntegerVT(RoundWidth);
1168 EVT ExtraVT = EVT::getIntegerVT(ExtraWidth);
1168 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
1169 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
11691170 SDValue Lo, Hi, Ch;
11701171 unsigned IncrementSize;
11711172
12521253 // expand it.
12531254 if (!TLI.allowsUnalignedMemoryAccesses()) {
12541255 unsigned ABIAlignment = TLI.getTargetData()->
1255 getABITypeAlignment(LD->getMemoryVT().getTypeForEVT());
1256 getABITypeAlignment(LD->getMemoryVT().getTypeForEVT(*DAG.getContext()));
12561257 if (LD->getAlignment() < ABIAlignment){
12571258 Result = ExpandUnalignedLoad(cast(Result.getNode()),
12581259 DAG, TLI);
13301331 // expand it.
13311332 if (!TLI.allowsUnalignedMemoryAccesses()) {
13321333 unsigned ABIAlignment = TLI.getTargetData()->
1333 getABITypeAlignment(ST->getMemoryVT().getTypeForEVT());
1334 getABITypeAlignment(ST->getMemoryVT().getTypeForEVT(*DAG.getContext()));
13341335 if (ST->getAlignment() < ABIAlignment)
13351336 Result = ExpandUnalignedStore(cast(Result.getNode()), DAG,
13361337 TLI);
13611362 // Promote to a byte-sized store with upper bits zero if not
13621363 // storing an integral number of bytes. For example, promote
13631364 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
1364 EVT NVT = EVT::getIntegerVT(StVT.getStoreSizeInBits());
1365 EVT NVT = EVT::getIntegerVT(*DAG.getContext(), StVT.getStoreSizeInBits());
13651366 Tmp3 = DAG.getZeroExtendInReg(Tmp3, dl, StVT);
13661367 Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
13671368 SVOffset, NVT, isVolatile, Alignment);
13751376 assert(ExtraWidth < RoundWidth);
13761377 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
13771378 "Store size not an integral number of bytes!");
1378 EVT RoundVT = EVT::getIntegerVT(RoundWidth);
1379 EVT ExtraVT = EVT::getIntegerVT(ExtraWidth);
1379 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
1380 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
13801381 SDValue Lo, Hi;
13811382 unsigned IncrementSize;
13821383
14291430 // expand it.
14301431 if (!TLI.allowsUnalignedMemoryAccesses()) {
14311432 unsigned ABIAlignment = TLI.getTargetData()->
1432 getABITypeAlignment(ST->getMemoryVT().getTypeForEVT());
1433 getABITypeAlignment(ST->getMemoryVT().getTypeForEVT(*DAG.getContext()));
14331434 if (ST->getAlignment() < ABIAlignment)
14341435 Result = ExpandUnalignedStore(cast(Result.getNode()), DAG,
14351436 TLI);
16951696 // Create the stack frame object.
16961697 unsigned SrcAlign =
16971698 TLI.getTargetData()->getPrefTypeAlignment(SrcOp.getValueType().
1698 getTypeForEVT());
1699 getTypeForEVT(*DAG.getContext()));
16991700 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
17001701
17011702 FrameIndexSDNode *StackPtrFI = cast(FIPtr);
17061707 unsigned SlotSize = SlotVT.getSizeInBits();
17071708 unsigned DestSize = DestVT.getSizeInBits();
17081709 unsigned DestAlign =
1709 TLI.getTargetData()->getPrefTypeAlignment(DestVT.getTypeForEVT());
1710 TLI.getTargetData()->getPrefTypeAlignment(DestVT.getTypeForEVT(*DAG.getContext()));
17101711
17111712 // Emit a store to the stack slot. Use a truncstore if the input value is
17121713 // later than DestVT.
18001801 CV.push_back(const_cast(V->getConstantIntValue()));
18011802 } else {
18021803 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
1803 const Type *OpNTy = OpVT.getTypeForEVT();
1804 const Type *OpNTy = OpVT.getTypeForEVT(*DAG.getContext());
18041805 CV.push_back(UndefValue::get(OpNTy));
18051806 }
18061807 }
18541855 TargetLowering::ArgListEntry Entry;
18551856 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
18561857 EVT ArgVT = Node->getOperand(i).getValueType();
1857 const Type *ArgTy = ArgVT.getTypeForEVT();
1858 const Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
18581859 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
18591860 Entry.isSExt = isSigned;
18601861 Entry.isZExt = !isSigned;
18641865 TLI.getPointerTy());
18651866
18661867 // Splice the libcall in wherever FindInputOutputChains tells us to.
1867 const Type *RetTy = Node->getValueType(0).getTypeForEVT();
1868 const Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
18681869 std::pair CallInfo =
18691870 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
18701871 0, CallingConv::C, false,
23562357 // Increment the pointer, VAList, to the next vaarg
23572358 Tmp3 = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList,
23582359 DAG.getConstant(TLI.getTargetData()->
2359 getTypeAllocSize(VT.getTypeForEVT()),
2360 getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext())),
23602361 TLI.getPointerTy()));
23612362 // Store the incremented VAList to the legalized pointer
23622363 Tmp3 = DAG.getStore(VAList.getValue(1), dl, Tmp3, Tmp2, V, 0);
27562757 BottomHalf = DAG.getNode(Ops[isSigned][1], dl, DAG.getVTList(VT, VT), LHS,
27572758 RHS);
27582759 TopHalf = BottomHalf.getValue(1);
2759 } else if (TLI.isTypeLegal(EVT::getIntegerVT(VT.getSizeInBits() * 2))) {
2760 EVT WideVT = EVT::getIntegerVT(VT.getSizeInBits() * 2);
2760 } else if (TLI.isTypeLegal(EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits() * 2))) {
2761 EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits() * 2);
27612762 LHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, LHS);
27622763 RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS);
27632764 Tmp1 = DAG.getNode(ISD::MUL, dl, WideVT, LHS, RHS);
28222823 Index, DAG.getConstant(EntrySize, PTy));
28232824 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
28242825
2825 EVT MemVT = EVT::getIntegerVT(EntrySize * 8);
2826 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8);
28262827 SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, dl, PTy, Chain, Addr,
28272828 PseudoSourceValue::getJumpTable(), 0, MemVT);
28282829 Addr = LD;
107107 SDValue DAGTypeLegalizer::SoftenFloatRes_BUILD_PAIR(SDNode *N) {
108108 // Convert the inputs to integers, and build a new pair out of them.
109109 return DAG.getNode(ISD::BUILD_PAIR, N->getDebugLoc(),
110 TLI.getTypeToTransformTo(N->getValueType(0)),
110 TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)),
111111 BitConvertToInteger(N->getOperand(0)),
112112 BitConvertToInteger(N->getOperand(1)));
113113 }
114114
115115 SDValue DAGTypeLegalizer::SoftenFloatRes_ConstantFP(ConstantFPSDNode *N) {
116116 return DAG.getConstant(N->getValueAPF().bitcastToAPInt(),
117 TLI.getTypeToTransformTo(N->getValueType(0)));
117 TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)));
118118 }
119119
120120 SDValue DAGTypeLegalizer::SoftenFloatRes_EXTRACT_VECTOR_ELT(SDNode *N) {
125125 }
126126
127127 SDValue DAGTypeLegalizer::SoftenFloatRes_FABS(SDNode *N) {
128 EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
128 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
129129 unsigned Size = NVT.getSizeInBits();
130130
131131 // Mask = ~(1 << (Size-1))
136136 }
137137
138138 SDValue DAGTypeLegalizer::SoftenFloatRes_FADD(SDNode *N) {
139 EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
139 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
140140 SDValue Ops[2] = { GetSoftenedFloat(N->getOperand(0)),
141141 GetSoftenedFloat(N->getOperand(1)) };
142142 return MakeLibCall(GetFPLibCall(N->getValueType(0),
148148 }
149149
150150 SDValue DAGTypeLegalizer::SoftenFloatRes_FCEIL(SDNode *N) {
151 EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
151 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
152152 SDValue Op = GetSoftenedFloat(N->getOperand(0));
153153 return MakeLibCall(GetFPLibCall(N->getValueType(0),
154154 RTLIB::CEIL_F32,
199199 }
200200
201201 SDValue DAGTypeLegalizer::SoftenFloatRes_FCOS(SDNode *N) {
202 EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
202 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
203203 SDValue Op = GetSoftenedFloat(N->getOperand(0));
204204 return MakeLibCall(GetFPLibCall(N->getValueType(0),
205205 RTLIB::COS_F32,
210210 }
211211
212212 SDValue DAGTypeLegalizer::SoftenFloatRes_FDIV(SDNode *N) {
213 EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
213 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
214214 SDValue Ops[2] = { GetSoftenedFloat(N->getOperand(0)),
215215 GetSoftenedFloat(N->getOperand(1)) };
216216 return MakeLibCall(GetFPLibCall(N->getValueType(0),
222222 }
223223
224224 SDValue DAGTypeLegalizer::SoftenFloatRes_FEXP(SDNode *N) {
225 EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
225 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
226226 SDValue Op = GetSoftenedFloat(N->getOperand(0));
227227 return MakeLibCall(GetFPLibCall(N->getValueType(0),
228228 RTLIB::EXP_F32,
233233 }
234234
235235 SDValue DAGTypeLegalizer::SoftenFloatRes_FEXP2(SDNode *N) {
236 EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
236 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
237237 SDValue Op = GetSoftenedFloat(N->getOperand(0));
238238 return MakeLibCall(GetFPLibCall(N->getValueType(0),
239239 RTLIB::EXP2_F32,
244244 }
245245
246246 SDValue DAGTypeLegalizer::SoftenFloatRes_FFLOOR(SDNode *N) {
247 EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
247 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
248248 SDValue Op = GetSoftenedFloat(N->getOperand(0));
249249 return MakeLibCall(GetFPLibCall(N->getValueType(0),
250250 RTLIB::FLOOR_F32,
255255 }
256256
257257 SDValue DAGTypeLegalizer::SoftenFloatRes_FLOG(SDNode *N) {
258 EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
258 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
259259 SDValue Op = GetSoftenedFloat(N->getOperand(0));
260260 return MakeLibCall(GetFPLibCall(N->getValueType(0),
261261 RTLIB::LOG_F32,
266266 }
267267
268268 SDValue DAGTypeLegalizer::SoftenFloatRes_FLOG2(SDNode *N) {
269 EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
269 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
270270 SDValue Op = GetSoftenedFloat(N->getOperand(0));
271271 return MakeLibCall(GetFPLibCall(N->getValueType(0),
272272 RTLIB::LOG2_F32,
277277 }
278278
279279 SDValue DAGTypeLegalizer::SoftenFloatRes_FLOG10(SDNode *N) {
280 EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
280 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
281281 SDValue Op = GetSoftenedFloat(N->getOperand(0));
282282 return MakeLibCall(GetFPLibCall(N->getValueType(0),
283283 RTLIB::LOG10_F32,
288288 }
289289
290290 SDValue DAGTypeLegalizer::SoftenFloatRes_FMUL(SDNode *N) {
291 EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
291 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
292292 SDValue Ops[2] = { GetSoftenedFloat(N->getOperand(0)),
293293 GetSoftenedFloat(N->getOperand(1)) };
294294 return MakeLibCall(GetFPLibCall(N->getValueType(0),
300300 }
301301
302302 SDValue DAGTypeLegalizer::SoftenFloatRes_FNEARBYINT(SDNode *N) {
303 EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
303 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
304304 SDValue Op = GetSoftenedFloat(N->getOperand(0));
305305 return MakeLibCall(GetFPLibCall(N->getValueType(0),
306306 RTLIB::NEARBYINT_F32,
311311 }
312312
313313 SDValue DAGTypeLegalizer::SoftenFloatRes_FNEG(SDNode *N) {
314 EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
314 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
315315 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
316316 SDValue Ops[2] = { DAG.getConstantFP(-0.0, N->getValueType(0)),
317317 GetSoftenedFloat(N->getOperand(0)) };
324324 }
325325
326326 SDValue DAGTypeLegalizer::SoftenFloatRes_FP_EXTEND(SDNode *N) {
327 EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
327 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
328328 SDValue Op = N->getOperand(0);
329329 RTLIB::Libcall LC = RTLIB::getFPEXT(Op.getValueType(), N->getValueType(0));
330330 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_EXTEND!");
332332 }
333333
334334 SDValue DAGTypeLegalizer::SoftenFloatRes_FP_ROUND(SDNode *N) {
335 EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
335 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
336336 SDValue Op = N->getOperand(0);
337337 RTLIB::Libcall LC = RTLIB::getFPROUND(Op.getValueType(), N->getValueType(0));
338338 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_ROUND!");
340340 }
341341
342342 SDValue DAGTypeLegalizer::SoftenFloatRes_FPOW(SDNode *N) {
343 EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
343 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
344344 SDValue Ops[2] = { GetSoftenedFloat(N->getOperand(0)),
345345 GetSoftenedFloat(N->getOperand(1)) };
346346 return MakeLibCall(GetFPLibCall(N->getValueType(0),
354354 SDValue DAGTypeLegalizer::SoftenFloatRes_FPOWI(SDNode *N) {
355355 assert(N->getOperand(1).getValueType() == MVT::i32 &&
356356 "Unsupported power type!");
357 EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
357 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
358358 SDValue Ops[2] = { GetSoftenedFloat(N->getOperand(0)), N->getOperand(1) };
359359 return MakeLibCall(GetFPLibCall(N->getValueType(0),
360360 RTLIB::POWI_F32,
365365 }
366366
367367 SDValue DAGTypeLegalizer::SoftenFloatRes_FREM(SDNode *N) {
368 EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
368 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
369369 SDValue Ops[2] = { GetSoftenedFloat(N->getOperand(0)),
370370 GetSoftenedFloat(N->getOperand(1)) };
371371 return MakeLibCall(GetFPLibCall(N->getValueType(0),
377377 }
378378
379379 SDValue DAGTypeLegalizer::SoftenFloatRes_FRINT(SDNode *N) {
380 EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
380 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
381381 SDValue Op = GetSoftenedFloat(N->getOperand(0));
382382 return MakeLibCall(GetFPLibCall(N->getValueType(0),
383383 RTLIB::RINT_F32,
388388 }
389389
390390 SDValue DAGTypeLegalizer::SoftenFloatRes_FSIN(SDNode *N) {
391 EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
391 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
392392 SDValue Op = GetSoftenedFloat(N->getOperand(0));
393393 return MakeLibCall(GetFPLibCall(N->getValueType(0),
394394 RTLIB::SIN_F32,
399399 }
400400
401401 SDValue DAGTypeLegalizer::SoftenFloatRes_FSQRT(SDNode *N) {
402 EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
402 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
403403 SDValue Op = GetSoftenedFloat(N->getOperand(0));
404404 return MakeLibCall(GetFPLibCall(N->getValueType(0),
405405 RTLIB::SQRT_F32,
410410 }
411411
412412 SDValue DAGTypeLegalizer::SoftenFloatRes_FSUB(SDNode *N) {
413 EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
413 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
414414 SDValue Ops[2] = { GetSoftenedFloat(N->getOperand(0)),
415415 GetSoftenedFloat(N->getOperand(1)) };
416416 return MakeLibCall(GetFPLibCall(N->getValueType(0),
422422 }
423423
424424 SDValue DAGTypeLegalizer::SoftenFloatRes_FTRUNC(SDNode *N) {
425 EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
425 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
426426 SDValue Op = GetSoftenedFloat(N->getOperand(0));
427427 return MakeLibCall(GetFPLibCall(N->getValueType(0),
428428 RTLIB::TRUNC_F32,
435435 SDValue DAGTypeLegalizer::SoftenFloatRes_LOAD(SDNode *N) {
436436 LoadSDNode *L = cast(N);
437437 EVT VT = N->getValueType(0);
438 EVT NVT = TLI.getTypeToTransformTo(VT);
438 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
439439 DebugLoc dl = N->getDebugLoc();
440440
441441 SDValue NewL;
479479 }
480480
481481 SDValue DAGTypeLegalizer::SoftenFloatRes_UNDEF(SDNode *N) {
482 return DAG.getUNDEF(TLI.getTypeToTransformTo(N->getValueType(0)));
482 return DAG.getUNDEF(TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)));
483483 }
484484
485485 SDValue DAGTypeLegalizer::SoftenFloatRes_VAARG(SDNode *N) {
486486 SDValue Chain = N->getOperand(0); // Get the chain.
487487 SDValue Ptr = N->getOperand(1); // Get the pointer.
488488 EVT VT = N->getValueType(0);
489 EVT NVT = TLI.getTypeToTransformTo(VT);
489 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
490490 DebugLoc dl = N->getDebugLoc();
491491
492492 SDValue NewVAARG;
521521 // Sign/zero extend the argument if the libcall takes a larger type.
522522 SDValue Op = DAG.getNode(Signed ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, dl,
523523 NVT, N->getOperand(0));
524 return MakeLibCall(LC, TLI.getTypeToTransformTo(RVT), &Op, 1, false, dl);
524 return MakeLibCall(LC, TLI.getTypeToTransformTo(*DAG.getContext(), RVT), &Op, 1, false, dl);
525525 }
526526
527527
828828
829829 void DAGTypeLegalizer::ExpandFloatRes_ConstantFP(SDNode *N, SDValue &Lo,
830830 SDValue &Hi) {
831 EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
831 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
832832 assert(NVT.getSizeInBits() == integerPartWidth &&
833833 "Do not know how to expand this float constant!");
834834 APInt C = cast(N)->getValueAPF().bitcastToAPInt();
980980
981981 void DAGTypeLegalizer::ExpandFloatRes_FP_EXTEND(SDNode *N, SDValue &Lo,
982982 SDValue &Hi) {
983 EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
983 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
984984 Hi = DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), NVT, N->getOperand(0));
985985 Lo = DAG.getConstantFP(APFloat(APInt(NVT.getSizeInBits(), 0)), NVT);
986986 }
10651065 SDValue Ptr = LD->getBasePtr();
10661066 DebugLoc dl = N->getDebugLoc();
10671067
1068 EVT NVT = TLI.getTypeToTransformTo(LD->getValueType(0));
1068 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), LD->getValueType(0));
10691069 assert(NVT.isByteSized() && "Expanded type not byte sized!");
10701070 assert(LD->getMemoryVT().bitsLE(NVT) && "Float type not round?");
10711071
10891089 SDValue &Hi) {
10901090 assert(N->getValueType(0) == MVT::ppcf128 && "Unsupported XINT_TO_FP!");
10911091 EVT VT = N->getValueType(0);
1092 EVT NVT = TLI.getTypeToTransformTo(VT);
1092 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
10931093 SDValue Src = N->getOperand(0);
10941094 EVT SrcVT = Src.getValueType();
10951095 bool isSigned = N->getOpcode() == ISD::SINT_TO_FP;
13711371 SDValue Chain = ST->getChain();
13721372 SDValue Ptr = ST->getBasePtr();
13731373
1374 EVT NVT = TLI.getTypeToTransformTo(ST->getValue().getValueType());
1374 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), ST->getValue().getValueType());
13751375 assert(NVT.isByteSized() && "Expanded type not byte sized!");
13761376 assert(ST->getMemoryVT().bitsLE(NVT) && "Float type not round?");
13771377
162162 SDValue DAGTypeLegalizer::PromoteIntRes_BIT_CONVERT(SDNode *N) {
163163 SDValue InOp = N->getOperand(0);
164164 EVT InVT = InOp.getValueType();
165 EVT NInVT = TLI.getTypeToTransformTo(InVT);
165 EVT NInVT = TLI.getTypeToTransformTo(*DAG.getContext(), InVT);
166166 EVT OutVT = N->getValueType(0);
167 EVT NOutVT = TLI.getTypeToTransformTo(OutVT);
167 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
168168 DebugLoc dl = N->getDebugLoc();
169169
170170 switch (getTypeAction(InVT)) {
201201 std::swap(Lo, Hi);
202202
203203 InOp = DAG.getNode(ISD::ANY_EXTEND, dl,
204 EVT::getIntegerVT(NOutVT.getSizeInBits()),
204 EVT::getIntegerVT(*DAG.getContext(), NOutVT.getSizeInBits()),
205205 JoinIntegers(Lo, Hi));
206206 return DAG.getNode(ISD::BIT_CONVERT, dl, NOutVT, InOp);
207207 }
230230 // The pair element type may be legal, or may not promote to the same type as
231231 // the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases.
232232 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(),
233 TLI.getTypeToTransformTo(N->getValueType(0)),
233 TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)),
234234 JoinIntegers(N->getOperand(0), N->getOperand(1)));
235235 }
236236
241241 // Zero extend things like i1, sign extend everything else. It shouldn't
242242 // matter in theory which one we pick, but this tends to give better code?
243243 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
244 SDValue Result = DAG.getNode(Opc, dl, TLI.getTypeToTransformTo(VT),
244 SDValue Result = DAG.getNode(Opc, dl, TLI.getTypeToTransformTo(*DAG.getContext(), VT),
245245 SDValue(N, 0));
246246 assert(isa(Result) && "Didn't constant fold ext?");
247247 return Result;
253253 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
254254 CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) &&
255255 "can only promote integers");
256 EVT OutVT = TLI.getTypeToTransformTo(N->getValueType(0));
256 EVT OutVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
257257 return DAG.getConvertRndSat(OutVT, N->getDebugLoc(), N->getOperand(0),
258258 N->getOperand(1), N->getOperand(2),
259259 N->getOperand(3), N->getOperand(4), CvtCode);
294294
295295 SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) {
296296 DebugLoc dl = N->getDebugLoc();
297 EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
297 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
298298 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NVT, N->getOperand(0),
299299 N->getOperand(1));
300300 }
301301
302302 SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) {
303 EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
303 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
304304 unsigned NewOpc = N->getOpcode();
305305 DebugLoc dl = N->getDebugLoc();
306306
324324 }
325325
326326 SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) {
327 EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
327 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
328328 DebugLoc dl = N->getDebugLoc();
329329
330330 if (getTypeAction(N->getOperand(0).getValueType()) == PromoteInteger) {
351351
352352 SDValue DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) {
353353 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
354 EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
354 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
355355 ISD::LoadExtType ExtType =
356356 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType();
357357 DebugLoc dl = N->getDebugLoc();
369369 /// Promote the overflow flag of an overflowing arithmetic node.
370370 SDValue DAGTypeLegalizer::PromoteIntRes_Overflow(SDNode *N) {
371371 // Simply change the return type of the boolean result.
372 EVT NVT = TLI.getTypeToTransformTo(N->getValueType(1));
372 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(1));
373373 EVT ValueVTs[] = { N->getValueType(0), NVT };
374374 SDValue Ops[] = { N->getOperand(0), N->getOperand(1) };
375375 SDValue Res = DAG.getNode(N->getOpcode(), N->getDebugLoc(),
444444 N->getOperand(1), N->getOperand(2));
445445
446446 // Convert to the expected type.
447 EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
447 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
448448 assert(NVT.bitsLE(SVT) && "Integer type overpromoted?");
449449 return DAG.getNode(ISD::TRUNCATE, dl, NVT, SetCC);
450450 }
451451
452452 SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) {
453453 return DAG.getNode(ISD::SHL, N->getDebugLoc(),
454 TLI.getTypeToTransformTo(N->getValueType(0)),
454 TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)),
455455 GetPromotedInteger(N->getOperand(0)), N->getOperand(1));
456456 }
457457
481481 SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) {
482482 // The input value must be properly zero extended.
483483 EVT VT = N->getValueType(0);
484 EVT NVT = TLI.getTypeToTransformTo(VT);
484 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
485485 SDValue Res = ZExtPromotedInteger(N->getOperand(0));
486486 return DAG.getNode(ISD::SRL, N->getDebugLoc(), NVT, Res, N->getOperand(1));
487487 }
488488
489489 SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) {
490 EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
490 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
491491 SDValue Res;
492492
493493 switch (getTypeAction(N->getOperand(0).getValueType())) {
542542 }
543543
544544 SDValue DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) {
545 return DAG.getUNDEF(TLI.getTypeToTransformTo(N->getValueType(0)));
545 return DAG.getUNDEF(TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)));
546546 }
547547
548548 SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) {
551551 EVT VT = N->getValueType(0);
552552 DebugLoc dl = N->getDebugLoc();
553553
554 EVT RegVT = TLI.getRegisterType(VT);
555 unsigned NumRegs = TLI.getNumRegisters(VT);
554 EVT RegVT = TLI.getRegisterType(*DAG.getContext(), VT);
555 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), VT);
556556 // The argument is passed as NumRegs registers of type RegVT.
557557
558558 SmallVector Parts(NumRegs);
566566 std::reverse(Parts.begin(), Parts.end());
567567
568568 // Assemble the parts in the promoted type.
569 EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
569 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
570570 SDValue Res = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[0]);
571571 for (unsigned i = 1; i < NumRegs; ++i) {
572572 SDValue Part = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[i]);
10061006 Hi = InL;
10071007 } else if (Amt == 1 &&
10081008 TLI.isOperationLegalOrCustom(ISD::ADDC,
1009 TLI.getTypeToExpandTo(NVT))) {
1009 TLI.getTypeToExpandTo(*DAG.getContext(), NVT))) {
10101010 // Emit this X << 1 as X+X.
10111011 SDVTList VTList = DAG.getVTList(NVT, MVT::Flag);
10121012 SDValue LoOps[2] = { InL, InL };
10761076 bool DAGTypeLegalizer::
10771077 ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
10781078 SDValue Amt = N->getOperand(1);
1079 EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1079 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
10801080 EVT ShTy = Amt.getValueType();
10811081 unsigned ShBits = ShTy.getSizeInBits();
10821082 unsigned NVTBits = NVT.getSizeInBits();
11541154 bool DAGTypeLegalizer::
11551155 ExpandShiftWithUnknownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
11561156 SDValue Amt = N->getOperand(1);
1157 EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1157 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
11581158 EVT ShTy = Amt.getValueType();
11591159 unsigned NVTBits = NVT.getSizeInBits();
11601160 assert(isPowerOf2_32(NVTBits) &&
12411241 bool hasCarry =
12421242 TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ?
12431243 ISD::ADDC : ISD::SUBC,
1244 TLI.getTypeToExpandTo(NVT));
1244 TLI.getTypeToExpandTo(*DAG.getContext(), NVT));
12451245
12461246 if (hasCarry) {
12471247 SDVTList VTList = DAG.getVTList(NVT, MVT::Flag);
13301330
13311331 void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N,
13321332 SDValue &Lo, SDValue &Hi) {
1333 EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1333 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
13341334 DebugLoc dl = N->getDebugLoc();
13351335 SDValue Op = N->getOperand(0);
13361336 if (Op.getValueType().bitsLE(NVT)) {
13611361
13621362 if (NVTBits < EVTBits) {
13631363 Hi = DAG.getNode(ISD::AssertSext, dl, NVT, Hi,
1364 DAG.getValueType(EVT::getIntegerVT(EVTBits - NVTBits)));
1364 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(), EVTBits - NVTBits)));
13651365 } else {
13661366 Lo = DAG.getNode(ISD::AssertSext, dl, NVT, Lo, DAG.getValueType(EVT));
13671367 // The high part replicates the sign bit of Lo, make it explicit.
13811381
13821382 if (NVTBits < EVTBits) {
13831383 Hi = DAG.getNode(ISD::AssertZext, dl, NVT, Hi,
1384 DAG.getValueType(EVT::getIntegerVT(EVTBits - NVTBits)));
1384 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(), EVTBits - NVTBits)));
13851385 } else {
13861386 Lo = DAG.getNode(ISD::AssertZext, dl, NVT, Lo, DAG.getValueType(EVT));
13871387 // The high part must be zero, make it explicit.
13991399
14001400 void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N,
14011401 SDValue &Lo, SDValue &Hi) {
1402 EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1402 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
14031403 unsigned NBitWidth = NVT.getSizeInBits();
14041404 const APInt &Cst = cast(N)->getAPIntValue();
14051405 Lo = DAG.getConstant(APInt(Cst).trunc(NBitWidth), NVT);
14851485 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
14861486
14871487 EVT VT = N->getValueType(0);
1488 EVT NVT = TLI.getTypeToTransformTo(VT);
1488 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
14891489 SDValue Ch = N->getChain();
14901490 SDValue Ptr = N->getBasePtr();
14911491 ISD::LoadExtType ExtType = N->getExtensionType();
15261526
15271527 unsigned ExcessBits =
15281528 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
1529 EVT NEVT = EVT::getIntegerVT(ExcessBits);
1529 EVT NEVT = EVT::getIntegerVT(*DAG.getContext(), ExcessBits);
15301530
15311531 // Increment the pointer to the other half.
15321532 unsigned IncrementSize = NVT.getSizeInBits()/8;
15501550
15511551 // Load both the high bits and maybe some of the low bits.
15521552 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getSrcValue(), SVOffset,
1553 EVT::getIntegerVT(EVT.getSizeInBits() - ExcessBits),
1553 EVT::getIntegerVT(*DAG.getContext(), EVT.getSizeInBits() - ExcessBits),
15541554 isVolatile, Alignment);
15551555
15561556 // Increment the pointer to the other half.
15591559 // Load the rest of the low bits.
15601560 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, NVT, Ch, Ptr, N->getSrcValue(),
15611561 SVOffset+IncrementSize,
1562 EVT::getIntegerVT(ExcessBits),
1562 EVT::getIntegerVT(*DAG.getContext(), ExcessBits),
15631563 isVolatile, MinAlign(Alignment, IncrementSize));
15641564
15651565 // Build a factor node to remember that this load is independent of the
15991599 void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N,
16001600 SDValue &Lo, SDValue &Hi) {
16011601 EVT VT = N->getValueType(0);
1602 EVT NVT = TLI.getTypeToTransformTo(VT);
1602 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
16031603 DebugLoc dl = N->getDebugLoc();
16041604
16051605 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, NVT);
17341734
17351735 // Next check to see if the target supports this SHL_PARTS operation or if it
17361736 // will custom expand it.
1737 EVT NVT = TLI.getTypeToTransformTo(VT);
1737 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
17381738 TargetLowering::LegalizeAction Action = TLI.getOperationAction(PartsOpc, NVT);
17391739 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
17401740 Action == TargetLowering::Custom) {
17971797
17981798 void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N,
17991799 SDValue &Lo, SDValue &Hi) {
1800 EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1800 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
18011801 DebugLoc dl = N->getDebugLoc();
18021802 SDValue Op = N->getOperand(0);
18031803 if (Op.getValueType().bitsLE(NVT)) {
18201820 unsigned ExcessBits =
18211821 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
18221822 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
1823 DAG.getValueType(EVT::getIntegerVT(ExcessBits)));
1823 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(), ExcessBits)));
18241824 }
18251825 }
18261826
18461846 unsigned ExcessBits =
18471847 EVT.getSizeInBits() - Lo.getValueType().getSizeInBits();
18481848 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
1849 DAG.getValueType(EVT::getIntegerVT(ExcessBits)));
1849 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(), ExcessBits)));
18501850 }
18511851 }
18521852
18721872
18731873 void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N,
18741874 SDValue &Lo, SDValue &Hi) {
1875 EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1875 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
18761876 DebugLoc dl = N->getDebugLoc();
18771877 Lo = DAG.getNode(ISD::TRUNCATE, dl, NVT, N->getOperand(0));
18781878 Hi = DAG.getNode(ISD::SRL, dl,
19231923
19241924 void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N,
19251925 SDValue &Lo, SDValue &Hi) {
1926 EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1926 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
19271927 DebugLoc dl = N->getDebugLoc();
19281928 SDValue Op = N->getOperand(0);
19291929 if (Op.getValueType().bitsLE(NVT)) {
19421942 SplitInteger(Res, Lo, Hi);
19431943 unsigned ExcessBits =
19441944 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
1945 Hi = DAG.getZeroExtendInReg(Hi, dl, EVT::getIntegerVT(ExcessBits));
1945 Hi = DAG.getZeroExtendInReg(Hi, dl, EVT::getIntegerVT(*DAG.getContext(), ExcessBits));
19461946 }
19471947 }
19481948
21882188 assert(OpNo == 1 && "Can only expand the stored value so far");
21892189
21902190 EVT VT = N->getOperand(1).getValueType();
2191 EVT NVT = TLI.getTypeToTransformTo(VT);
2191 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
21922192 SDValue Ch = N->getChain();
21932193 SDValue Ptr = N->getBasePtr();
21942194 int SVOffset = N->getSrcValueOffset();
22122212
22132213 unsigned ExcessBits =
22142214 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
2215 EVT NEVT = EVT::getIntegerVT(ExcessBits);
2215 EVT NEVT = EVT::getIntegerVT(*DAG.getContext(), ExcessBits);
22162216
22172217 // Increment the pointer to the other half.
22182218 unsigned IncrementSize = NVT.getSizeInBits()/8;
22312231 unsigned EBytes = ExtVT.getStoreSizeInBits()/8;
22322232 unsigned IncrementSize = NVT.getSizeInBits()/8;
22332233 unsigned ExcessBits = (EBytes - IncrementSize)*8;
2234 EVT HiVT = EVT::getIntegerVT(ExtVT.getSizeInBits() - ExcessBits);
2234 EVT HiVT = EVT::getIntegerVT(*DAG.getContext(), ExtVT.getSizeInBits() - ExcessBits);
22352235
22362236 if (ExcessBits < NVT.getSizeInBits()) {
22372237 // Transfer high bits from the top of Lo to the bottom of Hi.
22542254 // Store the lowest ExcessBits bits in the second half.
22552255 Lo = DAG.getTruncStore(Ch, dl, Lo, Ptr, N->getSrcValue(),
22562256 SVOffset+IncrementSize,
2257 EVT::getIntegerVT(ExcessBits),
2257 EVT::getIntegerVT(*DAG.getContext(), ExcessBits),
22582258 isVolatile, MinAlign(Alignment, IncrementSize));
22592259 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
22602260 }
731731 }
732732
733733 void DAGTypeLegalizer::SetPromotedInteger(SDValue Op, SDValue Result) {
734 assert(Result.getValueType() == TLI.getTypeToTransformTo(Op.getValueType()) &&
734 assert(Result.getValueType() == TLI.getTypeToTransformTo(*DAG.getContext(), Op.getValueType()) &&
735735 "Invalid type for promoted integer");
736736 AnalyzeNewValue(Result);
737737
741741 }
742742
743743 void DAGTypeLegalizer::SetSoftenedFloat(SDValue Op, SDValue Result) {
744 assert(Result.getValueType() == TLI.getTypeToTransformTo(Op.getValueType()) &&
744 assert(Result.getValueType() == TLI.getTypeToTransformTo(*DAG.getContext(), Op.getValueType()) &&
745745 "Invalid type for softened float");
746746 AnalyzeNewValue(Result);
747747
772772
773773 void DAGTypeLegalizer::SetExpandedInteger(SDValue Op, SDValue Lo,
774774 SDValue Hi) {
775 assert(Lo.getValueType() == TLI.getTypeToTransformTo(Op.getValueType()) &&
775 assert(Lo.getValueType() == TLI.getTypeToTransformTo(*DAG.getContext(), Op.getValueType()) &&
776776 Hi.getValueType() == Lo.getValueType() &&
777777 "Invalid type for expanded integer");
778778 // Lo/Hi may have been newly allocated, if so, add nodeid's as relevant.
798798
799799 void DAGTypeLegalizer::SetExpandedFloat(SDValue Op, SDValue Lo,
800800 SDValue Hi) {
801 assert(Lo.getValueType() == TLI.getTypeToTransformTo(Op.getValueType()) &&
801 assert(Lo.getValueType() == TLI.getTypeToTransformTo(*DAG.getContext(), Op.getValueType()) &&
802802 Hi.getValueType() == Lo.getValueType() &&
803803 "Invalid type for expanded float");
804804 // Lo/Hi may have been newly allocated, if so, add nodeid's as relevant.
842842 }
843843
844844 void DAGTypeLegalizer::SetWidenedVector(SDValue Op, SDValue Result) {
845 assert(Result.getValueType() == TLI.getTypeToTransformTo(Op.getValueType()) &&
845 assert(Result.getValueType() == TLI.getTypeToTransformTo(*DAG.getContext(), Op.getValueType()) &&
846846 "Invalid type for widened vector");
847847 AnalyzeNewValue(Result);
848848
860860 SDValue DAGTypeLegalizer::BitConvertToInteger(SDValue Op) {
861861 unsigned BitWidth = Op.getValueType().getSizeInBits();
862862 return DAG.getNode(ISD::BIT_CONVERT, Op.getDebugLoc(),
863 EVT::getIntegerVT(BitWidth), Op);
863 EVT::getIntegerVT(*DAG.getContext(), BitWidth), Op);
864864 }
865865
866866 /// BitConvertVectorToIntegerVector - Convert to a vector of integers of the
868868 SDValue DAGTypeLegalizer::BitConvertVectorToIntegerVector(SDValue Op) {
869869 assert(Op.getValueType().isVector() && "Only applies to vectors!");
870870 unsigned EltWidth = Op.getValueType().getVectorElementType().getSizeInBits();
871 EVT EltNVT = EVT::getIntegerVT(EltWidth);
871 EVT EltNVT = EVT::getIntegerVT(*DAG.getContext(), EltWidth);
872872 unsigned NumElts = Op.getValueType().getVectorNumElements();
873873 return DAG.getNode(ISD::BIT_CONVERT, Op.getDebugLoc(),
874 EVT::getVectorVT(EltNVT, NumElts), Op);
874 EVT::getVectorVT(*DAG.getContext(), EltNVT, NumElts), Op);
875875 }
876876
877877 SDValue DAGTypeLegalizer::CreateStackStoreLoad(SDValue Op,
922922 void DAGTypeLegalizer::GetSplitDestVTs(EVT InVT, EVT &LoVT, EVT &HiVT) {
923923 // Currently all types are split in half.
924924 if (!InVT.isVector()) {
925 LoVT = HiVT = TLI.getTypeToTransformTo(InVT);
925 LoVT = HiVT = TLI.getTypeToTransformTo(*DAG.getContext(), InVT);
926926 } else {
927927 unsigned NumElements = InVT.getVectorNumElements();
928928 assert(!(NumElements & 1) && "Splitting vector, but not in half!");
929 LoVT = HiVT = EVT::getVectorVT(InVT.getVectorElementType(), NumElements/2);
929 LoVT = HiVT = EVT::getVectorVT(*DAG.getContext(), InVT.getVectorElementType(), NumElements/2);
930930 }
931931 }
932932
935935 void DAGTypeLegalizer::GetPairElements(SDValue Pair,
936936 SDValue &Lo, SDValue &Hi) {
937937 DebugLoc dl = Pair.getDebugLoc();
938 EVT NVT = TLI.getTypeToTransformTo(Pair.getValueType());
938 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), Pair.getValueType());
939939 Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, NVT, Pair,
940940 DAG.getIntPtrConstant(0));
941941 Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, NVT, Pair,
966966 DebugLoc dlLo = Lo.getDebugLoc();
967967 EVT LVT = Lo.getValueType();
968968 EVT HVT = Hi.getValueType();
969 EVT NVT = EVT::getIntegerVT(LVT.getSizeInBits() + HVT.getSizeInBits());
969 EVT NVT = EVT::getIntegerVT(*DAG.getContext(), LVT.getSizeInBits() + HVT.getSizeInBits());
970970
971971 Lo = DAG.getNode(ISD::ZERO_EXTEND, dlLo, NVT, Lo);
972972 Hi = DAG.getNode(ISD::ANY_EXTEND, dlHi, NVT, Hi);
10071007 TargetLowering::ArgListEntry Entry;
10081008 for (unsigned i = 0; i != NumOps; ++i) {
10091009 Entry.Node = Ops[i];
1010 Entry.Ty = Entry.Node.getValueType().getTypeForEVT();
1010 Entry.Ty = Entry.Node.getValueType().getTypeForEVT(*DAG.getContext());
10111011 Entry.isSExt = isSigned;
10121012 Entry.isZExt = !isSigned;
10131013 Args.push_back(Entry);
10151015 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
10161016 TLI.getPointerTy());
10171017
1018 const Type *RetTy = RetVT.getTypeForEVT();
1018 const Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
10191019 std::pair CallInfo =
10201020 TLI.LowerCallTo(DAG.getEntryNode(), RetTy, isSigned, !isSigned, false,
10211021 false, 0, CallingConv::C, false,
10681068 /// type half the size of Op's.
10691069 void DAGTypeLegalizer::SplitInteger(SDValue Op,
10701070 SDValue &Lo, SDValue &Hi) {
1071 EVT HalfVT = EVT::getIntegerVT(Op.getValueType().getSizeInBits()/2);
1071 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), Op.getValueType().getSizeInBits()/2);
10721072 SplitInteger(Op, HalfVT, HalfVT, Lo, Hi);
10731073 }
10741074
7474
7575 /// getTypeAction - Return how we should legalize values of this type.
7676 LegalizeAction getTypeAction(EVT VT) const {
77 switch (ValueTypeActions.getTypeAction(VT)) {
77 switch (ValueTypeActions.getTypeAction(*DAG.getContext(), VT)) {
7878 default:
7979 assert(false && "Unknown legalize action!");
8080 case TargetLowering::Legal:
9595 if (VT.isInteger())
9696 return ExpandInteger;
9797 else if (VT.getSizeInBits() ==
98 TLI.getTypeToTransformTo(VT).getSizeInBits())
98 TLI.getTypeToTransformTo(*DAG.getContext(), VT).getSizeInBits())
9999 return SoftenFloat;
100100 else
101101 return ExpandFloat;
109109
110110 /// isTypeLegal - Return true if this type is legal on this target.
111111 bool isTypeLegal(EVT VT) const {
112 return ValueTypeActions.getTypeAction(VT) == TargetLowering::Legal;
112 return (ValueTypeActions.getTypeAction(*DAG.getContext(), VT) ==
113 TargetLowering::Legal);
113114 }
114115
115116 /// IgnoreNodeResults - Pretend all of this node's results are legal.
3434 void DAGTypeLegalizer::ExpandRes_BIT_CONVERT(SDNode *N, SDValue &Lo,
3535 SDValue &Hi) {
3636 EVT OutVT = N->getValueType(0);
37 EVT NOutVT = TLI.getTypeToTransformTo(OutVT);
37 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
3838 SDValue InOp = N->getOperand(0);
3939 EVT InVT = InOp.getValueType();
4040 DebugLoc dl = N->getDebugLoc();
7575 case WidenVector: {
7676 assert(!(InVT.getVectorNumElements() & 1) && "Unsupported BIT_CONVERT");
7777 InOp = GetWidenedVector(InOp);
78 EVT InNVT = EVT::getVectorVT(InVT.getVectorElementType(),
78 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), InVT.getVectorElementType(),
7979 InVT.getVectorNumElements()/2);
8080 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp,
8181 DAG.getIntPtrConstant(0));
9292 if (InVT.isVector() && OutVT.isInteger()) {
9393 // Handle cases like i64 = BIT_CONVERT v1i64 on x86, where the operand
9494 // is legal but the result is not.
95 EVT NVT = EVT::getVectorVT(NOutVT, 2);
95 EVT NVT = EVT::getVectorVT(*DAG.getContext(), NOutVT, 2);
9696
9797 if (isTypeLegal(NVT)) {
9898 SDValue CastInOp = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, InOp);
114114 // Create the stack frame object. Make sure it is aligned for both
115115 // the source and expanded destination types.
116116 unsigned Alignment =
117 TLI.getTargetData()->getPrefTypeAlignment(NOutVT.getTypeForEVT());
117 TLI.getTargetData()->getPrefTypeAlignment(NOutVT.getTypeForEVT(*DAG.getContext()));
118118 SDValue StackPtr = DAG.CreateStackTemporary(InVT, Alignment);
119119 int SPFI = cast(StackPtr.getNode())->getIndex();
120120 const Value *SV = PseudoSourceValue::getFixedStack(SPFI);
167167 // Convert to a vector of the expanded element type, for example
168168 // <3 x i64> -> <6 x i32>.
169169 EVT OldVT = N->getValueType(0);
170 EVT NewVT = TLI.getTypeToTransformTo(OldVT);
170 EVT NewVT = TLI.getTypeToTransformTo(*DAG.getContext(), OldVT);
171171
172172 SDValue NewVec = DAG.getNode(ISD::BIT_CONVERT, dl,
173 EVT::getVectorVT(NewVT, 2*OldElts),
173 EVT::getVectorVT(*DAG.getContext(), NewVT, 2*OldElts),
174174 OldVec);
175175
176176 // Extract the elements at 2 * Idx and 2 * Idx + 1 from the new vector.
197197 DebugLoc dl = N->getDebugLoc();
198198
199199 LoadSDNode *LD = cast(N);
200 EVT NVT = TLI.getTypeToTransformTo(LD->getValueType(0));
200 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), LD->getValueType(0));
201201 SDValue Chain = LD->getChain();
202202 SDValue Ptr = LD->getBasePtr();
203203 int SVOffset = LD->getSrcValueOffset();
232232 }
233233
234234 void DAGTypeLegalizer::ExpandRes_VAARG(SDNode *N, SDValue &Lo, SDValue &Hi) {
235 EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
235 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
236236 SDValue Chain = N->getOperand(0);
237237 SDValue Ptr = N->getOperand(1);
238238 DebugLoc dl = N->getDebugLoc();
263263 // is no point, and it might create expansion loops). For example, on
264264 // x86 this turns v1i64 = BIT_CONVERT i64 into v1i64 = BIT_CONVERT v2i32.
265265 EVT OVT = N->getOperand(0).getValueType();
266 EVT NVT = EVT::getVectorVT(TLI.getTypeToTransformTo(OVT), 2);
266 EVT NVT = EVT::getVectorVT(*DAG.getContext(), TLI.getTypeToTransformTo(*DAG.getContext(), OVT), 2);
267267
268268 if (isTypeLegal(NVT)) {
269269 SDValue Parts[2];
286286 EVT VecVT = N->getValueType(0);
287287 unsigned NumElts = VecVT.getVectorNumElements();
288288 EVT OldVT = N->getOperand(0).getValueType();
289 EVT NewVT = TLI.getTypeToTransformTo(OldVT);
289 EVT NewVT = TLI.getTypeToTransformTo(*DAG.getContext(), OldVT);
290290 DebugLoc dl = N->getDebugLoc();
291291
292292 assert(OldVT == VecVT.getVectorElementType() &&
307307 }
308308
309309 SDValue NewVec = DAG.getNode(ISD::BUILD_VECTOR, dl,
310 EVT::getVectorVT(NewVT, NewElts.size()),
310 EVT::getVectorVT(*DAG.getContext(), NewVT, NewElts.size()),
311311 &NewElts[0], NewElts.size());
312312
313313 // Convert the new vector to the old vector type.
328328
329329 SDValue Val = N->getOperand(1);
330330 EVT OldEVT = Val.getValueType();
331 EVT NewEVT = TLI.getTypeToTransformTo(OldEVT);
331 EVT NewEVT = TLI.getTypeToTransformTo(*DAG.getContext(), OldEVT);
332332
333333 assert(OldEVT == VecVT.getVectorElementType() &&
334334 "Inserted element type doesn't match vector element type!");
335335
336336 // Bitconvert to a vector of twice the length with elements of the expanded
337337 // type, insert the expanded vector elements, and then convert back.
338 EVT NewVecVT = EVT::getVectorVT(NewEVT, NumElts*2);
338 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewEVT, NumElts*2);
339339 SDValue NewVec = DAG.getNode(ISD::BIT_CONVERT, dl,
340340 NewVecVT, N->getOperand(0));
341341
375375 DebugLoc dl = N->getDebugLoc();
376376
377377 StoreSDNode *St = cast(N);
378 EVT NVT = TLI.getTypeToTransformTo(St->getValue().getValueType());
378 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), St->getValue().getValueType());
379379 SDValue Chain = St->getChain();
380380 SDValue Ptr = St->getBasePtr();
381381 int SVOffset = St->getSrcValueOffset();
511511 }
512512
513513 // In the general case, convert the input to an integer and split it by hand.
514 EVT LoIntVT = EVT::getIntegerVT(LoVT.getSizeInBits());
515 EVT HiIntVT = EVT::getIntegerVT(HiVT.getSizeInBits());
514 EVT LoIntVT = EVT::getIntegerVT(*DAG.getContext(), LoVT.getSizeInBits());
515 EVT HiIntVT = EVT::getIntegerVT(*DAG.getContext(), HiVT.getSizeInBits());
516516 if (TLI.isBigEndian())
517517 std::swap(LoIntVT, HiIntVT);
518518
577577 switch (getTypeAction(InVT)) {
578578 default: llvm_unreachable("Unexpected type action!");
579579 case Legal: {
580 EVT InNVT = EVT::getVectorVT(InVT.getVectorElementType(),
580 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), InVT.getVectorElementType(),
581581 LoVT.getVectorNumElements());
582582 VLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, N->getOperand(0),
583583 DAG.getIntPtrConstant(0));
593593 // the two types must have different lengths. Use the widened result
594594 // and extract from it to do the split.
595595 SDValue InOp = GetWidenedVector(N->getOperand(0));
596 EVT InNVT = EVT::getVectorVT(InVT.getVectorElementType(),
596 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), InVT.getVectorElementType(),
597597 LoVT.getVectorNumElements());
598598 VLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp,
599599 DAG.getIntPtrConstant(0));
666666 // so use a truncating store.
667667 SDValue EltPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
668668 unsigned Alignment =
669 TLI.getTargetData()->getPrefTypeAlignment(VecVT.getTypeForEVT());
669 TLI.getTargetData()->getPrefTypeAlignment(VecVT.getTypeForEVT(*DAG.getContext()));
670670 Store = DAG.getTruncStore(Store, dl, Elt, EltPtr, NULL, 0, EltVT);
671671
672672 // Load the Lo part from the stack slot.
740740 // Split the input.
741741 EVT InVT = N->getOperand(0).getValueType();
742742 SDValue LL, LH, RL, RH;
743 EVT InNVT = EVT::getVectorVT(InVT.getVectorElementType(),
743 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), InVT.getVectorElementType(),
744744 LoVT.getVectorNumElements());
745745 LL = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(0),
746746 DAG.getIntPtrConstant(0));
768768 switch (getTypeAction(InVT)) {
769769 default: llvm_unreachable("Unexpected type action!");
770770 case Legal: {
771 EVT InNVT = EVT::getVectorVT(InVT.getVectorElementType(),
771 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), InVT.getVectorElementType(),
772772 LoVT.getVectorNumElements());
773773 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, N->getOperand(0),
774774 DAG.getIntPtrConstant(0));
784784 // the two types must have different lengths. Use the widened result
785785 // and extract from it to do the split.
786786 SDValue InOp = GetWidenedVector(N->getOperand(0));
787 EVT InNVT = EVT::getVectorVT(InVT.getVectorElementType(),
787 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), InVT.getVectorElementType(),
788788 LoVT.getVectorNumElements());
789789 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp,
790790 DAG.getIntPtrConstant(0));
974974 GetSplitVector(N->getOperand(0), Lo, Hi);
975975 EVT InVT = Lo.getValueType();
976976
977 EVT OutVT = EVT::getVectorVT(ResVT.getVectorElementType(),
977 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(),
978978 InVT.getVectorNumElements());
979979
980980 Lo = DAG.getNode(N->getOpcode(), dl, OutVT, Lo);
11961196
11971197 SDValue DAGTypeLegalizer::WidenVecRes_Binary(SDNode *N) {
11981198 // Binary op widening.
1199 EVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
1199 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
12001200 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
12011201 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
12021202 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), WidenVT, InOp1, InOp2);
12061206 SDValue InOp = N->getOperand(0);
12071207 DebugLoc dl = N->getDebugLoc();
12081208
1209 EVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
1209 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
12101210 unsigned WidenNumElts = WidenVT.getVectorNumElements();
12111211
12121212 EVT InVT = InOp.getValueType();
12131213 EVT InEltVT = InVT.getVectorElementType();
1214 EVT InWidenVT = EVT::getVectorVT(InEltVT, WidenNumElts);
1214 EVT InWidenVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, WidenNumElts);
12151215
12161216 unsigned Opcode = N->getOpcode();
12171217 unsigned InVTNumElts = InVT.getVectorNumElements();
12691269 }
12701270
12711271 SDValue DAGTypeLegalizer::WidenVecRes_Shift(SDNode *N) {
1272 EVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
1272 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
12731273 SDValue InOp = GetWidenedVector(N->getOperand(0));
12741274 SDValue ShOp = N->getOperand(1);
12751275
12781278 ShOp = GetWidenedVector(ShOp);
12791279 ShVT = ShOp.getValueType();
12801280 }
1281 EVT ShWidenVT = EVT::getVectorVT(ShVT.getVectorElementType(),
1281 EVT ShWidenVT = EVT::getVectorVT(*DAG.getContext(), ShVT.getVectorElementType(),
12821282 WidenVT.getVectorNumElements());
12831283 if (ShVT != ShWidenVT)
12841284 ShOp = ModifyToType(ShOp, ShWidenVT);
12881288
12891289 SDValue DAGTypeLegalizer::WidenVecRes_Unary(SDNode *N) {
12901290 // Unary op widening.
1291 EVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
1291 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
12921292 SDValue InOp = GetWidenedVector(N->getOperand(0));
12931293 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), WidenVT, InOp);
12941294 }
12971297 SDValue InOp = N->getOperand(0);
12981298 EVT InVT = InOp.getValueType();
12991299 EVT VT = N->getValueType(0);
1300 EVT WidenVT = TLI.getTypeToTransformTo(VT);
1300 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
13011301 DebugLoc dl = N->getDebugLoc();
13021302
13031303 switch (getTypeAction(InVT)) {
13411341 unsigned NewNumElts = WidenSize / InSize;
13421342 if (InVT.isVector()) {
13431343 EVT InEltVT = InVT.getVectorElementType();
1344 NewInVT= EVT::getVectorVT(InEltVT, WidenSize / InEltVT.getSizeInBits());
1344 NewInVT= EVT::getVectorVT(*DAG.getContext(), InEltVT, WidenSize / InEltVT.getSizeInBits());
13451345 } else {
1346 NewInVT = EVT::getVectorVT(InVT, NewNumElts);
1346 NewInVT = EVT::getVectorVT(*DAG.getContext(), InVT, NewNumElts);
13471347 }
13481348
13491349 if (TLI.isTypeLegal(NewInVT)) {
13791379 EVT EltVT = VT.getVectorElementType();
13801380 unsigned NumElts = VT.getVectorNumElements();
13811381
1382 EVT WidenVT = TLI.getTypeToTransformTo(VT);
1382 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
13831383 unsigned WidenNumElts = WidenVT.getVectorNumElements();
13841384
13851385 SmallVector NewOps(N->op_begin(), N->op_end());
13921392
13931393 SDValue DAGTypeLegalizer::WidenVecRes_CONCAT_VECTORS(SDNode *N) {
13941394 EVT InVT = N->getOperand(0).getValueType();
1395 EVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
1395 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
13961396 DebugLoc dl = N->getDebugLoc();
13971397 unsigned WidenNumElts = WidenVT.getVectorNumElements();
13981398 unsigned NumOperands = N->getNumOperands();
14131413 }
14141414 } else {
14151415 InputWidened = true;
1416 if (WidenVT == TLI.getTypeToTransformTo(InVT)) {
1416 if (WidenVT == TLI.getTypeToTransformTo(*DAG.getContext(), InVT)) {
14171417 // The inputs and the result are widen to the same value.
14181418 unsigned i;
14191419 for (i=1; i < NumOperands; ++i)
14651465 SDValue RndOp = N->getOperand(3);
14661466 SDValue SatOp = N->getOperand(4);
14671467
1468 EVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
1468 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
14691469 unsigned WidenNumElts = WidenVT.getVectorNumElements();
14701470
14711471 EVT InVT = InOp.getValueType();
14721472 EVT InEltVT = InVT.getVectorElementType();
1473 EVT InWidenVT = EVT::getVectorVT(InEltVT, WidenNumElts);
1473 EVT InWidenVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, WidenNumElts);
14741474
14751475 SDValue DTyOp = DAG.getValueType(WidenVT);
14761476 SDValue STyOp = DAG.getValueType(InWidenVT);
15391539
15401540 SDValue DAGTypeLegalizer::WidenVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
15411541 EVT VT = N->getValueType(0);
1542 EVT WidenVT = TLI.getTypeToTransformTo(VT);
1542 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
15431543 unsigned WidenNumElts = WidenVT.getVectorNumElements();
15441544 SDValue InOp = N->getOperand(0);
15451545 SDValue Idx = N->getOperand(1);
15991599
16001600 SDValue DAGTypeLegalizer::WidenVecRes_LOAD(SDNode *N) {
16011601 LoadSDNode *LD = cast(N);
1602 EVT WidenVT = TLI.getTypeToTransformTo(LD->getValueType(0));
1602 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), LD->getValueType(0));
16031603 EVT LdVT = LD->getMemoryVT();
16041604 DebugLoc dl = N->getDebugLoc();
16051605 assert(LdVT.isVector() && WidenVT.isVector());
16701670 }
16711671
16721672 SDValue DAGTypeLegalizer::WidenVecRes_SCALAR_TO_VECTOR(SDNode *N) {
1673 EVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
1673 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
16741674 return DAG.getNode(ISD::SCALAR_TO_VECTOR, N->getDebugLoc(),
16751675 WidenVT, N->getOperand(0));
16761676 }
16771677
16781678 SDValue DAGTypeLegalizer::WidenVecRes_SELECT(SDNode *N) {
1679 EVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
1679 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
16801680 unsigned WidenNumElts = WidenVT.getVectorNumElements();
16811681
16821682 SDValue Cond1 = N->getOperand(0);
16831683 EVT CondVT = Cond1.getValueType();
16841684 if (CondVT.isVector()) {
16851685 EVT CondEltVT = CondVT.getVectorElementType();
1686 EVT CondWidenVT = EVT::getVectorVT(CondEltVT, WidenNumElts);
1686 EVT CondWidenVT = EVT::getVectorVT(*DAG.getContext(), CondEltVT, WidenNumElts);
16871687 if (getTypeAction(CondVT) == WidenVector)
16881688 Cond1 = GetWidenedVector(Cond1);
16891689
17071707 }
17081708
17091709 SDValue DAGTypeLegalizer::WidenVecRes_UNDEF(SDNode *N) {
1710 EVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
1710 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
17111711 return DAG.getUNDEF(WidenVT);
17121712 }
17131713
17151715 EVT VT = N->getValueType(0);
17161716 DebugLoc dl = N->getDebugLoc();
17171717
1718 EVT WidenVT = TLI.getTypeToTransformTo(VT);
1718 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
17191719 unsigned NumElts = VT.getVectorNumElements();
17201720 unsigned WidenNumElts = WidenVT.getVectorNumElements();
17211721
17371737 }
17381738
17391739 SDValue DAGTypeLegalizer::WidenVecRes_VSETCC(SDNode *N) {
1740 EVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
1740 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
17411741 unsigned WidenNumElts = WidenVT.getVectorNumElements();
17421742
17431743 SDValue InOp1 = N->getOperand(0);
17441744 EVT InVT = InOp1.getValueType();
17451745 assert(InVT.isVector() && "can not widen non vector type");
1746 EVT WidenInVT = EVT::getVectorVT(InVT.getVectorElementType(), WidenNumElts);
1746 EVT WidenInVT = EVT::getVectorVT(*DAG.getContext(), InVT.getVectorElementType(), WidenNumElts);
17471747 InOp1 = GetWidenedVector(InOp1);
17481748 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
17491749
18421842 unsigned Size = VT.getSizeInBits();
18431843 if (InWidenSize % Size == 0 && !VT.isVector()) {
18441844 unsigned NewNumElts = InWidenSize / Size;
1845 EVT NewVT = EVT::getVectorVT(VT, NewNumElts);
1845 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), VT, NewNumElts);
18461846 if (TLI.isTypeLegal(NewVT)) {
18471847 SDValue BitOp = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, InOp);
18481848 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, BitOp,
19561956 // VecVT: Vector value type whose size we must match.
19571957 // Returns NewVecVT and NewEltVT - the vector type and its associated
19581958 // element type.
1959 static void FindAssocWidenVecType(const TargetLowering &TLI, unsigned Width,
1959 static void FindAssocWidenVecType(SelectionDAG& DAG,
1960 const TargetLowering &TLI, unsigned Width,
19601961 EVT VecVT,
19611962 EVT& NewEltVT, EVT& NewVecVT) {
19621963 unsigned EltWidth = Width + 1;
19681969 do {
19691970 assert(EltWidth > 0);
19701971 EltWidth = 1 << Log2_32(EltWidth - 1);
1971 NewEltVT = EVT::getIntegerVT(EltWidth);
1972 NewEltVT = EVT::getIntegerVT(*DAG.getContext(), EltWidth);
19721973 unsigned NumElts = VecVT.getSizeInBits() / EltWidth;
1973 NewVecVT = EVT::getVectorVT(NewEltVT, NumElts);
1974 NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewEltVT, NumElts);
19741975 } while (!TLI.isTypeLegal(NewVecVT) ||
19751976 VecVT.getSizeInBits() != NewVecVT.getSizeInBits());
19761977 } else {
19831984 do {
19841985 assert(EltWidth > 0);
19851986 EltWidth = 1 << Log2_32(EltWidth - 1);
1986 NewEltVT = EVT::getIntegerVT(EltWidth);
1987 NewEltVT = EVT::getIntegerVT(*DAG.getContext(), EltWidth);
19871988 unsigned NumElts = VecVT.getSizeInBits() / EltWidth;
1988 NewVecVT = EVT::getVectorVT(NewEltVT, NumElts);
1989 NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewEltVT, NumElts);
19891990 } while (!TLI.isTypeLegal(NewEltVT) ||
19901991 VecVT.getSizeInBits() != NewVecVT.getSizeInBits());
19911992 }
20122013 // Find the vector type that can load from.
20132014 EVT NewEltVT, NewVecVT;
20142015 unsigned NewEltVTWidth;
2015 FindAssocWidenVecType(TLI, LdWidth, ResType, NewEltVT, NewVecVT);
2016 FindAssocWidenVecType(DAG, TLI, LdWidth, ResType, NewEltVT, NewVecVT);
20162017 NewEltVTWidth = NewEltVT.getSizeInBits();
20172018
20182019 SDValue LdOp = DAG.getLoad(NewEltVT, dl, Chain, BasePtr, SV, SVOffset,
20392040 // Our current type we are using is too large, use a smaller size by
20402041 // using a smaller power of 2
20412042 unsigned oNewEltVTWidth = NewEltVTWidth;
2042 FindAssocWidenVecType(TLI, LdWidth, ResType, NewEltVT, NewVecVT);
2043 FindAssocWidenVecType(DAG, TLI, LdWidth, ResType, NewEltVT, NewVecVT);
20432044 NewEltVTWidth = NewEltVT.getSizeInBits();
20442045 // Readjust position and vector position based on new load type
20452046 Idx = Idx * (oNewEltVTWidth/NewEltVTWidth);
20772078 EVT WidenVT = ValOp.getValueType();
20782079 EVT NewEltVT, NewVecVT;
20792080
2080 FindAssocWidenVecType(TLI, StWidth, WidenVT, NewEltVT, NewVecVT);
2081 FindAssocWidenVecType(DAG, TLI, StWidth, WidenVT, NewEltVT, NewVecVT);
20812082 unsigned NewEltVTWidth = NewEltVT.getSizeInBits();
20822083
20832084 SDValue VecOp = DAG.getNode(ISD::BIT_CONVERT, dl, NewVecVT, ValOp);
21062107 // Our current type we are using is too large, use a smaller size by
21072108 // using a smaller power of 2
21082109 unsigned oNewEltVTWidth = NewEltVTWidth;
2109 FindAssocWidenVecType(TLI, StWidth, WidenVT, NewEltVT, NewVecVT);
2110 FindAssocWidenVecType(DAG, TLI, StWidth, WidenVT, NewEltVT, NewVecVT);
21102111 NewEltVTWidth = NewEltVT.getSizeInBits();
21112112 // Readjust position and vector position based on new load type
21122113 Idx = Idx * (oNewEltVTWidth/NewEltVTWidth);
789789 unsigned SelectionDAG::getEVTAlignment(EVT VT) const {
790790 const Type *Ty = VT == MVT::iPTR ?
791791 PointerType::get(Type::Int8Ty, 0) :
792 VT.getTypeForEVT();
792 VT.getTypeForEVT(*getContext());
793793
794794 return TLI.getTargetData()->getABITypeAlignment(Ty);
795795 }
13681368 SDValue SelectionDAG::CreateStackTemporary(EVT VT, unsigned minAlign) {
13691369 MachineFrameInfo *FrameInfo = getMachineFunction().getFrameInfo();
13701370 unsigned ByteSize = VT.getStoreSizeInBits()/8;
1371 const Type *Ty = VT.getTypeForEVT();
1371 const Type *Ty = VT.getTypeForEVT(*getContext());
13721372 unsigned StackAlign =
13731373 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), minAlign);
13741374
13811381 SDValue SelectionDAG::CreateStackTemporary(EVT VT1, EVT VT2) {
13821382 unsigned Bytes = std::max(VT1.getStoreSizeInBits(),
13831383 VT2.getStoreSizeInBits())/8;
1384 const Type *Ty1 = VT1.getTypeForEVT();
1385 const Type *Ty2 = VT2.getTypeForEVT();
1384 const Type *Ty1 = VT1.getTypeForEVT(*getContext());
1385 const Type *Ty2 = VT2.getTypeForEVT(*getContext());
13861386 const TargetData *TD = TLI.getTargetData();
13871387 unsigned Align = std::max(TD->getPrefTypeAlignment(Ty1),
13881388 TD->getPrefTypeAlignment(Ty2));
30433043 unsigned NumElts = VT.getVectorNumElements();
30443044 MVT EltVT = (VT.getVectorElementType() == MVT::f32) ? MVT::i32 : MVT::i64;
30453045 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
3046 DAG.getConstant(0, EVT::getVectorVT(EltVT, NumElts)));
3046 DAG.getConstant(0,
3047 EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts)));
30473048 }
30483049
30493050 assert(!VT.isVector() && "Can't handle vector type here!");
31073108 EVT VT = TLI.getOptimalMemOpType(Size, Align, isSrcConst, isSrcStr, DAG);
31083109 if (VT != MVT::iAny) {
31093110 unsigned NewAlign = (unsigned)
3110 TLI.getTargetData()->getABITypeAlignment(VT.getTypeForEVT());
3111 TLI.getTargetData()->getABITypeAlignment(
3112 VT.getTypeForEVT(*DAG.getContext()));
31113113 // If source is a string constant, this will require an unaligned load.
31123114 if (NewAlign > Align && (isSrcConst || AllowUnalign)) {
31133115 if (Dst.getOpcode() != ISD::FrameIndex) {
32263228 // thing to do is generate a LoadExt/StoreTrunc pair. These simplify
32273229 // to Load/Store if NVT==VT.
32283230 // FIXME does the case above also need this?
3229 EVT NVT = TLI.getTypeToTransformTo(VT);
3231 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
32303232 assert(NVT.bitsGE(VT));
32313233 Value = DAG.getExtLoad(ISD::EXTLOAD, dl, NVT, Chain,
32323234 getMemBasePlusOffset(Src, SrcOff, DAG),
192192 const SmallVector ®vts,
193193 const SmallVector &valuevts)
194194 : TLI(&tli), ValueVTs(valuevts), RegVTs(regvts), Regs(regs) {}
195 RegsForValue(const TargetLowering &tli,
195 RegsForValue(LLVMContext &Context, const TargetLowering &tli,
196196 unsigned Reg, const Type *Ty) : TLI(&tli) {
197197 ComputeValueVTs(tli, Ty, ValueVTs);
198198
199199 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
200200 EVT ValueVT = ValueVTs[Value];
201 unsigned NumRegs = TLI->getNumRegisters(ValueVT);
202 EVT RegisterVT = TLI->getRegisterType(ValueVT);
201 unsigned NumRegs = TLI->getNumRegisters(Context, ValueVT);
202 EVT RegisterVT = TLI->getRegisterType(Context, ValueVT);
203203 for (unsigned i = 0; i != NumRegs; ++i)
204204 Regs.push_back(Reg + i);
205205 RegVTs.push_back(RegisterVT);
357357 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
358358 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
359359 EVT VT = ValueVTs[vti];
360 unsigned NumRegisters = TLI.getNumRegisters(VT);
360 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT);
361361 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
362362 for (unsigned i = 0; i != NumRegisters; ++i)
363363 BuildMI(MBB, DL, TII->get(TargetInstrInfo::PHI), PHIReg + i);
385385 unsigned FirstReg = 0;
386386 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
387387 EVT ValueVT = ValueVTs[Value];
388 EVT RegisterVT = TLI.getRegisterType(ValueVT);
389
390 unsigned NumRegs = TLI.getNumRegisters(ValueVT);
388 EVT RegisterVT = TLI.getRegisterType(V->getContext(), ValueVT);
389
390 unsigned NumRegs = TLI.getNumRegisters(V->getContext(), ValueVT);
391391 for (unsigned i = 0; i != NumRegs; ++i) {
392392 unsigned R = MakeReg(RegisterVT);
393393 if (!FirstReg) FirstReg = R;
420420 1 << Log2_32(NumParts) : NumParts;
421421 unsigned RoundBits = PartBits * RoundParts;
422422 EVT RoundVT = RoundBits == ValueBits ?
423 ValueVT : EVT::getIntegerVT(RoundBits);
423 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
424424 SDValue Lo, Hi;
425425
426 EVT HalfVT = EVT::getIntegerVT(RoundBits/2);
426 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
427427
428428 if (RoundParts > 2) {
429429 Lo = getCopyFromParts(DAG, dl, Parts, RoundParts/2, PartVT, HalfVT);
440440 if (RoundParts < NumParts) {
441441 // Assemble the trailing non-power-of-2 part.
442442 unsigned OddParts = NumParts - RoundParts;
443 EVT OddVT = EVT::getIntegerVT(OddParts * PartBits);
443 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
444444 Hi = getCopyFromParts(DAG, dl,
445445 Parts+RoundParts, OddParts, PartVT, OddVT);
446446
448448 Lo = Val;
449449 if (TLI.isBigEndian())
450450 std::swap(Lo, Hi);
451 EVT TotalVT = EVT::getIntegerVT(NumParts * PartBits);
451 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
452452 Hi = DAG.getNode(ISD::ANY_EXTEND, dl, TotalVT, Hi);
453453 Hi = DAG.getNode(ISD::SHL, dl, TotalVT, Hi,
454454 DAG.getConstant(Lo.getValueType().getSizeInBits(),
461461 EVT IntermediateVT, RegisterVT;
462462 unsigned NumIntermediates;
463463 unsigned NumRegs =
464 TLI.getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
465 RegisterVT);
464 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
465 NumIntermediates, RegisterVT);
466466 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
467467 NumParts = NumRegs; // Silence a compiler warning.
468468 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
507507 // FP split into integer parts (soft fp)
508508 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
509509 !PartVT.isVector() && "Unexpected split");
510 EVT IntVT = EVT::getIntegerVT(ValueVT.getSizeInBits());
510 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
511511 Val = getCopyFromParts(DAG, dl, Parts, NumParts, PartVT, IntVT);
512512 }
513513 }
589589 assert(NumParts == 1 && "Do not know what to promote to!");
590590 Val = DAG.getNode(ISD::FP_EXTEND, dl, PartVT, Val);
591591 } else if (PartVT.isInteger() && ValueVT.isInteger()) {
592 ValueVT = EVT::getIntegerVT(NumParts * PartBits);
592 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
593593 Val = DAG.getNode(ExtendKind, dl, ValueVT, Val);
594594 } else {
595595 llvm_unreachable("Unknown mismatch!");
601601 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
602602 // If the parts cover less bits than value has, truncate the value.
603603 if (PartVT.isInteger() && ValueVT.isInteger()) {
604 ValueVT = EVT::getIntegerVT(NumParts * PartBits);
604 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
605605 Val = DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val);
606606 } else {
607607 llvm_unreachable("Unknown mismatch!");
635635 // The odd parts were reversed by getCopyToParts - unreverse them.
636636 std::reverse(Parts + RoundParts, Parts + NumParts);
637637 NumParts = RoundParts;
638 ValueVT = EVT::getIntegerVT(NumParts * PartBits);
638 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
639639 Val = DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val);
640640 }
641641
642642 // The number of parts is a power of 2. Repeatedly bisect the value using
643643 // EXTRACT_ELEMENT.
644644 Parts[0] = DAG.getNode(ISD::BIT_CONVERT, dl,
645 EVT::getIntegerVT(ValueVT.getSizeInBits()),
645 EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits()),
646646 Val);
647647 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
648648 for (unsigned i = 0; i < NumParts; i += StepSize) {
649649 unsigned ThisBits = StepSize * PartBits / 2;
650 EVT ThisVT = EVT::getIntegerVT (ThisBits);
650 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
651651 SDValue &Part0 = Parts[i];
652652 SDValue &Part1 = Parts[i+StepSize/2];
653653
695695 // Handle a multi-element vector.
696696 EVT IntermediateVT, RegisterVT;
697697 unsigned NumIntermediates;
698 unsigned NumRegs = TLI
699 .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
700 RegisterVT);
698 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
699 IntermediateVT, NumIntermediates, RegisterVT);
701700 unsigned NumElements = ValueVT.getVectorNumElements();
702701
703702 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
928927 unsigned InReg = FuncInfo.ValueMap[V];
929928 assert(InReg && "Value not in map!");
930929
931 RegsForValue RFV(TLI, InReg, V->getType());
930 RegsForValue RFV(*DAG.getContext(), TLI, InReg, V->getType());
932931 SDValue Chain = DAG.getEntryNode();
933932 return RFV.getCopyFromRegs(DAG, getCurDebugLoc(), Chain, NULL);
934933 }
960959 // conventions. The frontend should mark functions whose return values
961960 // require promoting with signext or zeroext attributes.
962961 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
963 EVT MinVT = TLI.getRegisterType(MVT::i32);
962 EVT MinVT = TLI.getRegisterType(*DAG.getContext(), MVT::i32);
964963 if (VT.bitsLT(MinVT))
965964 VT = MinVT;
966965 }
967966
968 unsigned NumParts = TLI.getNumRegisters(VT);
969 EVT PartVT = TLI.getRegisterType(VT);
967 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), VT);
968 EVT PartVT = TLI.getRegisterType(*DAG.getContext(), VT);
970969 SmallVector Parts(NumParts);
971970 getCopyToParts(DAG, getCurDebugLoc(),
972971 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
46084607 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
46094608 // Copy the legal parts from the registers.
46104609 EVT ValueVT = ValueVTs[Value];
4611 unsigned NumRegs = TLI->getNumRegisters(ValueVT);
4610 unsigned NumRegs = TLI->getNumRegisters(*DAG.getContext(), ValueVT);
46124611 EVT RegisterVT = RegVTs[Value];
46134612
46144613 Parts.resize(NumRegs);
46894688 SmallVector Parts(NumRegs);
46904689 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
46914690 EVT ValueVT = ValueVTs[Value];
4692 unsigned NumParts = TLI->getNumRegisters(ValueVT);
4691 unsigned NumParts = TLI->getNumRegisters(*DAG.getContext(), ValueVT);
46934692 EVT RegisterVT = RegVTs[Value];
46944693
46954694 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
47404739 Flag |= 0x80000000 | (MatchingIdx << 16);
47414740 Ops.push_back(DAG.getTargetConstant(Flag, IntPtrTy));
47424741 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
4743 unsigned NumRegs = TLI->getNumRegisters(ValueVTs[Value]);
4742 unsigned NumRegs = TLI->getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
47444743 EVT RegisterVT = RegVTs[Value];
47454744 for (unsigned i = 0; i != NumRegs; ++i) {
47464745 assert(Reg < Regs.size() && "Mismatch in # registers expected");
48984897 GetRegistersForValue(SDISelAsmOperandInfo &OpInfo,
48994898 std::set &OutputRegs,
49004899 std::set &InputRegs) {
4900 LLVMContext &Context = CurMBB->getParent()->getFunction()->getContext();
4901
49014902 // Compute whether this value requires an input register, an output register,
49024903 // or both.
49034904 bool isOutReg = false;
49504951 // bitcast to the corresponding integer type. This turns an f64 value
49514952 // into i64, which can be passed with two i32 values on a 32-bit
49524953 // machine.
4953 RegVT = EVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits());
4954 RegVT = EVT::getIntegerVT(Context,
4955 OpInfo.ConstraintVT.getSizeInBits());
49544956 OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
49554957 RegVT, OpInfo.CallOperand);
49564958 OpInfo.ConstraintVT = RegVT;
49574959 }
49584960 }
49594961
4960 NumRegs = TLI.getNumRegisters(OpInfo.ConstraintVT);
4962 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
49614963 }
49624964
49634965 EVT RegVT;
56245626 for (unsigned Value = 0, NumValues = ValueVTs.size();
56255627 Value != NumValues; ++Value) {
56265628 EVT VT = ValueVTs[Value];
5627 const Type *ArgTy = VT.getTypeForEVT();
5629 const Type *ArgTy = VT.getTypeForEVT(RetTy->getContext());
56285630 SDValue Op = SDValue(Args[i].Node.getNode(),
56295631 Args[i].Node.getResNo() + Value);
56305632 ISD::ArgFlagsTy Flags;
56565658 Flags.setNest();
56575659 Flags.setOrigAlign(OriginalAlignment);
56585660
5659 EVT PartVT = getRegisterType(VT);
5660 unsigned NumParts = getNumRegisters(VT);
5661 EVT PartVT = getRegisterType(RetTy->getContext(), VT);
5662 unsigned NumParts = getNumRegisters(RetTy->getContext(), VT);
56615663 SmallVector Parts(NumParts);
56625664 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
56635665
56875689 ComputeValueVTs(*this, RetTy, RetTys);
56885690 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
56895691 EVT VT = RetTys[I];
5690 EVT RegisterVT = getRegisterType(VT);
5691 unsigned NumRegs = getNumRegisters(VT);
5692 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT);
5693 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT);
56925694 for (unsigned i = 0; i != NumRegs; ++i) {
56935695 ISD::InputArg MyFlags;
56945696 MyFlags.VT = RegisterVT;
57475749 unsigned CurReg = 0;
57485750 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
57495751 EVT VT = RetTys[I];
5750 EVT RegisterVT = getRegisterType(VT);
5751 unsigned NumRegs = getNumRegisters(VT);
5752 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT);
5753 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT);
57525754
57535755 SDValue ReturnValue =
57545756 getCopyFromParts(DAG, dl, &InVals[CurReg], NumRegs, RegisterVT, VT,
57915793 "Copy from a reg to the same reg!");
57925794 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
57935795
5794 RegsForValue RFV(TLI, Reg, V->getType());
5796 RegsForValue RFV(V->getContext(), TLI, Reg, V->getType());
57955797 SDValue Chain = DAG.getEntryNode();
57965798 RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), Chain, 0);
57975799 PendingExports.push_back(Chain);
58195821 for (unsigned Value = 0, NumValues = ValueVTs.size();
58205822 Value != NumValues; ++Value) {
58215823 EVT VT = ValueVTs[Value];
5822 const Type *ArgTy = VT.getTypeForEVT();
5824 const Type *ArgTy = VT.getTypeForEVT(*CurDAG->getContext());
58235825 ISD::ArgFlagsTy Flags;
58245826 unsigned OriginalAlignment =
58255827 TD->getABITypeAlignment(ArgTy);
58495851 Flags.setNest();
58505852 Flags.setOrigAlign(OriginalAlignment);
58515853
5852 EVT RegisterVT = TLI.getRegisterType(VT);
5853 unsigned NumRegs = TLI.getNumRegisters(VT);
5854 EVT RegisterVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
5855 unsigned NumRegs = TLI.getNumRegisters(*CurDAG->getContext(), VT);
58545856 for (unsigned i = 0; i != NumRegs; ++i) {
58555857 ISD::InputArg MyFlags(Flags, RegisterVT, isArgValueUsed);
58565858 if (NumRegs > 1 && i == 0)
58955897 unsigned NumValues = ValueVTs.size();
58965898 for (unsigned Value = 0; Value != NumValues; ++Value) {
58975899 EVT VT = ValueVTs[Value];
5898 EVT PartVT = TLI.getRegisterType(VT);
5899 unsigned NumParts = TLI.getNumRegisters(VT);
5900 EVT PartVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
5901 unsigned NumParts = TLI.getNumRegisters(*CurDAG->getContext(), VT);
59005902
59015903 if (!I->use_empty()) {
59025904 ISD::NodeType AssertOp = ISD::DELETED_NODE;
59875989 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
59885990 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
59895991 EVT VT = ValueVTs[vti];
5990 unsigned NumRegisters = TLI.getNumRegisters(VT);
5992 unsigned NumRegisters = TLI.getNumRegisters(*CurDAG->getContext(), VT);
59915993 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
59925994 SDL->PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
59935995 Reg += NumRegisters;
60416043 if (VT == MVT::Other || !TLI.isTypeLegal(VT)) {
60426044 // Promote MVT::i1.
60436045 if (VT == MVT::i1)
6044 VT = TLI.getTypeToTransformTo(VT);
6046 VT = TLI.getTypeToTransformTo(*CurDAG->getContext(), VT);
60456047 else {
60466048 SDL->PHINodesToUpdate.resize(OrigNumPHINodesToUpdate);
60476049 return false;
531531 delete &TLOF;
532532 }
533533
534 static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT,
535 unsigned &NumIntermediates,
536 EVT &RegisterVT,
537 TargetLowering* TLI) {
538 // Figure out the right, legal destination reg to copy into.
539 unsigned NumElts = VT.getVectorNumElements();
540 MVT EltTy = VT.getVectorElementType();
541
542 unsigned NumVectorRegs = 1;
543
544 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
545 // could break down into LHS/RHS like LegalizeDAG does.
546 if (!isPowerOf2_32(NumElts)) {
547 NumVectorRegs = NumElts;
548 NumElts = 1;
549 }
550
551 // Divide the input until we get to a supported size. This will always
552 // end with a scalar if the target doesn't support vectors.
553 while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) {
554 NumElts >>= 1;
555 NumVectorRegs <<= 1;
556 }
557
558 NumIntermediates = NumVectorRegs;
559
560 MVT NewVT = MVT::getVectorVT(EltTy, NumElts);
561 if (!TLI->isTypeLegal(NewVT))
562 NewVT = EltTy;
563 IntermediateVT = NewVT;
564
565 EVT DestVT = TLI->getRegisterType(NewVT);
566 RegisterVT = DestVT;
567 if (EVT(DestVT).bitsLT(NewVT)) {
568 // Value is expanded, e.g. i64 -> i16.
569 return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits());
570 } else {
571 // Otherwise, promotion or legal types use the same number of registers as
572 // the vector decimated to the appropriate level.
573 return NumVectorRegs;
574 }
575
576 return 1;
577 }
578
534579 /// computeRegisterProperties - Once all of the register classes are added,
535580 /// this allows us to compute derived properties we expose.
536581 void TargetLowering::computeRegisterProperties() {
613658 // Loop over all of the vector value types to see which need transformations.
614659 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
615660 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
616 EVT VT = (MVT::SimpleValueType)i;
661 MVT VT = (MVT::SimpleValueType)i;
617662 if (!isTypeLegal(VT)) {
618 EVT IntermediateVT, RegisterVT;
663 MVT IntermediateVT;
664 EVT RegisterVT;
619665 unsigned NumIntermediates;
620666 NumRegistersForVT[i] =
621 getVectorTypeBreakdown(VT,
622 IntermediateVT, NumIntermediates,
623 RegisterVT);
667 getVectorTypeBreakdownMVT(VT, IntermediateVT, NumIntermediates,
668 RegisterVT, this);
624669 RegisterTypeForVT[i] = RegisterVT;
625670
626671 // Determine if there is a legal wider type.
661706 return getValueType(TD->getIntPtrType()).getSimpleVT().SimpleTy;
662707 }
663708
664
665709 /// getVectorTypeBreakdown - Vector types are broken down into some number of
666710 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
667711 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
671715 /// register. It also returns the VT and quantity of the intermediate values
672716 /// before they are promoted/expanded.
673717 ///
674 unsigned TargetLowering::getVectorTypeBreakdown(EVT VT,
718 unsigned TargetLowering::getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
675719 EVT &IntermediateVT,
676720 unsigned &NumIntermediates,
677 EVT &RegisterVT) const {
721 EVT &RegisterVT) const {
678722 // Figure out the right, legal destination reg to copy into.
679723 unsigned NumElts = VT.getVectorNumElements();
680724 EVT EltTy = VT.getVectorElementType();
690734
691735 // Divide the input until we get to a supported size. This will always
692736 // end with a scalar if the target doesn't support vectors.
693 while (NumElts > 1 && !isTypeLegal(EVT::getVectorVT(EltTy, NumElts))) {
737 while (NumElts > 1 && !isTypeLegal(
738 EVT::getVectorVT(Context, EltTy, NumElts))) {
694739 NumElts >>= 1;
695740 NumVectorRegs <<= 1;
696741 }
697742
698743 NumIntermediates = NumVectorRegs;
699744
700 EVT NewVT = EVT::getVectorVT(EltTy, NumElts);
745 EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts);
701746 if (!isTypeLegal(NewVT))
702747 NewVT = EltTy;
703748 IntermediateVT = NewVT;
704749
705 EVT DestVT = getRegisterType(NewVT);
750 EVT DestVT = getRegisterType(Context, NewVT);
706751 RegisterVT = DestVT;
707752 if (DestVT.bitsLT(NewVT)) {
708753 // Value is expanded, e.g. i64 -> i16.
829874 if (!isPowerOf2_32(SmallVTBits))
830875 SmallVTBits = NextPowerOf2(SmallVTBits);
831876 for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) {
832 EVT SmallVT = EVT::getIntegerVT(SmallVTBits);
877 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits);
833878 if (TLI.isTruncateFree(Op.getValueType(), SmallVT) &&
834879 TLI.isZExtFree(SmallVT, Op.getValueType())) {
835880 // We found a type with free casts.
15151560 ISD::CondCode Cond, bool foldBooleans,
15161561 DAGCombinerInfo &DCI, DebugLoc dl) const {
15171562 SelectionDAG &DAG = DCI.DAG;
1563 LLVMContext &Context = *DAG.getContext();
15181564
15191565 // These setcc operations always fold.
15201566 switch (Cond) {
15971643 }
15981644 }
15991645 if (bestWidth) {
1600 EVT newVT = EVT::getIntegerVT(bestWidth);
1646 EVT newVT = EVT::getIntegerVT(Context, bestWidth);
16011647 if (newVT.isRound()) {
16021648 EVT PtrType = Lod->getOperand(1).getValueType();
16031649 SDValue Ptr = Lod->getBasePtr();
725725 && OpVT == MVT::i64) {
726726 SDValue Op0 = Op.getOperand(0);
727727 EVT Op0VT = Op0.getValueType();
728 EVT Op0VecVT = EVT::getVectorVT(Op0VT, (128 / Op0VT.getSizeInBits()));
729 EVT OpVecVT = EVT::getVectorVT(OpVT, (128 / OpVT.getSizeInBits()));
728 EVT Op0VecVT = EVT::getVectorVT(*CurDAG->getContext(),
729 Op0VT, (128 / Op0VT.getSizeInBits()));
730 EVT OpVecVT = EVT::getVectorVT(*CurDAG->getContext(),
731 OpVT, (128 / OpVT.getSizeInBits()));
730732 SDValue shufMask;
731733
732734 switch (Op0VT.getSimpleVT().SimpleTy) {
968970 SDNode *
969971 SPUDAGToDAGISel::SelectSHLi64(SDValue &Op, EVT OpVT) {
970972 SDValue Op0 = Op.getOperand(0);
971 EVT VecVT = EVT::getVectorVT(OpVT, (128 / OpVT.getSizeInBits()));
973 EVT VecVT = EVT::getVectorVT(*CurDAG->getContext(),
974 OpVT, (128 / OpVT.getSizeInBits()));
972975 SDValue ShiftAmt = Op.getOperand(1);
973976 EVT ShiftAmtVT = ShiftAmt.getValueType();
974977 SDNode *VecOp0, *SelMask, *ZeroFill, *Shift = 0;
10331036 SDNode *
10341037 SPUDAGToDAGISel::SelectSRLi64(SDValue &Op, EVT OpVT) {
10351038 SDValue Op0 = Op.getOperand(0);
1036 EVT VecVT = EVT::getVectorVT(OpVT, (128 / OpVT.getSizeInBits()));
1039 EVT VecVT = EVT::getVectorVT(*CurDAG->getContext(),
1040 OpVT, (128 / OpVT.getSizeInBits()));
10371041 SDValue ShiftAmt = Op.getOperand(1);
10381042 EVT ShiftAmtVT = ShiftAmt.getValueType();
10391043 SDNode *VecOp0, *Shift = 0;
10991103 SDNode *
11001104 SPUDAGToDAGISel::SelectSRAi64(SDValue &Op, EVT OpVT) {
11011105 // Promote Op0 to vector
1102 EVT VecVT = EVT::getVectorVT(OpVT, (128 / OpVT.getSizeInBits()));
1106 EVT VecVT = EVT::getVectorVT(*CurDAG->getContext(),
1107 OpVT, (128 / OpVT.getSizeInBits()));
11031108 SDValue ShiftAmt = Op.getOperand(1);
11041109 EVT ShiftAmtVT = ShiftAmt.getValueType();
11051110 DebugLoc dl = Op.getDebugLoc();
11731178
11741179 SDNode *SPUDAGToDAGISel::SelectI64Constant(uint64_t Value64, EVT OpVT,
11751180 DebugLoc dl) {
1176 EVT OpVecVT = EVT::getVectorVT(OpVT, 2);
1181 EVT OpVecVT = EVT::getVectorVT(*CurDAG->getContext(), OpVT, 2);
11771182 SDValue i64vec =
11781183 SPU::LowerV2I64Splat(OpVecVT, *CurDAG, Value64, dl);
11791184
100100 TargetLowering::ArgListEntry Entry;
101101 for (unsigned i = 0, e = Op.getNumOperands(); i != e; ++i) {
102102 EVT ArgVT = Op.getOperand(i).getValueType();
103 const Type *ArgTy = ArgVT.getTypeForEVT();
103 const Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
104104 Entry.Node = Op.getOperand(i);
105105 Entry.Ty = ArgTy;
106106 Entry.isSExt = isSigned;
111111 TLI.getPointerTy());
112112
113113 // Splice the libcall in wherever FindInputOutputChains tells us to.
114 const Type *RetTy = Op.getNode()->getValueType(0).getTypeForEVT();
114 const Type *RetTy =
115 Op.getNode()->getValueType(0).getTypeForEVT(*DAG.getContext());
115116 std::pair CallInfo =
116117 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
117118 0, CallingConv::C, false,
682683
683684 // Convert the loaded v16i8 vector to the appropriate vector type
684685 // specified by the operand:
685 EVT vecVT = EVT::getVectorVT(InVT, (128 / InVT.getSizeInBits()));
686 EVT vecVT = EVT::getVectorVT(*DAG.getContext(),
687 InVT, (128 / InVT.getSizeInBits()));
686688 result = DAG.getNode(SPUISD::VEC2PREFSLOT, dl, InVT,
687689 DAG.getNode(ISD::BIT_CONVERT, dl, vecVT, result));
688690
748750 switch (SN->getAddressingMode()) {
749751 case ISD::UNINDEXED: {
750752 // The vector type we really want to load from the 16-byte chunk.
751 EVT vecVT = EVT::getVectorVT(VT, (128 / VT.getSizeInBits())),
752 stVecVT = EVT::getVectorVT(StVT, (128 / StVT.getSizeInBits()));
753 EVT vecVT = EVT::getVectorVT(*DAG.getContext(),
754 VT, (128 / VT.getSizeInBits())),
755 stVecVT = EVT::getVectorVT(*DAG.getContext(),
756 StVT, (128 / StVT.getSizeInBits()));
753757
754758 SDValue alignLoadVec;
755759 SDValue basePtr = SN->getBasePtr();
22512255 */
22522256 static SDValue LowerCTPOP(SDValue Op, SelectionDAG &DAG) {
22532257 EVT VT = Op.getValueType();
2254 EVT vecVT = EVT::getVectorVT(VT, (128 / VT.getSizeInBits()));
2258 EVT vecVT = EVT::getVectorVT(*DAG.getContext(),
2259 VT, (128 / VT.getSizeInBits()));
22552260 DebugLoc dl = Op.getDebugLoc();
22562261
22572262 switch (VT.getSimpleVT().SimpleTy) {
25742579 // Type to truncate to
25752580 EVT VT = Op.getValueType();
25762581 MVT simpleVT = VT.getSimpleVT();
2577 EVT VecVT = EVT::getVectorVT(VT, (128 / VT.getSizeInBits()));
2582 EVT VecVT = EVT::getVectorVT(*DAG.getContext(),
2583 VT, (128 / VT.getSizeInBits()));
25782584 DebugLoc dl = Op.getDebugLoc();
25792585
25802586 // Type to truncate from
398398 TargetLowering::ArgListEntry Entry;
399399 for (unsigned i = 0; i != NumOps; ++i) {
400400 Entry.Node = Ops[i];
401 Entry.Ty = Entry.Node.getValueType().getTypeForEVT();
401 Entry.Ty = Entry.Node.getValueType().getTypeForEVT(*DAG.getContext());
402402 Entry.isSExt = isSigned;
403403 Entry.isZExt = !isSigned;
404404 Args.push_back(Entry);
406406
407407 SDValue Callee = DAG.getExternalSymbol(getPIC16LibcallName(Call), MVT::i16);
408408
409 const Type *RetTy = RetVT.getTypeForEVT();
409 const Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
410410 std::pair CallInfo =
411411 LowerCallTo(DAG.getEntryNode(), RetTy, isSigned, !isSigned, false,
412412 false, 0, CallingConv::C, false,
690690 SDValue &Lo, SDValue &Hi) {
691691 SDNode *N = Op.getNode();
692692 DebugLoc dl = N->getDebugLoc();
693 EVT NewVT = getTypeToTransformTo(N->getValueType(0));
693 EVT NewVT = getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
694694
695695 // Extract the lo component.
696696 Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, NewVT, Op,
12861286
12871287 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
12881288 std::pair CallResult =
1289 LowerCallTo(Chain, Op.getValueType().getTypeForEVT(),
1289 LowerCallTo(Chain, Op.getValueType().getTypeForEVT(*DAG.getContext()),
12901290 false, false, false, false, 0, CallingConv::C, false,
12911291 /*isReturnValueUsed=*/true,
12921292 DAG.getExternalSymbol("__trampoline_setup", PtrVT),
372372 return SDValue();
373373 }
374374 unsigned ABIAlignment = getTargetData()->
375 getABITypeAlignment(LD->getMemoryVT().getTypeForEVT());
375 getABITypeAlignment(LD->getMemoryVT().getTypeForEVT(*DAG.getContext()));
376376 // Leave aligned load alone.
377377 if (LD->getAlignment() >= ABIAlignment) {
378378 return SDValue();
468468 return SDValue();
469469 }
470470 unsigned ABIAlignment = getTargetData()->
471 getABITypeAlignment(ST->getMemoryVT().getTypeForEVT());
471 getABITypeAlignment(ST->getMemoryVT().getTypeForEVT(*DAG.getContext()));
472472 // Leave aligned store alone.
473473 if (ST->getAlignment() >= ABIAlignment) {
474474 return SDValue();
10571057 if (StoreBits % 8) {
10581058 break;
10591059 }
1060 unsigned ABIAlignment = getTargetData()->
1061 getABITypeAlignment(ST->getMemoryVT().getTypeForEVT());
1060 unsigned ABIAlignment = getTargetData()->getABITypeAlignment(
1061 ST->getMemoryVT().getTypeForEVT(*DCI.DAG.getContext()));
10621062 unsigned Alignment = ST->getAlignment();
10631063 if (Alignment >= ABIAlignment) {
10641064 break;
422422 // If these values will be promoted, find out what they will be promoted
423423 // to. This helps us consider truncates on PPC as noop copies when they
424424 // are.
425 if (TLI.getTypeAction(SrcVT) == TargetLowering::Promote)
426 SrcVT = TLI.getTypeToTransformTo(SrcVT);
427 if (TLI.getTypeAction(DstVT) == TargetLowering::Promote)
428 DstVT = TLI.getTypeToTransformTo(DstVT);
425 if (TLI.getTypeAction(CI->getContext(), SrcVT) == TargetLowering::Promote)
426 SrcVT = TLI.getTypeToTransformTo(CI->getContext(), SrcVT);
427 if (TLI.getTypeAction(CI->getContext(), DstVT) == TargetLowering::Promote)
428 DstVT = TLI.getTypeToTransformTo(CI->getContext(), DstVT);
429429
430430 // If, after promotion, these are the same types, this is a noop copy.
431431 if (SrcVT != DstVT)
1818 #include "llvm/Support/ErrorHandling.h"
1919 using namespace llvm;
2020
21 EVT EVT::getExtendedIntegerVT(unsigned BitWidth) {
21 EVT EVT::getExtendedIntegerVT(LLVMContext &Context, unsigned BitWidth) {
2222 EVT VT;
2323 VT.LLVMTy = IntegerType::get(BitWidth);
2424 assert(VT.isExtended() && "Type is not extended!");
2525 return VT;
2626 }
2727
28 EVT EVT::getExtendedVectorVT(EVT VT, unsigned NumElements) {
28 EVT EVT::getExtendedVectorVT(LLVMContext &Context, EVT VT,
29 unsigned NumElements) {
2930 EVT ResultVT;
30 ResultVT.LLVMTy = VectorType::get(VT.getTypeForEVT(), NumElements);
31 ResultVT.LLVMTy = VectorType::get(VT.getTypeForEVT(Context), NumElements);
3132 assert(ResultVT.isExtended() && "Type is not extended!");
3233 return ResultVT;
3334 }
130131 /// getTypeForEVT - This method returns an LLVM type corresponding to the
131132 /// specified EVT. For integer types, this returns an unsigned type. Note
132133 /// that this will abort for types that cannot be represented.
133 const Type *EVT::getTypeForEVT() const {
134 const Type *EVT::getTypeForEVT(LLVMContext &Context) const {
134135 switch (V.SimpleTy) {
135136 default:
136137 assert(isExtended() && "Type is not extended!");
178179 default:
179180 if (HandleUnknown) return MVT(MVT::Other);
180181 llvm_unreachable("Unknown type!");
181 return MVT(MVT::isVoid);
182 return MVT::isVoid;
182183 case Type::VoidTyID:
183 return MVT(MVT::isVoid);
184 return MVT::isVoid;
184185 case Type::IntegerTyID:
185 return getIntegerVT(cast(Ty)->getBitWidth());
186 return getIntegerVT(Ty->getContext(), cast(Ty)->getBitWidth());
186187 case Type::FloatTyID: return MVT(MVT::f32);
187188 case Type::DoubleTyID: return MVT(MVT::f64);
188189 case Type::X86_FP80TyID: return MVT(MVT::f80);
191192 case Type::PointerTyID: return MVT(MVT::iPTR);
192193 case Type::VectorTyID: {
193194 const VectorType *VTy = cast(Ty);
194 return getVectorVT(getEVT(VTy->getElementType(), false),
195 return getVectorVT(Ty->getContext(), getEVT(VTy->getElementType(), false),
195196 VTy->getNumElements());
196197 }
197198 }
16341634 "vector elements!", F);
16351635 return false;
16361636 }
1637 } else if (EVT((MVT::SimpleValueType)VT).getTypeForEVT() != EltTy) {
1637 } else if (EVT((MVT::SimpleValueType)VT).getTypeForEVT(Ty->getContext()) !=
1638 EltTy) {
16381639 CheckFailed(IntrinsicParam(ArgNo, NumRets) + " is wrong!", F);
16391640 return false;
16401641 } else if (EltTy != Ty) {
162162 O << Size << ", ";
163163 else
164164 O << "\n" << IndentStr << " State.getTarget().getTargetData()"
165 "->getTypeAllocSize(LocVT.getTypeForEVT()), ";
165 "->getTypeAllocSize(LocVT.getTypeForEVT(State.getContext())), ";
166166 if (Align)
167167 O << Align;
168168 else
169169 O << "\n" << IndentStr << " State.getTarget().getTargetData()"
170 "->getABITypeAlignment(LocVT.getTypeForEVT())";
170 "->getABITypeAlignment(LocVT.getTypeForEVT(State.getContext()))";
171171 O << ");\n" << IndentStr
172172 << "State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset"
173173 << Counter << ", LocVT, LocInfo));\n";
6363 static std::map, const Type *>
6464 ExtendedVectorTypeMap;
6565
66 EVT EVT::getExtendedIntegerVT(unsigned BitWidth) {
67 const Type *&ET = ExtendedIntegerTypeMap[BitWidth];
68 if (!ET) ET = new ExtendedIntegerType(BitWidth);
69 EVT VT;
70 VT.LLVMTy = ET;
71 assert(VT.isExtended() && "Type is not extended!");
72 return VT;
73 }
74
75 EVT EVT::getExtendedVectorVT(EVT VT, unsigned NumElements) {
76 const Type *&ET = ExtendedVectorTypeMap[std::make_pair(VT.getRawBits(),
77 NumElements)];
78 if (!ET) ET = new ExtendedVectorType(VT, NumElements);
79 EVT ResultVT;
80 ResultVT.LLVMTy = ET;
81 assert(ResultVT.isExtended() && "Type is not extended!");
82 return ResultVT;
83 }
84
8566 bool EVT::isExtendedFloatingPoint() const {
8667 assert(isExtended() && "Type is not extended!");
8768 // Extended floating-point types are not supported yet.