llvm.org GIT mirror llvm / 2365f51
Long live the exception handling! This patch fills the last necessary bits to enable exceptions handling in LLVM. Currently only on x86-32/linux. In fact, this patch adds necessary intrinsics (and their lowering) which represent really weird target-specific gcc builtins used inside unwinder. After corresponding llvm-gcc patch will land (easy) exceptions should be more or less workable. However, exceptions handling support should not be thought as 'finished': I expect many small and not so small glitches everywhere. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@39855 91177308-0d34-0410-b5e6-96231b3b80d8 Anton Korobeynikov 12 years ago
25 changed file(s) with 258 addition(s) and 36 deletion(s). Raw diff Collapse all Expand all
10291029 // Personalities - Vector of all personality functions ever seen. Used to emit
10301030 // common EH frames.
10311031 std::vector Personalities;
1032
1033 bool CallsEHReturn;
1034 bool CallsUnwindInit;
10321035 public:
10331036 static char ID; // Pass identification, replacement for typeid
10341037
10711074 /// needsFrameInfo - Returns true if we need to gather callee-saved register
10721075 /// move info for the frame.
10731076 bool needsFrameInfo() const;
1077
1078 bool callsEHReturn() const { return CallsEHReturn; }
1079 void setCallsEHReturn(bool b) { CallsEHReturn = b; }
1080
1081 bool callsUnwindInit() const { return CallsUnwindInit; }
1082 void setCallsUnwindInit(bool b) { CallsUnwindInit = b; }
10741083
10751084 /// NextLabelID - Return the next unique label id.
10761085 ///
109109 // to the current function's frame or return address, an index of one to the
110110 // parent's frame or return address, and so on.
111111 FRAMEADDR, RETURNADDR,
112
113 // FRAME_TO_ARGS_OFFSET - This node represents offset from frame pointer to
114 // first (possible) on-stack argument. This is needed for correct stack
115 // adjustment during unwind.
116 FRAME_TO_ARGS_OFFSET,
112117
113118 // RESULT, OUTCHAIN = EXCEPTIONADDR(INCHAIN) - This node represents the
114119 // address of the exception block on entry to an landing pad block.
117122 // RESULT, OUTCHAIN = EHSELECTION(INCHAIN, EXCEPTION) - This node represents
118123 // the selection index of the exception thrown.
119124 EHSELECTION,
125
126 // OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER) - This node represents
127 // 'eh_return' gcc dwarf builtin, which is used to return from
128 // exception. The general meaning is: adjust stack by OFFSET and pass
129 // execution to HANDLER. Many platform-related details also :)
130 EH_RETURN,
120131
121132 // TargetConstant* - Like Constant*, but the DAG does not do any folding or
122133 // simplification of the constant.
232232 llvm_vararg_ty]>;
233233 def int_eh_typeid_for : Intrinsic<[llvm_i32_ty, llvm_ptr_ty]>;
234234
235 def int_eh_return : Intrinsic<[llvm_void_ty, llvm_i32_ty, llvm_ptr_ty]>,
236 GCCBuiltin<"__builtin_eh_return">;
237
238 def int_eh_unwind_init: Intrinsic<[llvm_void_ty]>,
239 GCCBuiltin<"__builtin_unwind_init">;
240
241 def int_eh_dwarf_cfa : Intrinsic<[llvm_ptr_ty, llvm_i32_ty]>;
242
235243 //===---------------- Generic Variable Attribute Intrinsics----------------===//
236244 //
237245 def int_var_annotation : Intrinsic<[llvm_void_ty, llvm_ptr_ty, llvm_ptr_ty,
395395 /// callee saved registers on this target. The register should be in the
396396 /// order of desired callee-save stack frame offset. The first register is
397397 /// closed to the incoming stack pointer if stack grows down, and vice versa.
398 virtual const unsigned* getCalleeSavedRegs() const = 0;
398 virtual const unsigned* getCalleeSavedRegs(const MachineFunction *MF = 0)
399 const = 0;
399400
400401 /// getCalleeSavedRegClasses - Return a null-terminated list of the preferred
401402 /// register classes to spill each callee saved register with. The order and
402403 /// length of this list match the getCalleeSaveRegs() list.
403 virtual const TargetRegisterClass* const *getCalleeSavedRegClasses() const =0;
404 virtual const TargetRegisterClass* const *getCalleeSavedRegClasses(
405 const MachineFunction *MF) const =0;
404406
405407 /// getReservedRegs - Returns a bitset indexed by physical register number
406408 /// indicating if a register is a special register that has particular uses and
14751475 , FrameMoves()
14761476 , LandingPads()
14771477 , Personalities()
1478 , CallsEHReturn(0)
1479 , CallsUnwindInit(0)
14781480 {
14791481 // Always emit "no personality" info
14801482 Personalities.push_back(NULL);
15221524 TypeInfos.clear();
15231525 FilterIds.clear();
15241526 FilterEnds.clear();
1527 CallsEHReturn = 0;
1528 CallsUnwindInit = 0;
15251529 }
15261530
15271531 /// getDescFor - Convert a Value to a debug information descriptor.
120120 const TargetFrameInfo *TFI = Fn.getTarget().getFrameInfo();
121121
122122 // Get the callee saved register list...
123 const unsigned *CSRegs = RegInfo->getCalleeSavedRegs();
123 const unsigned *CSRegs = RegInfo->getCalleeSavedRegs(&Fn);
124124
125125 // Get the function call frame set-up and tear-down instruction opcode
126126 int FrameSetupOpcode = RegInfo->getCallFrameSetupOpcode();
169169 // function, thus needing to be saved and restored in the prolog/epilog.
170170 //
171171 const TargetRegisterClass* const *CSRegClasses =
172 RegInfo->getCalleeSavedRegClasses();
172 RegInfo->getCalleeSavedRegClasses(&Fn);
173173 std::vector CSI;
174174 for (unsigned i = 0; CSRegs[i]; ++i) {
175175 unsigned Reg = CSRegs[i];
639639 break;
640640 case ISD::FRAMEADDR:
641641 case ISD::RETURNADDR:
642 case ISD::FRAME_TO_ARGS_OFFSET:
642643 // The only option for these nodes is to custom lower them. If the target
643644 // does not custom lower them, then return zero.
644645 Tmp1 = TLI.LowerOperation(Op, DAG);
692693 break;
693694 }
694695 }
696 }
697 break;
698 case ISD::EH_RETURN:
699 MVT::ValueType VT = Node->getValueType(0);
700 // The only "good" option for this node is to custom lower it.
701 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
702 default: assert(0 && "This action is not supported at all!");
703 case TargetLowering::Custom:
704 Result = TLI.LowerOperation(Op, DAG);
705 if (Result.Val) break;
706 // Fall Thru
707 case TargetLowering::Legal:
708 // Target does not know, how to lower this, lower to noop
709 Result = LegalizeOp(Node->getOperand(0));
710 break;
695711 }
696712 break;
697713 case ISD::AssertSext:
33683368 case ISD::GLOBAL_OFFSET_TABLE: return "GLOBAL_OFFSET_TABLE";
33693369 case ISD::RETURNADDR: return "RETURNADDR";
33703370 case ISD::FRAMEADDR: return "FRAMEADDR";
3371 case ISD::FRAME_TO_ARGS_OFFSET: return "FRAME_TO_ARGS_OFFSET";
33713372 case ISD::EXCEPTIONADDR: return "EXCEPTIONADDR";
33723373 case ISD::EHSELECTION: return "EHSELECTION";
3374 case ISD::EH_RETURN: return "EH_RETURN";
33733375 case ISD::ConstantPool: return "ConstantPool";
33743376 case ISD::ExternalSymbol: return "ExternalSymbol";
33753377 case ISD::INTRINSIC_WO_CHAIN: {
27182718 }
27192719
27202720 return 0;
2721 }
2722
2723 case Intrinsic::eh_return: {
2724 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2725
2726 if (MMI && ExceptionHandling) {
2727 MMI->setCallsEHReturn(true);
2728 DAG.setRoot(DAG.getNode(ISD::EH_RETURN,
2729 MVT::Other,
2730 getRoot(),
2731 getValue(I.getOperand(1)),
2732 getValue(I.getOperand(2))));
2733 } else {
2734 setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
2735 }
2736
2737 return 0;
2738 }
2739
2740 case Intrinsic::eh_unwind_init: {
2741 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) {
2742 MMI->setCallsUnwindInit(true);
2743 }
2744
2745 return 0;
2746 }
2747
2748 case Intrinsic::eh_dwarf_cfa: {
2749 if (ExceptionHandling) {
2750 MVT::ValueType VT = getValue(I.getOperand(1)).getValueType();
2751 SDOperand Offset = DAG.getNode(ISD::ADD,
2752 TLI.getPointerTy(),
2753 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET,
2754 VT),
2755 getValue(I.getOperand(1)));
2756 setValue(&I, DAG.getNode(ISD::ADD,
2757 TLI.getPointerTy(),
2758 DAG.getNode(ISD::FRAMEADDR,
2759 TLI.getPointerTy(),
2760 DAG.getConstant(0,
2761 TLI.getPointerTy())),
2762 Offset));
2763 } else {
2764 setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
2765 }
2766
2767 return 0;
27212768 }
27222769
27232770 case Intrinsic::sqrt_f32:
326326 return NewMI;
327327 }
328328
329 const unsigned* ARMRegisterInfo::getCalleeSavedRegs() const {
329 const unsigned* ARMRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
330 const {
330331 static const unsigned CalleeSavedRegs[] = {
331332 ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8,
332333 ARM::R7, ARM::R6, ARM::R5, ARM::R4,
348349 }
349350
350351 const TargetRegisterClass* const *
351 ARMRegisterInfo::getCalleeSavedRegClasses() const {
352 ARMRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
352353 static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
353354 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
354355 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
6565 MachineInstr* foldMemoryOperand(MachineInstr* MI, unsigned OpNum,
6666 int FrameIndex) const;
6767
68 const unsigned *getCalleeSavedRegs() const;
68 const unsigned *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
6969
70 const TargetRegisterClass* const* getCalleeSavedRegClasses() const;
70 const TargetRegisterClass* const* getCalleeSavedRegClasses(
71 const MachineFunction *MF = 0) const;
7172
7273 BitVector getReservedRegs(const MachineFunction &MF) const;
7374
163163 MBB.insert(I, MI);
164164 }
165165
166 const unsigned* AlphaRegisterInfo::getCalleeSavedRegs() const {
166 const unsigned* AlphaRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
167 const {
167168 static const unsigned CalleeSavedRegs[] = {
168169 Alpha::R9, Alpha::R10,
169170 Alpha::R11, Alpha::R12,
177178 }
178179
179180 const TargetRegisterClass* const*
180 AlphaRegisterInfo::getCalleeSavedRegClasses() const {
181 AlphaRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
181182 static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
182183 &Alpha::GPRCRegClass, &Alpha::GPRCRegClass,
183184 &Alpha::GPRCRegClass, &Alpha::GPRCRegClass,
4747 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
4848 unsigned DestReg, const MachineInstr *Orig) const;
4949
50 const unsigned *getCalleeSavedRegs() const;
50 const unsigned *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
5151
52 const TargetRegisterClass* const* getCalleeSavedRegClasses() const;
52 const TargetRegisterClass* const* getCalleeSavedRegClasses(
53 const MachineFunction *MF = 0) const;
5354
5455 BitVector getReservedRegs(const MachineFunction &MF) const;
5556
101101 MBB.insert(I, MI);
102102 }
103103
104 const unsigned* IA64RegisterInfo::getCalleeSavedRegs() const {
104 const unsigned* IA64RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
105 const {
105106 static const unsigned CalleeSavedRegs[] = {
106107 IA64::r5, 0
107108 };
109110 }
110111
111112 const TargetRegisterClass* const*
112 IA64RegisterInfo::getCalleeSavedRegClasses() const {
113 IA64RegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
113114 static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
114115 &IA64::GRRegClass, 0
115116 };
4646 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
4747 unsigned DestReg, const MachineInstr *Orig) const;
4848
49 const unsigned *getCalleeSavedRegs() const;
49 const unsigned *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
5050
51 const TargetRegisterClass* const* getCalleeSavedRegClasses() const;
51 const TargetRegisterClass* const* getCalleeSavedRegClasses(
52 const MachineFunction *MF = 0) const;
5253
5354 BitVector getReservedRegs(const MachineFunction &MF) const;
5455
247247 MBB.insert(I, MI);
248248 }
249249
250 const unsigned* PPCRegisterInfo::getCalleeSavedRegs() const {
250 const unsigned* PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
251 const {
251252 // 32-bit Darwin calling convention.
252253 static const unsigned Macho32_CalleeSavedRegs[] = {
253254 PPC::R13, PPC::R14, PPC::R15,
323324 }
324325
325326 const TargetRegisterClass* const*
326 PPCRegisterInfo::getCalleeSavedRegClasses() const {
327 PPCRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
327328 // 32-bit Macho calling convention.
328329 static const TargetRegisterClass * const Macho32_CalleeSavedRegClasses[] = {
329330 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
5656 virtual MachineInstr* foldMemoryOperand(MachineInstr* MI, unsigned OpNum,
5757 int FrameIndex) const;
5858
59 const unsigned *getCalleeSavedRegs() const;
59 const unsigned *getCalleeSavedRegs(const MachineFunction* MF = 0) const;
6060
61 const TargetRegisterClass* const* getCalleeSavedRegClasses() const;
61 const TargetRegisterClass* const* getCalleeSavedRegClasses(
62 const MachineFunction *MF = 0) const;
6263
6364 BitVector getReservedRegs(const MachineFunction &MF) const;
6465
120120 return NewMI;
121121 }
122122
123 const unsigned* SparcRegisterInfo::getCalleeSavedRegs() const {
123 const unsigned* SparcRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
124 const {
124125 static const unsigned CalleeSavedRegs[] = { 0 };
125126 return CalleeSavedRegs;
126127 }
142143
143144
144145 const TargetRegisterClass* const*
145 SparcRegisterInfo::getCalleeSavedRegClasses() const {
146 SparcRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
146147 static const TargetRegisterClass * const CalleeSavedRegClasses[] = { 0 };
147148 return CalleeSavedRegClasses;
148149 }
5050 unsigned OpNum,
5151 int FrameIndex) const;
5252
53 const unsigned *getCalleeSavedRegs() const;
53 const unsigned *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
5454
55 const TargetRegisterClass* const* getCalleeSavedRegClasses() const;
55 const TargetRegisterClass* const* getCalleeSavedRegClasses(
56 const MachineFunction *MF = 0) const;
5657
5758 BitVector getReservedRegs(const MachineFunction &MF) const;
5859
4141 X86ScalarSSE = Subtarget->hasSSE2();
4242 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
4343
44 RegInfo = TM.getRegisterInfo();
45
4446 // Set up the TargetLowering object.
4547
4648 // X86 is weird, it always uses i8 for shift amounts and setcc results.
196198 }
197199 // X86 ret instruction may pop stack.
198200 setOperationAction(ISD::RET , MVT::Other, Custom);
201 if (!Subtarget->is64Bit())
202 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
203
199204 // Darwin ABI issue.
200205 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
201206 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
42254230 DAG.getConstant(4, getPointerTy()));
42264231 }
42274232
4233 SDOperand X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDOperand Op,
4234 SelectionDAG &DAG) {
4235 // Is not yet supported on x86-64
4236 if (Subtarget->is64Bit())
4237 return SDOperand();
4238
4239 return DAG.getConstant(8, getPointerTy());
4240 }
4241
4242 SDOperand X86TargetLowering::LowerEH_RETURN(SDOperand Op, SelectionDAG &DAG)
4243 {
4244 assert(!Subtarget->is64Bit() &&
4245 "Lowering of eh_return builtin is not supported yet on x86-64");
4246
4247 MachineFunction &MF = DAG.getMachineFunction();
4248 SDOperand Chain = Op.getOperand(0);
4249 SDOperand Offset = Op.getOperand(1);
4250 SDOperand Handler = Op.getOperand(2);
4251
4252 SDOperand Frame = DAG.getRegister(RegInfo->getFrameRegister(MF),
4253 getPointerTy());
4254
4255 SDOperand StoreAddr = DAG.getNode(ISD::SUB, getPointerTy(), Frame,
4256 DAG.getConstant(-4UL, getPointerTy()));
4257 StoreAddr = DAG.getNode(ISD::ADD, getPointerTy(), StoreAddr, Offset);
4258 Chain = DAG.getStore(Chain, Handler, StoreAddr, NULL, 0);
4259 Chain = DAG.getCopyToReg(Chain, X86::ECX, StoreAddr);
4260 MF.addLiveOut(X86::ECX);
4261
4262 return DAG.getNode(X86ISD::EH_RETURN, MVT::Other,
4263 Chain, DAG.getRegister(X86::ECX, getPointerTy()));
4264 }
4265
42284266 /// LowerOperation - Provide custom lowering hooks for some operations.
42294267 ///
42304268 SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
42624300 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
42634301 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
42644302 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
4303 case ISD::FRAME_TO_ARGS_OFFSET:
4304 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
42654305 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
4306 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
42664307 }
42674308 return SDOperand();
42684309 }
43104351 case X86ISD::FRCP: return "X86ISD::FRCP";
43114352 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
43124353 case X86ISD::THREAD_POINTER: return "X86ISD::THREAD_POINTER";
4354 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
43134355 }
43144356 }
43154357
1515 #define X86ISELLOWERING_H
1616
1717 #include "X86Subtarget.h"
18 #include "X86RegisterInfo.h"
1819 #include "llvm/Target/TargetLowering.h"
1920 #include "llvm/CodeGen/SelectionDAG.h"
2021
183184 FRSQRT, FRCP,
184185
185186 // Thread Local Storage
186 TLSADDR, THREAD_POINTER
187 TLSADDR, THREAD_POINTER,
188
189 // Exception Handling helpers
190 EH_RETURN
187191 };
188192 }
189193
369373 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
370374 /// make the right decision when generating code for different targets.
371375 const X86Subtarget *Subtarget;
376 const MRegisterInfo *RegInfo;
372377
373378 /// X86StackPtr - X86 physical register used as stack ptr.
374379 unsigned X86StackPtr;
423428 SDOperand LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG);
424429 SDOperand LowerRETURNADDR(SDOperand Op, SelectionDAG &DAG);
425430 SDOperand LowerFRAMEADDR(SDOperand Op, SelectionDAG &DAG);
431 SDOperand LowerFRAME_TO_ARGS_OFFSET(SDOperand Op, SelectionDAG &DAG);
432 SDOperand LowerEH_RETURN(SDOperand Op, SelectionDAG &DAG);
426433 };
427434 }
428435
5050
5151 def SDT_X86TLSTP : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
5252
53 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
54
5355 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
5456 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
5557
9395 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
9496 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
9597 def X86TLStp : SDNode<"X86ISD::THREAD_POINTER", SDT_X86TLSTP, []>;
98
99 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
100 [SDNPHasChain]>;
96101
97102
98103 //===----------------------------------------------------------------------===//
24912496 (i32 imm:$file))]>;
24922497
24932498 //===----------------------------------------------------------------------===//
2499 // EH Pseudo Instructions
2500 //
2501 let isTerminator = 1, isReturn = 1, isBarrier = 1,
2502 hasCtrlDep = 1, noResults = 1 in {
2503 def EH_RETURN : I<0xC3, RawFrm, (ops GR32:$addr),
2504 "ret #eh_return, addr: $addr",
2505 [(X86ehret GR32:$addr)]>;
2506
2507 }
2508
2509 //===----------------------------------------------------------------------===//
24942510 // Non-Instruction Patterns
24952511 //===----------------------------------------------------------------------===//
24962512
902902 }
903903
904904
905 const unsigned *X86RegisterInfo::getCalleeSavedRegs() const {
905 const unsigned *X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
906 const {
906907 static const unsigned CalleeSavedRegs32Bit[] = {
907908 X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
908909 };
910
911 static const unsigned CalleeSavedRegs32EHRet[] = {
912 X86::EAX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
913 };
914
909915 static const unsigned CalleeSavedRegs64Bit[] = {
910916 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
911917 };
912918
913 return Is64Bit ? CalleeSavedRegs64Bit : CalleeSavedRegs32Bit;
919 if (Is64Bit)
920 return CalleeSavedRegs64Bit;
921 else {
922 if (MF) {
923 MachineFrameInfo *MFI = MF->getFrameInfo();
924 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
925 if (MMI && MMI->callsEHReturn())
926 return CalleeSavedRegs32EHRet;
927 }
928 return CalleeSavedRegs32Bit;
929 }
914930 }
915931
916932 const TargetRegisterClass* const*
917 X86RegisterInfo::getCalleeSavedRegClasses() const {
933 X86RegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
918934 static const TargetRegisterClass * const CalleeSavedRegClasses32Bit[] = {
935 &X86::GR32RegClass, &X86::GR32RegClass,
936 &X86::GR32RegClass, &X86::GR32RegClass, 0
937 };
938 static const TargetRegisterClass * const CalleeSavedRegClasses32EHRet[] = {
939 &X86::GR32RegClass, &X86::GR32RegClass,
919940 &X86::GR32RegClass, &X86::GR32RegClass,
920941 &X86::GR32RegClass, &X86::GR32RegClass, 0
921942 };
925946 &X86::GR64RegClass, &X86::GR64RegClass, 0
926947 };
927948
928 return Is64Bit ? CalleeSavedRegClasses64Bit : CalleeSavedRegClasses32Bit;
949 if (Is64Bit)
950 return CalleeSavedRegClasses64Bit;
951 else {
952 if (MF) {
953 MachineFrameInfo *MFI = MF->getFrameInfo();
954 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
955 if (MMI && MMI->callsEHReturn())
956 return CalleeSavedRegClasses32EHRet;
957 }
958 return CalleeSavedRegClasses32Bit;
959 }
960
929961 }
930962
931963 BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
952984 // if frame pointer elimination is disabled.
953985 //
954986 bool X86RegisterInfo::hasFP(const MachineFunction &MF) const {
987 MachineFrameInfo *MFI = MF.getFrameInfo();
988 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
989
955990 return (NoFramePointerElim ||
956991 MF.getFrameInfo()->hasVarSizedObjects() ||
957 MF.getInfo()->getForceFramePointer());
992 MF.getInfo()->getForceFramePointer() ||
993 (MMI && MMI->callsUnwindInit()));
958994 }
959995
960996 void X86RegisterInfo::
12421278 MachineBasicBlock &MBB) const {
12431279 const MachineFrameInfo *MFI = MF.getFrameInfo();
12441280 MachineBasicBlock::iterator MBBI = prior(MBB.end());
1245
1246 switch (MBBI->getOpcode()) {
1281 unsigned RetOpcode = MBBI->getOpcode();
1282
1283 switch (RetOpcode) {
12471284 case X86::RET:
12481285 case X86::RETI:
1286 case X86::EH_RETURN:
12491287 case X86::TAILJMPd:
12501288 case X86::TAILJMPr:
12511289 case X86::TAILJMPm: break; // These are ok
12861324 if (NumBytes)
12871325 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
12881326 }
1327 }
1328
1329 // We're returning from function via eh_return.
1330 if (RetOpcode == X86::EH_RETURN) {
1331 MachineOperand &DestAddr = MBBI->getOperand(0);
1332 assert(DestAddr.isReg() && "Offset should be in register!");
1333 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),StackPtr).
1334 addReg(DestAddr.getReg());
12891335 }
12901336 }
12911337
7373
7474 /// getCalleeSavedRegs - Return a null-terminated list of all of the
7575 /// callee-save registers on this target.
76 const unsigned *getCalleeSavedRegs() const;
76 const unsigned *getCalleeSavedRegs(const MachineFunction* MF = 0) const;
7777
7878 /// getCalleeSavedRegClasses - Return a null-terminated list of the preferred
7979 /// register classes to spill each callee-saved register with. The order and
8080 /// length of this list match the getCalleeSavedRegs() list.
81 const TargetRegisterClass* const* getCalleeSavedRegClasses() const;
81 const TargetRegisterClass* const* getCalleeSavedRegClasses(
82 const MachineFunction *MF = 0) const;
8283
8384 /// getReservedRegs - Returns a bitset indexed by physical register number
8485 /// indicating if a register is a special register that has particular uses and
123123 DwarfARangesSection = "\t.section\t.debug_aranges,\"\",@progbits";
124124 DwarfRangesSection = "\t.section\t.debug_ranges,\"\",@progbits";
125125 DwarfMacInfoSection = "\t.section\t.debug_macinfo,\"\",@progbits";
126
127 SupportsExceptionHandling = true;
126
127 if (!Subtarget->is64Bit())
128 SupportsExceptionHandling = true;
128129 DwarfEHFrameSection = "\t.section\t.eh_frame,\"aw\",@progbits";
129130 DwarfExceptionSection = "\t.section\t.gcc_except_table,\"a\",@progbits";
130131 break;