llvm.org GIT mirror llvm / 234b36e
[CodeGen] Move printing MO_IntrinsicID operands to MachineOperand::print Work towards the unification of MIR and debug output by refactoring the interfaces. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321112 91177308-0d34-0410-b5e6-96231b3b80d8 Francis Visoiu Mistrih 2 years ago
4 changed file(s) with 33 addition(s) and 9 deletion(s). Raw diff Collapse all Expand all
722722 .. code-block:: text
723723
724724 %x0 = COPY intrinsic(@llvm.returnaddress)
725
726 Predicate Operands
727 ^^^^^^^^^^^^^^^^^^
728
729 A Predicate operand contains an IR predicate from ``CmpInst::Predicate``, like
730 ``ICMP_EQ``, etc.
731
732 For an int eq predicate ``ICMP_EQ``, the syntax is:
733
734 .. code-block:: text
735
736 %2:gpr(s32) = G_ICMP intpred(eq), %0, %1
725737
726738 .. TODO: Describe the parsers default behaviour when optional YAML attributes
727739 are missing.
784784 case MachineOperand::MO_Metadata:
785785 case MachineOperand::MO_MCSymbol:
786786 case MachineOperand::MO_CFIIndex:
787 case MachineOperand::MO_IntrinsicID: {
787 case MachineOperand::MO_IntrinsicID:
788 case MachineOperand::MO_Predicate: {
788789 unsigned TiedOperandIdx = 0;
789790 if (ShouldPrintRegisterTies && Op.isReg() && Op.isTied() && !Op.isDef())
790791 TiedOperandIdx = Op.getParent()->findTiedOperandIdx(OpIdx);
811812 OS << StringRef(TRI->getRegMaskNames()[RegMaskInfo->second]).lower();
812813 else
813814 printCustomRegMask(Op.getRegMask(), OS, TRI);
814 break;
815 }
816 case MachineOperand::MO_Predicate: {
817 auto Pred = static_cast(Op.getPredicate());
818 OS << (CmpInst::isIntPredicate(Pred) ? "int" : "float") << "pred("
819 << CmpInst::getPredicateName(Pred) << ')';
820815 break;
821816 }
822817 }
806806 }
807807 case MachineOperand::MO_Predicate: {
808808 auto Pred = static_cast(getPredicate());
809 OS << '<' << (CmpInst::isIntPredicate(Pred) ? "intpred" : "floatpred")
810 << CmpInst::getPredicateName(Pred) << '>';
809 OS << (CmpInst::isIntPredicate(Pred) ? "int" : "float") << "pred("
810 << CmpInst::getPredicateName(Pred) << ')';
811811 break;
812812 }
813813 }
99 #include "llvm/CodeGen/MachineOperand.h"
1010 #include "llvm/ADT/ilist_node.h"
1111 #include "llvm/IR/Constants.h"
12 #include "llvm/IR/InstrTypes.h"
1213 #include "llvm/IR/LLVMContext.h"
1314 #include "llvm/IR/Module.h"
1415 #include "llvm/IR/ModuleSlotTracker.h"
381382 }
382383 }
383384
385 TEST(MachineOperandTest, PrintPredicate) {
386 // Create a MachineOperand with a generic intrinsic ID.
387 MachineOperand MO = MachineOperand::CreatePredicate(CmpInst::ICMP_EQ);
388
389 // Checking some preconditions on the newly created
390 // MachineOperand.
391 ASSERT_TRUE(MO.isPredicate());
392 ASSERT_TRUE(MO.getPredicate() == CmpInst::ICMP_EQ);
393
394 std::string str;
395 // Print a MachineOperand containing a int predicate ICMP_EQ.
396 raw_string_ostream OS(str);
397 MO.print(OS, /*TRI=*/nullptr, /*IntrinsicInfo=*/nullptr);
398 ASSERT_TRUE(OS.str() == "intpred(eq)");
399 }
400
384401 } // end namespace