llvm.org GIT mirror llvm / 2348232
Add annotations to tablegen-generated processor itineraries, or replace them with something meaningful. I want to be able to read and debug the generated tables. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128703 91177308-0d34-0410-b5e6-96231b3b80d8 Andrew Trick 9 years ago
2 changed file(s) with 21 addition(s) and 16 deletion(s). Raw diff Collapse all Expand all
341341 BypassTable += " 0, // No itinerary\n";
342342
343343 unsigned StageCount = 1, OperandCycleCount = 1;
344 unsigned ItinStageEnum = 1, ItinOperandCycleEnum = 1;
345344 std::map ItinStageMap, ItinOperandMap;
346345 for (unsigned i = 0, N = ProcItinList.size(); i < N; i++) {
347346 // Next record
385384 if (NStages > 0) {
386385 FindStage = ItinStageMap[ItinStageString];
387386 if (FindStage == 0) {
388 // Emit as { cycles, u1 | u2 | ... | un, timeinc }, // index
389 StageTable += ItinStageString + ", // " + itostr(ItinStageEnum) + "\n";
387 // Emit as { cycles, u1 | u2 | ... | un, timeinc }, // indices
388 StageTable += ItinStageString + ", // " + itostr(StageCount);
389 if (NStages > 1)
390 StageTable += "-" + itostr(StageCount + NStages - 1);
391 StageTable += "\n";
390392 // Record Itin class number.
391393 ItinStageMap[ItinStageString] = FindStage = StageCount;
392394 StageCount += NStages;
393 ItinStageEnum++;
394395 }
395396 }
396397
401402 FindOperandCycle = ItinOperandMap[ItinOperandString];
402403 if (FindOperandCycle == 0) {
403404 // Emit as cycle, // index
404 OperandCycleTable += ItinOperandCycleString + ", // " +
405 itostr(ItinOperandCycleEnum) + "\n";
405 OperandCycleTable += ItinOperandCycleString + ", // ";
406 std::string OperandIdxComment = itostr(OperandCycleCount);
407 if (NOperandCycles > 1)
408 OperandIdxComment += "-"
409 + itostr(OperandCycleCount + NOperandCycles - 1);
410 OperandCycleTable += OperandIdxComment + "\n";
406411 // Record Itin class number.
407412 ItinOperandMap[ItinOperandCycleString] =
408413 FindOperandCycle = OperandCycleCount;
409
410414 // Emit as bypass, // index
411 BypassTable += ItinBypassString + ", // " +
412 itostr(ItinOperandCycleEnum) + "\n";
413
415 BypassTable += ItinBypassString + ", // " + OperandIdxComment + "\n";
414416 OperandCycleCount += NOperandCycles;
415 ItinOperandCycleEnum++;
416417 }
417418 }
418419
460461 //
461462 // EmitProcessorData - Generate data for processor itineraries.
462463 //
463 void SubtargetEmitter::EmitProcessorData(raw_ostream &OS,
464 std::vector > &ProcList) {
464 void SubtargetEmitter::
465 EmitProcessorData(raw_ostream &OS,
466 std::vector &ItinClassList,
467 std::vector > &ProcList) {
465468 // Get an iterator for processor itinerary stages
466469 std::vector >::iterator
467470 ProcListIter = ProcList.begin();
485488
486489 // For each itinerary class
487490 std::vector &ItinList = *ProcListIter++;
491 assert(ItinList.size() == ItinClassList.size() && "bad itinerary");
488492 for (unsigned j = 0, M = ItinList.size(); j < M; ++j) {
489493 InstrItinerary &Intinerary = ItinList[j];
490494
501505 Intinerary.LastOperandCycle << " }";
502506 }
503507
504 OS << ", // " << j << "\n";
508 OS << ", // " << j << " " << ItinClassList[j]->getName() << "\n";
505509 }
506510
507511 // End processor itinerary table
578582 EmitStageAndOperandCycleData(OS, NItinClasses, ItinClassesMap,
579583 ItinClassList, ProcList);
580584 // Emit the processor itinerary data
581 EmitProcessorData(OS, ProcList);
585 EmitProcessorData(OS, ItinClassList, ProcList);
582586 // Emit the processor lookup data
583587 EmitProcessorLookup(OS);
584588 }
4747 std::vector &ItinClassList,
4848 std::vector > &ProcList);
4949 void EmitProcessorData(raw_ostream &OS,
50 std::vector > &ProcList);
50 std::vector &ItinClassList,
51 std::vector > &ProcList);
5152 void EmitProcessorLookup(raw_ostream &OS);
5253 void EmitData(raw_ostream &OS);
5354 void ParseFeaturesFunction(raw_ostream &OS);