llvm.org GIT mirror llvm / 2343955
Merging r367124, r367292, r367394, r367396, and r367398. ------------------------------------------------------------------------ r367124 | c-rhodes | 2019-07-26 17:57:50 +0200 (Fri, 26 Jul 2019) | 14 lines [AArch64][SVE2] Rename bitperm feature to sve2-bitperm Summary: The bitperm feature flag is now prefixed with SVE2, as it is for all other SVE2 extensions Patch by Maciej Gabka. Reviewers: sdesmalen, rovka, chill, SjoerdMeijer, rengolin Reviewed By: SjoerdMeijer, rengolin Differential Revision: https://reviews.llvm.org/D65327 ------------------------------------------------------------------------ ------------------------------------------------------------------------ r367292 | c-rhodes | 2019-07-30 09:47:48 +0200 (Tue, 30 Jul 2019) | 10 lines [AArch64][AsmParser] Remove SVE and SVE2 from ARMTargetParser Summary: Patch removes SVE and SVE2 features from ARMTargetParser as these features are not supported on ARM. Reviewed By: rengolin Differential Revision: https://reviews.llvm.org/D65385 ------------------------------------------------------------------------ ------------------------------------------------------------------------ r367394 | c-rhodes | 2019-07-31 10:45:57 +0200 (Wed, 31 Jul 2019) | 25 lines [AArch64][SVE2] Use destination register as source register Summary: This patch fixes a bug in the following instructions that should have been implemented as destructive. A destructive instruction is an instruction where one of the source registers also acts as the destination register. Therefore, the contents of the source register, when the instruction begins execution, are replaced by the result of the instruction when the instruction completes execution [1]: * SRI/SLI * EORBT/EORTB * TBX * Narrowing top instructions * FP convert precision instructions These changes are non-functional from the assembler/diassembler point-of-view but are necessary for correct codegen. [1] https://static.docs.arm.com/ddi0584/ae/DDI0584A_e_SVE_supp_armv8A.pdf Reviewed By: sdesmalen Differential Revision: https://reviews.llvm.org/D65389 ------------------------------------------------------------------------ ------------------------------------------------------------------------ r367396 | c-rhodes | 2019-07-31 10:58:16 +0200 (Wed, 31 Jul 2019) | 15 lines [AArch64][SVE2] Minor refactoring and cleanup Summary: * Clarify comment with SVE2 for predicated shifts and move next to other shift instructions. * Clarify comments for various instructions. * Move FCVTX instruction next to other fp conversions. * Move FLOGB to next to other fp instructions and fix description. * Remove "cons" from non-constructive multiclass for bitwise shift-right and accumulate instructions. Reviewed By: sdesmalen Differential Revision: https://reviews.llvm.org/D65390 ------------------------------------------------------------------------ ------------------------------------------------------------------------ r367398 | c-rhodes | 2019-07-31 11:10:36 +0200 (Wed, 31 Jul 2019) | 14 lines [AArch64][SVE2] Load/store instruction fixes Summary: * Loads and stores in SVE2 are gather/scatter not contiguous, fixed by renaming multiclasses to reflect this and also updated comments. * Remove aliases from load/store multiclasses that reflect the behaviour of the original form. * Fix bug in scatter store implementation, vector list should be used as input, not output. Reviewed By: sdesmalen Differential Revision: https://reviews.llvm.org/D65392 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_90@367434 91177308-0d34-0410-b5e6-96231b3b80d8 Hans Wennborg 2 months ago
22 changed file(s) with 354 addition(s) and 245 deletion(s). Raw diff Collapse all Expand all
4949 #define AARCH64_ARCH_EXT_NAME(NAME, ID, FEATURE, NEGFEATURE)
5050 #endif
5151 // FIXME: This would be nicer were it tablegen
52 AARCH64_ARCH_EXT_NAME("invalid", AArch64::AEK_INVALID, nullptr, nullptr)
53 AARCH64_ARCH_EXT_NAME("none", AArch64::AEK_NONE, nullptr, nullptr)
54 AARCH64_ARCH_EXT_NAME("crc", AArch64::AEK_CRC, "+crc", "-crc")
55 AARCH64_ARCH_EXT_NAME("lse", AArch64::AEK_LSE, "+lse", "-lse")
56 AARCH64_ARCH_EXT_NAME("rdm", AArch64::AEK_RDM, "+rdm", "-rdm")
57 AARCH64_ARCH_EXT_NAME("crypto", AArch64::AEK_CRYPTO, "+crypto","-crypto")
58 AARCH64_ARCH_EXT_NAME("sm4", AArch64::AEK_SM4, "+sm4", "-sm4")
59 AARCH64_ARCH_EXT_NAME("sha3", AArch64::AEK_SHA3, "+sha3", "-sha3")
60 AARCH64_ARCH_EXT_NAME("sha2", AArch64::AEK_SHA2, "+sha2", "-sha2")
61 AARCH64_ARCH_EXT_NAME("aes", AArch64::AEK_AES, "+aes", "-aes")
62 AARCH64_ARCH_EXT_NAME("dotprod", AArch64::AEK_DOTPROD, "+dotprod","-dotprod")
63 AARCH64_ARCH_EXT_NAME("fp", AArch64::AEK_FP, "+fp-armv8", "-fp-armv8")
64 AARCH64_ARCH_EXT_NAME("simd", AArch64::AEK_SIMD, "+neon", "-neon")
65 AARCH64_ARCH_EXT_NAME("fp16", AArch64::AEK_FP16, "+fullfp16", "-fullfp16")
66 AARCH64_ARCH_EXT_NAME("fp16fml", AArch64::AEK_FP16FML, "+fp16fml", "-fp16fml")
67 AARCH64_ARCH_EXT_NAME("profile", AArch64::AEK_PROFILE, "+spe", "-spe")
68 AARCH64_ARCH_EXT_NAME("ras", AArch64::AEK_RAS, "+ras", "-ras")
69 AARCH64_ARCH_EXT_NAME("sve", AArch64::AEK_SVE, "+sve", "-sve")
70 AARCH64_ARCH_EXT_NAME("sve2", AArch64::AEK_SVE2, "+sve2", "-sve2")
71 AARCH64_ARCH_EXT_NAME("sve2-aes", AArch64::AEK_SVE2AES, "+sve2-aes", "-sve2-aes")
72 AARCH64_ARCH_EXT_NAME("sve2-sm4", AArch64::AEK_SVE2SM4, "+sve2-sm4", "-sve2-sm4")
73 AARCH64_ARCH_EXT_NAME("sve2-sha3", AArch64::AEK_SVE2SHA3, "+sve2-sha3", "-sve2-sha3")
74 AARCH64_ARCH_EXT_NAME("bitperm", AArch64::AEK_BITPERM, "+bitperm", "-bitperm")
75 AARCH64_ARCH_EXT_NAME("rcpc", AArch64::AEK_RCPC, "+rcpc", "-rcpc")
76 AARCH64_ARCH_EXT_NAME("rng", AArch64::AEK_RAND, "+rand", "-rand")
77 AARCH64_ARCH_EXT_NAME("memtag", AArch64::AEK_MTE, "+mte", "-mte")
78 AARCH64_ARCH_EXT_NAME("ssbs", AArch64::AEK_SSBS, "+ssbs", "-ssbs")
79 AARCH64_ARCH_EXT_NAME("sb", AArch64::AEK_SB, "+sb", "-sb")
80 AARCH64_ARCH_EXT_NAME("predres", AArch64::AEK_PREDRES, "+predres", "-predres")
52 AARCH64_ARCH_EXT_NAME("invalid", AArch64::AEK_INVALID, nullptr, nullptr)
53 AARCH64_ARCH_EXT_NAME("none", AArch64::AEK_NONE, nullptr, nullptr)
54 AARCH64_ARCH_EXT_NAME("crc", AArch64::AEK_CRC, "+crc", "-crc")
55 AARCH64_ARCH_EXT_NAME("lse", AArch64::AEK_LSE, "+lse", "-lse")
56 AARCH64_ARCH_EXT_NAME("rdm", AArch64::AEK_RDM, "+rdm", "-rdm")
57 AARCH64_ARCH_EXT_NAME("crypto", AArch64::AEK_CRYPTO, "+crypto","-crypto")
58 AARCH64_ARCH_EXT_NAME("sm4", AArch64::AEK_SM4, "+sm4", "-sm4")
59 AARCH64_ARCH_EXT_NAME("sha3", AArch64::AEK_SHA3, "+sha3", "-sha3")
60 AARCH64_ARCH_EXT_NAME("sha2", AArch64::AEK_SHA2, "+sha2", "-sha2")
61 AARCH64_ARCH_EXT_NAME("aes", AArch64::AEK_AES, "+aes", "-aes")
62 AARCH64_ARCH_EXT_NAME("dotprod", AArch64::AEK_DOTPROD, "+dotprod","-dotprod")
63 AARCH64_ARCH_EXT_NAME("fp", AArch64::AEK_FP, "+fp-armv8", "-fp-armv8")
64 AARCH64_ARCH_EXT_NAME("simd", AArch64::AEK_SIMD, "+neon", "-neon")
65 AARCH64_ARCH_EXT_NAME("fp16", AArch64::AEK_FP16, "+fullfp16", "-fullfp16")
66 AARCH64_ARCH_EXT_NAME("fp16fml", AArch64::AEK_FP16FML, "+fp16fml", "-fp16fml")
67 AARCH64_ARCH_EXT_NAME("profile", AArch64::AEK_PROFILE, "+spe", "-spe")
68 AARCH64_ARCH_EXT_NAME("ras", AArch64::AEK_RAS, "+ras", "-ras")
69 AARCH64_ARCH_EXT_NAME("sve", AArch64::AEK_SVE, "+sve", "-sve")
70 AARCH64_ARCH_EXT_NAME("sve2", AArch64::AEK_SVE2, "+sve2", "-sve2")
71 AARCH64_ARCH_EXT_NAME("sve2-aes", AArch64::AEK_SVE2AES, "+sve2-aes", "-sve2-aes")
72 AARCH64_ARCH_EXT_NAME("sve2-sm4", AArch64::AEK_SVE2SM4, "+sve2-sm4", "-sve2-sm4")
73 AARCH64_ARCH_EXT_NAME("sve2-sha3", AArch64::AEK_SVE2SHA3, "+sve2-sha3", "-sve2-sha3")
74 AARCH64_ARCH_EXT_NAME("sve2-bitperm", AArch64::AEK_SVE2BITPERM, "+sve2-bitperm", "-sve2-bitperm")
75 AARCH64_ARCH_EXT_NAME("rcpc", AArch64::AEK_RCPC, "+rcpc", "-rcpc")
76 AARCH64_ARCH_EXT_NAME("rng", AArch64::AEK_RAND, "+rand", "-rand")
77 AARCH64_ARCH_EXT_NAME("memtag", AArch64::AEK_MTE, "+mte", "-mte")
78 AARCH64_ARCH_EXT_NAME("ssbs", AArch64::AEK_SSBS, "+ssbs", "-ssbs")
79 AARCH64_ARCH_EXT_NAME("sb", AArch64::AEK_SB, "+sb", "-sb")
80 AARCH64_ARCH_EXT_NAME("predres", AArch64::AEK_PREDRES, "+predres", "-predres")
8181 #undef AARCH64_ARCH_EXT_NAME
8282
8383 #ifndef AARCH64_CPU_NAME
5252 AEK_SVE2AES = 1 << 24,
5353 AEK_SVE2SM4 = 1 << 25,
5454 AEK_SVE2SHA3 = 1 << 26,
55 AEK_BITPERM = 1 << 27,
55 AEK_SVE2BITPERM = 1 << 27,
5656 };
5757
5858 enum class ArchKind {
3838 AEK_DSP = 1 << 10,
3939 AEK_FP16 = 1 << 11,
4040 AEK_RAS = 1 << 12,
41 AEK_SVE = 1 << 13,
42 AEK_DOTPROD = 1 << 14,
43 AEK_SHA2 = 1 << 15,
44 AEK_AES = 1 << 16,
45 AEK_FP16FML = 1 << 17,
46 AEK_SB = 1 << 18,
47 AEK_SVE2 = 1 << 19,
48 AEK_SVE2AES = 1 << 20,
49 AEK_SVE2SM4 = 1 << 21,
50 AEK_SVE2SHA3 = 1 << 22,
51 AEK_BITPERM = 1 << 23,
52 AEK_FP_DP = 1 << 24,
53 AEK_LOB = 1 << 25,
41 AEK_DOTPROD = 1 << 13,
42 AEK_SHA2 = 1 << 14,
43 AEK_AES = 1 << 15,
44 AEK_FP16FML = 1 << 16,
45 AEK_SB = 1 << 17,
46 AEK_FP_DP = 1 << 18,
47 AEK_LOB = 1 << 19,
5448 // Unsupported extensions.
5549 AEK_OS = 0x8000000,
5650 AEK_IWMMXT = 0x10000000,
9595 Features.push_back("+sve2-sm4");
9696 if (Extensions & AEK_SVE2SHA3)
9797 Features.push_back("+sve2-sha3");
98 if (Extensions & AEK_BITPERM)
99 Features.push_back("+bitperm");
98 if (Extensions & AEK_SVE2BITPERM)
99 Features.push_back("+sve2-bitperm");
100100 if (Extensions & AEK_RCPC)
101101 Features.push_back("+rcpc");
102102
114114 def FeatureSVE2SHA3 : SubtargetFeature<"sve2-sha3", "HasSVE2SHA3", "true",
115115 "Enable SHA3 SVE2 instructions", [FeatureSVE2, FeatureSHA3]>;
116116
117 def FeatureSVE2BitPerm : SubtargetFeature<"bitperm", "HasSVE2BitPerm", "true",
117 def FeatureSVE2BitPerm : SubtargetFeature<"sve2-bitperm", "HasSVE2BitPerm", "true",
118118 "Enable bit permutation SVE2 instructions", [FeatureSVE2]>;
119119
120120 def FeatureZCRegMove : SubtargetFeature<"zcm", "HasZeroCycleRegMove", "true",
115115 def HasSVE2SHA3 : Predicate<"Subtarget->hasSVE2SHA3()">,
116116 AssemblerPredicate<"FeatureSVE2SHA3", "sve2-sha3">;
117117 def HasSVE2BitPerm : Predicate<"Subtarget->hasSVE2BitPerm()">,
118 AssemblerPredicate<"FeatureSVE2BitPerm", "bitperm">;
118 AssemblerPredicate<"FeatureSVE2BitPerm", "sve2-bitperm">;
119119 def HasRCPC : Predicate<"Subtarget->hasRCPC()">,
120120 AssemblerPredicate<"FeatureRCPC", "rcpc">;
121121 def HasAltNZCV : Predicate<"Subtarget->hasAlternativeNZCV()">,
11631163 defm SQRSHLR_ZPmZ : sve2_int_arith_pred<0b011100, "sqrshlr">;
11641164 defm UQRSHLR_ZPmZ : sve2_int_arith_pred<0b011110, "uqrshlr">;
11651165
1166 // SVE2 predicated shifts
1167 defm SQSHL_ZPmI : sve_int_bin_pred_shift_imm_left< 0b0110, "sqshl">;
1168 defm UQSHL_ZPmI : sve_int_bin_pred_shift_imm_left< 0b0111, "uqshl">;
1169 defm SRSHR_ZPmI : sve_int_bin_pred_shift_imm_right<0b1100, "srshr">;
1170 defm URSHR_ZPmI : sve_int_bin_pred_shift_imm_right<0b1101, "urshr">;
1171 defm SQSHLU_ZPmI : sve_int_bin_pred_shift_imm_left< 0b1111, "sqshlu">;
1172
11661173 // SVE2 integer add/subtract long
11671174 defm SADDLB_ZZZ : sve2_wide_int_arith_long<0b00000, "saddlb">;
11681175 defm SADDLT_ZZZ : sve2_wide_int_arith_long<0b00001, "saddlt">;
11981205 defm PMULLT_ZZZ : sve2_pmul_long<0b1, "pmullt">;
11991206
12001207 // SVE2 bitwise shift and insert
1201 defm SRI_ZZI : sve2_int_bin_cons_shift_imm_right<0b0, "sri">;
1202 defm SLI_ZZI : sve2_int_bin_cons_shift_imm_left< 0b1, "sli">;
1208 defm SRI_ZZI : sve2_int_bin_shift_imm_right<0b0, "sri">;
1209 defm SLI_ZZI : sve2_int_bin_shift_imm_left< 0b1, "sli">;
12031210
12041211 // SVE2 bitwise shift right and accumulate
1205 defm SSRA_ZZI : sve2_int_bin_accum_cons_shift_imm_right<0b00, "ssra">;
1206 defm USRA_ZZI : sve2_int_bin_accum_cons_shift_imm_right<0b01, "usra">;
1207 defm SRSRA_ZZI : sve2_int_bin_accum_cons_shift_imm_right<0b10, "srsra">;
1208 defm URSRA_ZZI : sve2_int_bin_accum_cons_shift_imm_right<0b11, "ursra">;
1212 defm SSRA_ZZI : sve2_int_bin_accum_shift_imm_right<0b00, "ssra">;
1213 defm USRA_ZZI : sve2_int_bin_accum_shift_imm_right<0b01, "usra">;
1214 defm SRSRA_ZZI : sve2_int_bin_accum_shift_imm_right<0b10, "srsra">;
1215 defm URSRA_ZZI : sve2_int_bin_accum_shift_imm_right<0b11, "ursra">;
12091216
12101217 // SVE2 complex integer add
12111218 defm CADD_ZZI : sve2_int_cadd<0b0, "cadd">;
12271234 defm SBCLB_ZZZ : sve2_int_addsub_long_carry<0b10, "sbclb">;
12281235 defm SBCLT_ZZZ : sve2_int_addsub_long_carry<0b11, "sbclt">;
12291236
1230 // SVE2 bitwise shift right narrow
1231 defm SQSHRUNB_ZZI : sve2_int_bin_cons_shift_imm_right_narrow<0b0000, "sqshrunb">;
1232 defm SQSHRUNT_ZZI : sve2_int_bin_cons_shift_imm_right_narrow<0b0001, "sqshrunt">;
1233 defm SQRSHRUNB_ZZI : sve2_int_bin_cons_shift_imm_right_narrow<0b0010, "sqrshrunb">;
1234 defm SQRSHRUNT_ZZI : sve2_int_bin_cons_shift_imm_right_narrow<0b0011, "sqrshrunt">;
1235 defm SHRNB_ZZI : sve2_int_bin_cons_shift_imm_right_narrow<0b0100, "shrnb">;
1236 defm SHRNT_ZZI : sve2_int_bin_cons_shift_imm_right_narrow<0b0101, "shrnt">;
1237 defm RSHRNB_ZZI : sve2_int_bin_cons_shift_imm_right_narrow<0b0110, "rshrnb">;
1238 defm RSHRNT_ZZI : sve2_int_bin_cons_shift_imm_right_narrow<0b0111, "rshrnt">;
1239 defm SQSHRNB_ZZI : sve2_int_bin_cons_shift_imm_right_narrow<0b1000, "sqshrnb">;
1240 defm SQSHRNT_ZZI : sve2_int_bin_cons_shift_imm_right_narrow<0b1001, "sqshrnt">;
1241 defm SQRSHRNB_ZZI : sve2_int_bin_cons_shift_imm_right_narrow<0b1010, "sqrshrnb">;
1242 defm SQRSHRNT_ZZI : sve2_int_bin_cons_shift_imm_right_narrow<0b1011, "sqrshrnt">;
1243 defm UQSHRNB_ZZI : sve2_int_bin_cons_shift_imm_right_narrow<0b1100, "uqshrnb">;
1244 defm UQSHRNT_ZZI : sve2_int_bin_cons_shift_imm_right_narrow<0b1101, "uqshrnt">;
1245 defm UQRSHRNB_ZZI : sve2_int_bin_cons_shift_imm_right_narrow<0b1110, "uqrshrnb">;
1246 defm UQRSHRNT_ZZI : sve2_int_bin_cons_shift_imm_right_narrow<0b1111, "uqrshrnt">;
1247
1248 // SVE2 integer add/subtract narrow high part
1249 defm ADDHNB_ZZZ : sve2_int_addsub_narrow_high<0b000, "addhnb">;
1250 defm ADDHNT_ZZZ : sve2_int_addsub_narrow_high<0b001, "addhnt">;
1251 defm RADDHNB_ZZZ : sve2_int_addsub_narrow_high<0b010, "raddhnb">;
1252 defm RADDHNT_ZZZ : sve2_int_addsub_narrow_high<0b011, "raddhnt">;
1253 defm SUBHNB_ZZZ : sve2_int_addsub_narrow_high<0b100, "subhnb">;
1254 defm SUBHNT_ZZZ : sve2_int_addsub_narrow_high<0b101, "subhnt">;
1255 defm RSUBHNB_ZZZ : sve2_int_addsub_narrow_high<0b110, "rsubhnb">;
1256 defm RSUBHNT_ZZZ : sve2_int_addsub_narrow_high<0b111, "rsubhnt">;
1257
1258 // SVE2 saturating extract narrow
1259 defm SQXTNB_ZZ : sve2_int_sat_extract_narrow<0b000, "sqxtnb">;
1260 defm SQXTNT_ZZ : sve2_int_sat_extract_narrow<0b001, "sqxtnt">;
1261 defm UQXTNB_ZZ : sve2_int_sat_extract_narrow<0b010, "uqxtnb">;
1262 defm UQXTNT_ZZ : sve2_int_sat_extract_narrow<0b011, "uqxtnt">;
1263 defm SQXTUNB_ZZ : sve2_int_sat_extract_narrow<0b100, "sqxtunb">;
1264 defm SQXTUNT_ZZ : sve2_int_sat_extract_narrow<0b101, "sqxtunt">;
1237 // SVE2 bitwise shift right narrow (bottom)
1238 defm SQSHRUNB_ZZI : sve2_int_bin_shift_imm_right_narrow_bottom<0b000, "sqshrunb">;
1239 defm SQRSHRUNB_ZZI : sve2_int_bin_shift_imm_right_narrow_bottom<0b001, "sqrshrunb">;
1240 defm SHRNB_ZZI : sve2_int_bin_shift_imm_right_narrow_bottom<0b010, "shrnb">;
1241 defm RSHRNB_ZZI : sve2_int_bin_shift_imm_right_narrow_bottom<0b011, "rshrnb">;
1242 defm SQSHRNB_ZZI : sve2_int_bin_shift_imm_right_narrow_bottom<0b100, "sqshrnb">;
1243 defm SQRSHRNB_ZZI : sve2_int_bin_shift_imm_right_narrow_bottom<0b101, "sqrshrnb">;
1244 defm UQSHRNB_ZZI : sve2_int_bin_shift_imm_right_narrow_bottom<0b110, "uqshrnb">;
1245 defm UQRSHRNB_ZZI : sve2_int_bin_shift_imm_right_narrow_bottom<0b111, "uqrshrnb">;
1246
1247 // SVE2 bitwise shift right narrow (top)
1248 defm SQSHRUNT_ZZI : sve2_int_bin_shift_imm_right_narrow_top<0b000, "sqshrunt">;
1249 defm SQRSHRUNT_ZZI : sve2_int_bin_shift_imm_right_narrow_top<0b001, "sqrshrunt">;
1250 defm SHRNT_ZZI : sve2_int_bin_shift_imm_right_narrow_top<0b010, "shrnt">;
1251 defm RSHRNT_ZZI : sve2_int_bin_shift_imm_right_narrow_top<0b011, "rshrnt">;
1252 defm SQSHRNT_ZZI : sve2_int_bin_shift_imm_right_narrow_top<0b100, "sqshrnt">;
1253 defm SQRSHRNT_ZZI : sve2_int_bin_shift_imm_right_narrow_top<0b101, "sqrshrnt">;
1254 defm UQSHRNT_ZZI : sve2_int_bin_shift_imm_right_narrow_top<0b110, "uqshrnt">;
1255 defm UQRSHRNT_ZZI : sve2_int_bin_shift_imm_right_narrow_top<0b111, "uqrshrnt">;
1256
1257 // SVE2 integer add/subtract narrow high part (bottom)
1258 defm ADDHNB_ZZZ : sve2_int_addsub_narrow_high_bottom<0b00, "addhnb">;
1259 defm RADDHNB_ZZZ : sve2_int_addsub_narrow_high_bottom<0b01, "raddhnb">;
1260 defm SUBHNB_ZZZ : sve2_int_addsub_narrow_high_bottom<0b10, "subhnb">;
1261 defm RSUBHNB_ZZZ : sve2_int_addsub_narrow_high_bottom<0b11, "rsubhnb">;
1262
1263 // SVE2 integer add/subtract narrow high part (top)
1264 defm ADDHNT_ZZZ : sve2_int_addsub_narrow_high_top<0b00, "addhnt">;
1265 defm RADDHNT_ZZZ : sve2_int_addsub_narrow_high_top<0b01, "raddhnt">;
1266 defm SUBHNT_ZZZ : sve2_int_addsub_narrow_high_top<0b10, "subhnt">;
1267 defm RSUBHNT_ZZZ : sve2_int_addsub_narrow_high_top<0b11, "rsubhnt">;
1268
1269 // SVE2 saturating extract narrow (bottom)
1270 defm SQXTNB_ZZ : sve2_int_sat_extract_narrow_bottom<0b00, "sqxtnb">;
1271 defm UQXTNB_ZZ : sve2_int_sat_extract_narrow_bottom<0b01, "uqxtnb">;
1272 defm SQXTUNB_ZZ : sve2_int_sat_extract_narrow_bottom<0b10, "sqxtunb">;
1273
1274 // SVE2 saturating extract narrow (top)
1275 defm SQXTNT_ZZ : sve2_int_sat_extract_narrow_top<0b00, "sqxtnt">;
1276 defm UQXTNT_ZZ : sve2_int_sat_extract_narrow_top<0b01, "uqxtnt">;
1277 defm SQXTUNT_ZZ : sve2_int_sat_extract_narrow_top<0b10, "sqxtunt">;
12651278
12661279 // SVE2 character match
12671280 defm MATCH_PPzZZ : sve2_char_match<0b0, "match">;
12881301 // SVE2 histogram generation (vector)
12891302 defm HISTCNT_ZPzZZ : sve2_hist_gen_vector<"histcnt">;
12901303
1304 // SVE2 floating-point base 2 logarithm as integer
1305 defm FLOGB_ZPmZ : sve2_fp_flogb<"flogb">;
1306
12911307 // SVE2 floating-point convert precision
12921308 defm FCVTXNT_ZPmZ : sve2_fp_convert_down_odd_rounding<"fcvtxnt">;
12931309 defm FCVTNT_ZPmZ : sve2_fp_convert_down_narrow<"fcvtnt">;
12941310 defm FCVTLT_ZPmZ : sve2_fp_convert_up_long<"fcvtlt">;
1311 def FCVTX_ZPmZ_DtoS : sve_fp_2op_p_zd<0b0001010, "fcvtx", ZPR64, ZPR32, ElementSizeD>;
12951312
12961313 // SVE2 floating-point pairwise operations
12971314 defm FADDP_ZPmZZ : sve2_fp_pairwise_pred<0b000, "faddp">;
13201337 def BSL2N_ZZZZ_D : sve2_int_bitwise_ternary_op_d<0b101, "bsl2n">;
13211338 def NBSL_ZZZZ_D : sve2_int_bitwise_ternary_op_d<0b111, "nbsl">;
13221339
1323 // sve_int_rotate_imm
1340 // SVE2 bitwise xor and rotate right by immediate
13241341 defm XAR_ZZZI : sve2_int_rotate_right_imm<"xar">;
13251342
13261343 // SVE2 extract vector (immediate offset, constructive)
13271344 def EXT_ZZI_B : sve2_int_perm_extract_i_cons<"ext">;
13281345
1329 // SVE floating-point convert precision
1330 def FCVTX_ZPmZ_DtoS : sve_fp_2op_p_zd<0b0001010, "fcvtx", ZPR64, ZPR32, ElementSizeD>;
1331
1332 // SVE floating-point convert to integer
1333 defm FLOGB_ZPmZ : sve2_fp_flogb<"flogb">;
1334
1335 // Non-temporal contiguous loads (vector + register)
1336 defm LDNT1SB_ZZR_S : sve2_mem_cldnt_vs<0b00000, "ldnt1sb", Z_s, ZPR32>;
1337 defm LDNT1B_ZZR_S : sve2_mem_cldnt_vs<0b00001, "ldnt1b", Z_s, ZPR32>;
1338 defm LDNT1SH_ZZR_S : sve2_mem_cldnt_vs<0b00100, "ldnt1sh", Z_s, ZPR32>;
1339 defm LDNT1H_ZZR_S : sve2_mem_cldnt_vs<0b00101, "ldnt1h", Z_s, ZPR32>;
1340 defm LDNT1W_ZZR_S : sve2_mem_cldnt_vs<0b01001, "ldnt1w", Z_s, ZPR32>;
1341
1342 defm LDNT1SB_ZZR_D : sve2_mem_cldnt_vs<0b10000, "ldnt1sb", Z_d, ZPR64>;
1343 defm LDNT1B_ZZR_D : sve2_mem_cldnt_vs<0b10010, "ldnt1b", Z_d, ZPR64>;
1344 defm LDNT1SH_ZZR_D : sve2_mem_cldnt_vs<0b10100, "ldnt1sh", Z_d, ZPR64>;
1345 defm LDNT1H_ZZR_D : sve2_mem_cldnt_vs<0b10110, "ldnt1h", Z_d, ZPR64>;
1346 defm LDNT1SW_ZZR_D : sve2_mem_cldnt_vs<0b11000, "ldnt1sw", Z_d, ZPR64>;
1347 defm LDNT1W_ZZR_D : sve2_mem_cldnt_vs<0b11010, "ldnt1w", Z_d, ZPR64>;
1348 defm LDNT1D_ZZR_D : sve2_mem_cldnt_vs<0b11110, "ldnt1d", Z_d, ZPR64>;
1346 // SVE2 non-temporal gather loads
1347 defm LDNT1SB_ZZR_S : sve2_mem_gldnt_vs<0b00000, "ldnt1sb", Z_s, ZPR32>;
1348 defm LDNT1B_ZZR_S : sve2_mem_gldnt_vs<0b00001, "ldnt1b", Z_s, ZPR32>;
1349 defm LDNT1SH_ZZR_S : sve2_mem_gldnt_vs<0b00100, "ldnt1sh", Z_s, ZPR32>;
1350 defm LDNT1H_ZZR_S : sve2_mem_gldnt_vs<0b00101, "ldnt1h", Z_s, ZPR32>;
1351 defm LDNT1W_ZZR_S : sve2_mem_gldnt_vs<0b01001, "ldnt1w", Z_s, ZPR32>;
1352
1353 defm LDNT1SB_ZZR_D : sve2_mem_gldnt_vs<0b10000, "ldnt1sb", Z_d, ZPR64>;
1354 defm LDNT1B_ZZR_D : sve2_mem_gldnt_vs<0b10010, "ldnt1b", Z_d, ZPR64>;
1355 defm LDNT1SH_ZZR_D : sve2_mem_gldnt_vs<0b10100, "ldnt1sh", Z_d, ZPR64>;
1356 defm LDNT1H_ZZR_D : sve2_mem_gldnt_vs<0b10110, "ldnt1h", Z_d, ZPR64>;
1357 defm LDNT1SW_ZZR_D : sve2_mem_gldnt_vs<0b11000, "ldnt1sw", Z_d, ZPR64>;
1358 defm LDNT1W_ZZR_D : sve2_mem_gldnt_vs<0b11010, "ldnt1w", Z_d, ZPR64>;
1359 defm LDNT1D_ZZR_D : sve2_mem_gldnt_vs<0b11110, "ldnt1d", Z_d, ZPR64>;
13491360
13501361 // SVE2 vector splice (constructive)
13511362 defm SPLICE_ZPZZ : sve2_int_perm_splice_cons<"splice">;
13521363
1353 // Predicated shifts
1354 defm SQSHL_ZPmI : sve_int_bin_pred_shift_imm_left< 0b0110, "sqshl">;
1355 defm UQSHL_ZPmI : sve_int_bin_pred_shift_imm_left< 0b0111, "uqshl">;
1356 defm SRSHR_ZPmI : sve_int_bin_pred_shift_imm_right<0b1100, "srshr">;
1357 defm URSHR_ZPmI : sve_int_bin_pred_shift_imm_right<0b1101, "urshr">;
1358 defm SQSHLU_ZPmI : sve_int_bin_pred_shift_imm_left< 0b1111, "sqshlu">;
1359
1360 // Non-temporal contiguous stores (vector + register)
1361 defm STNT1B_ZZR_S : sve2_mem_cstnt_vs<0b001, "stnt1b", Z_s, ZPR32>;
1362 defm STNT1H_ZZR_S : sve2_mem_cstnt_vs<0b011, "stnt1h", Z_s, ZPR32>;
1363 defm STNT1W_ZZR_S : sve2_mem_cstnt_vs<0b101, "stnt1w", Z_s, ZPR32>;
1364
1365 defm STNT1B_ZZR_D : sve2_mem_cstnt_vs<0b000, "stnt1b", Z_d, ZPR64>;
1366 defm STNT1H_ZZR_D : sve2_mem_cstnt_vs<0b010, "stnt1h", Z_d, ZPR64>;
1367 defm STNT1W_ZZR_D : sve2_mem_cstnt_vs<0b100, "stnt1w", Z_d, ZPR64>;
1368 defm STNT1D_ZZR_D : sve2_mem_cstnt_vs<0b110, "stnt1d", Z_d, ZPR64>;
1369
1370 // SVE table lookup (three sources)
1364 // SVE2 non-temporal scatter stores
1365 defm STNT1B_ZZR_S : sve2_mem_sstnt_vs<0b001, "stnt1b", Z_s, ZPR32>;
1366 defm STNT1H_ZZR_S : sve2_mem_sstnt_vs<0b011, "stnt1h", Z_s, ZPR32>;
1367 defm STNT1W_ZZR_S : sve2_mem_sstnt_vs<0b101, "stnt1w", Z_s, ZPR32>;
1368
1369 defm STNT1B_ZZR_D : sve2_mem_sstnt_vs<0b000, "stnt1b", Z_d, ZPR64>;
1370 defm STNT1H_ZZR_D : sve2_mem_sstnt_vs<0b010, "stnt1h", Z_d, ZPR64>;
1371 defm STNT1W_ZZR_D : sve2_mem_sstnt_vs<0b100, "stnt1w", Z_d, ZPR64>;
1372 defm STNT1D_ZZR_D : sve2_mem_sstnt_vs<0b110, "stnt1d", Z_d, ZPR64>;
1373
1374 // SVE2 table lookup (three sources)
13711375 defm TBL_ZZZZ : sve2_int_perm_tbl<"tbl">;
13721376 defm TBX_ZZZ : sve2_int_perm_tbx<"tbx">;
13731377
1374 // SVE integer compare scalar count and limit
1378 // SVE2 integer compare scalar count and limit
13751379 defm WHILEGE_PWW : sve_int_while4_rr<0b000, "whilege">;
13761380 defm WHILEGT_PWW : sve_int_while4_rr<0b001, "whilegt">;
13771381 defm WHILEHS_PWW : sve_int_while4_rr<0b100, "whilehs">;
13821386 defm WHILEHS_PXX : sve_int_while8_rr<0b100, "whilehs">;
13831387 defm WHILEHI_PXX : sve_int_while8_rr<0b101, "whilehi">;
13841388
1385 // SVE pointer conflict compare
1389 // SVE2 pointer conflict compare
13861390 defm WHILEWR_PXX : sve2_int_while_rr<0b0, "whilewr">;
13871391 defm WHILERW_PXX : sve2_int_while_rr<0b1, "whilerw">;
13881392 }
28392839 {"sve2-aes", {AArch64::FeatureSVE2AES}},
28402840 {"sve2-sm4", {AArch64::FeatureSVE2SM4}},
28412841 {"sve2-sha3", {AArch64::FeatureSVE2SHA3}},
2842 {"bitperm", {AArch64::FeatureSVE2BitPerm}},
2842 {"sve2-bitperm", {AArch64::FeatureSVE2BitPerm}},
28432843 // FIXME: Unsupported extensions
28442844 {"pan", {}},
28452845 {"lor", {}},
743743 }
744744
745745 class sve2_int_perm_tbx sz8_64, string asm, ZPRRegOp zprty>
746 : I<(outs zprty:$Zd), (ins zprty:$Zn, zprty:$Zm),
746 : I<(outs zprty:$Zd), (ins zprty:$_Zd, zprty:$Zn, zprty:$Zm),
747747 asm, "\t$Zd, $Zn, $Zm",
748748 "",
749749 []>, Sched<[]> {
757757 let Inst{15-10} = 0b001011;
758758 let Inst{9-5} = Zn;
759759 let Inst{4-0} = Zd;
760
761 let Constraints = "$Zd = $_Zd";
760762 }
761763
762764 multiclass sve2_int_perm_tbx {
14881490
14891491 class sve2_fp_convert_precision opc, string asm,
14901492 ZPRRegOp zprty1, ZPRRegOp zprty2>
1491 : I<(outs zprty1:$Zd), (ins PPR3bAny:$Pg, zprty2:$Zn),
1493 : I<(outs zprty1:$Zd), (ins zprty1:$_Zd, PPR3bAny:$Pg, zprty2:$Zn),
14921494 asm, "\t$Zd, $Pg/m, $Zn",
14931495 "",
14941496 []>, Sched<[]> {
15031505 let Inst{12-10} = Pg;
15041506 let Inst{9-5} = Zn;
15051507 let Inst{4-0} = Zd;
1508
1509 let Constraints = "$Zd = $_Zd";
15061510 }
15071511
15081512 multiclass sve2_fp_convert_down_narrow {
23982402 def _D : sve2_misc<0b11, opc, asm, ZPR64, ZPR64>;
23992403 }
24002404
2401 multiclass sve2_bitwise_xor_interleaved {
2402 let DestructiveInstType = Destructive, ElementSize = ElementSizeNone in {
2403 def _B : sve2_misc<0b00, { 0b010, opc }, asm, ZPR8, ZPR8>;
2404 def _H : sve2_misc<0b01, { 0b010, opc }, asm, ZPR16, ZPR16>;
2405 def _S : sve2_misc<0b10, { 0b010, opc }, asm, ZPR32, ZPR32>;
2406 def _D : sve2_misc<0b11, { 0b010, opc }, asm, ZPR64, ZPR64>;
2407 }
2408 }
2409
24102405 multiclass sve2_misc_int_addsub_long_interleaved opc, string asm> {
24112406 def _H : sve2_misc<0b01, { 0b00, opc }, asm, ZPR16, ZPR8>;
24122407 def _S : sve2_misc<0b10, { 0b00, opc }, asm, ZPR32, ZPR16>;
24132408 def _D : sve2_misc<0b11, { 0b00, opc }, asm, ZPR64, ZPR32>;
2409 }
2410
2411 class sve2_bitwise_xor_interleaved sz, bits<1> opc, string asm,
2412 ZPRRegOp zprty1, ZPRRegOp zprty2>
2413 : I<(outs zprty1:$Zd), (ins zprty1:$_Zd, zprty2:$Zn, zprty2:$Zm),
2414 asm, "\t$Zd, $Zn, $Zm", "", []>, Sched<[]> {
2415 bits<5> Zd;
2416 bits<5> Zn;
2417 bits<5> Zm;
2418 let Inst{31-24} = 0b01000101;
2419 let Inst{23-22} = sz;
2420 let Inst{21} = 0b0;
2421 let Inst{20-16} = Zm;
2422 let Inst{15-11} = 0b10010;
2423 let Inst{10} = opc;
2424 let Inst{9-5} = Zn;
2425 let Inst{4-0} = Zd;
2426
2427 let Constraints = "$Zd = $_Zd";
2428 let DestructiveInstType = Destructive;
2429 let ElementSize = ElementSizeNone;
2430 }
2431
2432 multiclass sve2_bitwise_xor_interleaved {
2433 def _B : sve2_bitwise_xor_interleaved<0b00, opc, asm, ZPR8, ZPR8>;
2434 def _H : sve2_bitwise_xor_interleaved<0b01, opc, asm, ZPR16, ZPR16>;
2435 def _S : sve2_bitwise_xor_interleaved<0b10, opc, asm, ZPR32, ZPR32>;
2436 def _D : sve2_bitwise_xor_interleaved<0b11, opc, asm, ZPR64, ZPR64>;
24142437 }
24152438
24162439 class sve2_bitwise_shift_left_long tsz8_64, bits<2> opc, string asm,
24502473 // SVE2 Accumulate Group
24512474 //===----------------------------------------------------------------------===//
24522475
2453 class sve2_int_bin_cons_shift_imm tsz8_64, bit opc, string asm,
2454 ZPRRegOp zprty, Operand immtype>
2455 : I<(outs zprty:$Zd), (ins zprty:$Zn, immtype:$imm),
2476 class sve2_int_bin_shift_imm tsz8_64, bit opc, string asm,
2477 ZPRRegOp zprty, Operand immtype>
2478 : I<(outs zprty:$Zd), (ins zprty:$_Zd, zprty:$Zn, immtype:$imm),
24562479 asm, "\t$Zd, $Zn, $imm",
24572480 "", []>, Sched<[]> {
24582481 bits<5> Zd;
24672490 let Inst{10} = opc;
24682491 let Inst{9-5} = Zn;
24692492 let Inst{4-0} = Zd;
2470 }
2471
2472 multiclass sve2_int_bin_cons_shift_imm_left {
2473 def _B : sve2_int_bin_cons_shift_imm<{0,0,0,1}, opc, asm, ZPR8, vecshiftL8>;
2474 def _H : sve2_int_bin_cons_shift_imm<{0,0,1,?}, opc, asm, ZPR16, vecshiftL16> {
2493
2494 let Constraints = "$Zd = $_Zd";
2495 }
2496
2497 multiclass sve2_int_bin_shift_imm_left {
2498 def _B : sve2_int_bin_shift_imm<{0,0,0,1}, opc, asm, ZPR8, vecshiftL8>;
2499 def _H : sve2_int_bin_shift_imm<{0,0,1,?}, opc, asm, ZPR16, vecshiftL16> {
24752500 let Inst{19} = imm{3};
24762501 }
2477 def _S : sve2_int_bin_cons_shift_imm<{0,1,?,?}, opc, asm, ZPR32, vecshiftL32> {
2502 def _S : sve2_int_bin_shift_imm<{0,1,?,?}, opc, asm, ZPR32, vecshiftL32> {
24782503 let Inst{20-19} = imm{4-3};
24792504 }
2480 def _D : sve2_int_bin_cons_shift_imm<{1,?,?,?}, opc, asm, ZPR64, vecshiftL64> {
2505 def _D : sve2_int_bin_shift_imm<{1,?,?,?}, opc, asm, ZPR64, vecshiftL64> {
24812506 let Inst{22} = imm{5};
24822507 let Inst{20-19} = imm{4-3};
24832508 }
24842509 }
24852510
2486 multiclass sve2_int_bin_cons_shift_imm_right {
2487 def _B : sve2_int_bin_cons_shift_imm<{0,0,0,1}, opc, asm, ZPR8, vecshiftR8>;
2488 def _H : sve2_int_bin_cons_shift_imm<{0,0,1,?}, opc, asm, ZPR16, vecshiftR16> {
2511 multiclass sve2_int_bin_shift_imm_right> {
2512 def _B : sve2_int_bin_shift_imm<{0,0,0,1}, opc, asm, ZPR8, vecshiftR8>;
2513 def _H : sve2_int_bin_shift_imm<{0,0,1,?}, opc, asm, ZPR16, vecshiftR16> {
24892514 let Inst{19} = imm{3};
24902515 }
2491 def _S : sve2_int_bin_cons_shift_imm<{0,1,?,?}, opc, asm, ZPR32, vecshiftR32> {
2516 def _S : sve2_int_bin_shift_imm<{0,1,?,?}, opc, asm, ZPR32, vecshiftR32> {
24922517 let Inst{20-19} = imm{4-3};
24932518 }
2494 def _D : sve2_int_bin_cons_shift_imm<{1,?,?,?}, opc, asm, ZPR64, vecshiftR64> {
2519 def _D : sve2_int_bin_shift_imm<{1,?,?,?}, opc, asm, ZPR64, vecshiftR64> {
24952520 let Inst{22} = imm{5};
24962521 let Inst{20-19} = imm{4-3};
24972522 }
24982523 }
24992524
2500 class sve2_int_bin_accum_cons_shift_imm tsz8_64, bits<2> opc, string asm,
2501 ZPRRegOp zprty, Operand immtype>
2525 class sve2_int_bin_accum_shift_imm tsz8_64, bits<2> opc, string asm,
2526 ZPRRegOp zprty, Operand immtype>
25022527 : I<(outs zprty:$Zda), (ins zprty:$_Zda, zprty:$Zn, immtype:$imm),
25032528 asm, "\t$Zda, $Zn, $imm",
25042529 "", []>, Sched<[]> {
25202545 let ElementSize = ElementSizeNone;
25212546 }
25222547
2523 multiclass sve2_int_bin_accum_cons_shift_imm_right opc, string asm> {
2524 def _B : sve2_int_bin_accum_cons_shift_imm<{0,0,0,1}, opc, asm, ZPR8, vecshiftR8>;
2525 def _H : sve2_int_bin_accum_cons_shift_imm<{0,0,1,?}, opc, asm, ZPR16, vecshiftR16> {
2548 multiclass sve2_int_bin_accum_shift_imm_right opc, string asm> {
2549 def _B : sve2_int_bin_accum_shift_imm<{0,0,0,1}, opc, asm, ZPR8, vecshiftR8>;
2550 def _H : sve2_int_bin_accum_shift_imm<{0,0,1,?}, opc, asm, ZPR16, vecshiftR16> {
25262551 let Inst{19} = imm{3};
25272552 }
2528 def _S : sve2_int_bin_accum_cons_shift_imm<{0,1,?,?}, opc, asm, ZPR32, vecshiftR32> {
2553 def _S : sve2_int_bin_accum_shift_imm<{0,1,?,?}, opc, asm, ZPR32, vecshiftR32> {
25292554 let Inst{20-19} = imm{4-3};
25302555 }
2531 def _D : sve2_int_bin_accum_cons_shift_imm<{1,?,?,?}, opc, asm, ZPR64, vecshiftR64> {
2556 def _D : sve2_int_bin_accum_shift_imm<{1,?,?,?}, opc, asm, ZPR64, vecshiftR64> {
25322557 let Inst{22} = imm{5};
25332558 let Inst{20-19} = imm{4-3};
25342559 }
26062631 // SVE2 Narrowing Group
26072632 //===----------------------------------------------------------------------===//
26082633
2609 class sve2_int_bin_cons_shift_imm_narrow tsz8_64, bits<4> opc,
2610 string asm, ZPRRegOp zprty1,
2611 ZPRRegOp zprty2, Operand immtype>
2634 class sve2_int_bin_shift_imm_narrow_bottom tsz8_64, bits<3> opc,
2635 string asm, ZPRRegOp zprty1,
2636 ZPRRegOp zprty2, Operand immtype>
26122637 : I<(outs zprty1:$Zd), (ins zprty2:$Zn, immtype:$imm),
26132638 asm, "\t$Zd, $Zn, $imm",
26142639 "", []>, Sched<[]> {
26212646 let Inst{20-19} = tsz8_64{1-0};
26222647 let Inst{18-16} = imm{2-0}; // imm3
26232648 let Inst{15-14} = 0b00;
2624 let Inst{13-10} = opc;
2649 let Inst{13-11} = opc;
2650 let Inst{10} = 0b0;
26252651 let Inst{9-5} = Zn;
26262652 let Inst{4-0} = Zd;
26272653 }
26282654
2629 multiclass sve2_int_bin_cons_shift_imm_right_narrow opc, string asm> {
2630 def _B : sve2_int_bin_cons_shift_imm_narrow<{0,0,1}, opc, asm, ZPR8, ZPR16,
2631 vecshiftR8>;
2632 def _H : sve2_int_bin_cons_shift_imm_narrow<{0,1,?}, opc, asm, ZPR16, ZPR32,
2633 vecshiftR16> {
2655 multiclass sve2_int_bin_shift_imm_right_narrow_bottom opc, string asm> {
2656 def _B : sve2_int_bin_shift_imm_narrow_bottom<{0,0,1}, opc, asm, ZPR8, ZPR16,
2657 vecshiftR8>;
2658 def _H : sve2_int_bin_shift_imm_narrow_bottom<{0,1,?}, opc, asm, ZPR16, ZPR32,
2659 vecshiftR16> {
26342660 let Inst{19} = imm{3};
26352661 }
2636 def _S : sve2_int_bin_cons_shift_imm_narrow<{1,?,?}, opc, asm, ZPR32, ZPR64,
2637 vecshiftR32> {
2662 def _S : sve2_int_bin_shift_imm_narrow_bottom<{1,?,?}, opc, asm, ZPR32, ZPR64,
2663 vecshiftR32> {
26382664 let Inst{20-19} = imm{4-3};
26392665 }
26402666 }
26412667
2642 class sve2_int_addsub_narrow_high sz, bits<3> opc, string asm,
2643 ZPRRegOp zprty1, ZPRRegOp zprty2>
2668 class sve2_int_bin_shift_imm_narrow_top tsz8_64, bits<3> opc,
2669 string asm, ZPRRegOp zprty1,
2670 ZPRRegOp zprty2, Operand immtype>
2671 : I<(outs zprty1:$Zd), (ins zprty1:$_Zd, zprty2:$Zn, immtype:$imm),
2672 asm, "\t$Zd, $Zn, $imm",
2673 "", []>, Sched<[]> {
2674 bits<5> Zd;
2675 bits<5> Zn;
2676 bits<5> imm;
2677 let Inst{31-23} = 0b010001010;
2678 let Inst{22} = tsz8_64{2};
2679 let Inst{21} = 0b1;
2680 let Inst{20-19} = tsz8_64{1-0};
2681 let Inst{18-16} = imm{2-0}; // imm3
2682 let Inst{15-14} = 0b00;
2683 let Inst{13-11} = opc;
2684 let Inst{10} = 0b1;
2685 let Inst{9-5} = Zn;
2686 let Inst{4-0} = Zd;
2687
2688 let Constraints = "$Zd = $_Zd";
2689 }
2690
2691 multiclass sve2_int_bin_shift_imm_right_narrow_top opc, string asm> {
2692 def _B : sve2_int_bin_shift_imm_narrow_top<{0,0,1}, opc, asm, ZPR8, ZPR16,
2693 vecshiftR8>;
2694 def _H : sve2_int_bin_shift_imm_narrow_top<{0,1,?}, opc, asm, ZPR16, ZPR32,
2695 vecshiftR16> {
2696 let Inst{19} = imm{3};
2697 }
2698 def _S : sve2_int_bin_shift_imm_narrow_top<{1,?,?}, opc, asm, ZPR32, ZPR64,
2699 vecshiftR32> {
2700 let Inst{20-19} = imm{4-3};
2701 }
2702 }
2703
2704 class sve2_int_addsub_narrow_high_bottom sz, bits<2> opc, string asm,
2705 ZPRRegOp zprty1, ZPRRegOp zprty2>
26442706 : I<(outs zprty1:$Zd), (ins zprty2:$Zn, zprty2:$Zm),
26452707 asm, "\t$Zd, $Zn, $Zm", "", []>, Sched<[]> {
26462708 bits<5> Zd;
26512713 let Inst{21} = 0b1;
26522714 let Inst{20-16} = Zm;
26532715 let Inst{15-13} = 0b011;
2654 let Inst{12-10} = opc; // S, R, T
2716 let Inst{12-11} = opc; // S, R
2717 let Inst{10} = 0b0; // Top
26552718 let Inst{9-5} = Zn;
26562719 let Inst{4-0} = Zd;
26572720 }
26582721
2659 multiclass sve2_int_addsub_narrow_high opc, string asm> {
2660 def _B : sve2_int_addsub_narrow_high<0b01, opc, asm, ZPR8, ZPR16>;
2661 def _H : sve2_int_addsub_narrow_high<0b10, opc, asm, ZPR16, ZPR32>;
2662 def _S : sve2_int_addsub_narrow_high<0b11, opc, asm, ZPR32, ZPR64>;
2663 }
2664
2665 class sve2_int_sat_extract_narrow tsz8_64, bits<3> opc, string asm,
2666 ZPRRegOp zprty1, ZPRRegOp zprty2>
2722 multiclass sve2_int_addsub_narrow_high_bottom opc, string asm> {
2723 def _B : sve2_int_addsub_narrow_high_bottom<0b01, opc, asm, ZPR8, ZPR16>;
2724 def _H : sve2_int_addsub_narrow_high_bottom<0b10, opc, asm, ZPR16, ZPR32>;
2725 def _S : sve2_int_addsub_narrow_high_bottom<0b11, opc, asm, ZPR32, ZPR64>;
2726 }
2727
2728 class sve2_int_addsub_narrow_high_top sz, bits<2> opc, string asm,
2729 ZPRRegOp zprty1, ZPRRegOp zprty2>
2730 : I<(outs zprty1:$Zd), (ins zprty1:$_Zd, zprty2:$Zn, zprty2:$Zm),
2731 asm, "\t$Zd, $Zn, $Zm", "", []>, Sched<[]> {
2732 bits<5> Zd;
2733 bits<5> Zn;
2734 bits<5> Zm;
2735 let Inst{31-24} = 0b01000101;
2736 let Inst{23-22} = sz;
2737 let Inst{21} = 0b1;
2738 let Inst{20-16} = Zm;
2739 let Inst{15-13} = 0b011;
2740 let Inst{12-11} = opc; // S, R
2741 let Inst{10} = 0b1; // Top
2742 let Inst{9-5} = Zn;
2743 let Inst{4-0} = Zd;
2744
2745 let Constraints = "$Zd = $_Zd";
2746 }
2747
2748 multiclass sve2_int_addsub_narrow_high_top opc, string asm> {
2749 def _B : sve2_int_addsub_narrow_high_top<0b01, opc, asm, ZPR8, ZPR16>;
2750 def _H : sve2_int_addsub_narrow_high_top<0b10, opc, asm, ZPR16, ZPR32>;
2751 def _S : sve2_int_addsub_narrow_high_top<0b11, opc, asm, ZPR32, ZPR64>;
2752 }
2753
2754 class sve2_int_sat_extract_narrow_bottom tsz8_64, bits<2> opc, string asm,
2755 ZPRRegOp zprty1, ZPRRegOp zprty2>
26672756 : I<(outs zprty1:$Zd), (ins zprty2:$Zn),
26682757 asm, "\t$Zd, $Zn", "", []>, Sched<[]> {
26692758 bits<5> Zd;
26732762 let Inst{21} = 0b1;
26742763 let Inst{20-19} = tsz8_64{1-0};
26752764 let Inst{18-13} = 0b000010;
2676 let Inst{12-10} = opc;
2765 let Inst{12-11} = opc;
2766 let Inst{10} = 0b0;
26772767 let Inst{9-5} = Zn;
26782768 let Inst{4-0} = Zd;
26792769 }
26802770
2681 multiclass sve2_int_sat_extract_narrow opc, string asm> {
2682 def _B : sve2_int_sat_extract_narrow<0b001, opc, asm, ZPR8, ZPR16>;
2683 def _H : sve2_int_sat_extract_narrow<0b010, opc, asm, ZPR16, ZPR32>;
2684 def _S : sve2_int_sat_extract_narrow<0b100, opc, asm, ZPR32, ZPR64>;
2771 multiclass sve2_int_sat_extract_narrow_bottom opc, string asm> {
2772 def _B : sve2_int_sat_extract_narrow_bottom<0b001, opc, asm, ZPR8, ZPR16>;
2773 def _H : sve2_int_sat_extract_narrow_bottom<0b010, opc, asm, ZPR16, ZPR32>;
2774 def _S : sve2_int_sat_extract_narrow_bottom<0b100, opc, asm, ZPR32, ZPR64>;
2775 }
2776
2777 class sve2_int_sat_extract_narrow_top tsz8_64, bits<2> opc, string asm,
2778 ZPRRegOp zprty1, ZPRRegOp zprty2>
2779 : I<(outs zprty1:$Zd), (ins zprty1:$_Zd, zprty2:$Zn),
2780 asm, "\t$Zd, $Zn", "", []>, Sched<[]> {
2781 bits<5> Zd;
2782 bits<5> Zn;
2783 let Inst{31-23} = 0b010001010;
2784 let Inst{22} = tsz8_64{2};
2785 let Inst{21} = 0b1;
2786 let Inst{20-19} = tsz8_64{1-0};
2787 let Inst{18-13} = 0b000010;
2788 let Inst{12-11} = opc;
2789 let Inst{10} = 0b1;
2790 let Inst{9-5} = Zn;
2791 let Inst{4-0} = Zd;
2792
2793 let Constraints = "$Zd = $_Zd";
2794 }
2795
2796 multiclass sve2_int_sat_extract_narrow_top opc, string asm> {
2797 def _B : sve2_int_sat_extract_narrow_top<0b001, opc, asm, ZPR8, ZPR16>;
2798 def _H : sve2_int_sat_extract_narrow_top<0b010, opc, asm, ZPR16, ZPR32>;
2799 def _S : sve2_int_sat_extract_narrow_top<0b100, opc, asm, ZPR32, ZPR64>;
26852800 }
26862801
26872802 //===----------------------------------------------------------------------===//
38854000 (!cast(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), 0>;
38864001 }
38874002
3888 class sve2_mem_cstnt_vs_base opc, dag iops, string asm,
3889 RegisterOperand VecList>
3890 : I<(outs VecList:$Zt), iops,
4003 class sve2_mem_sstnt_vs_base opc, string asm,
4004 RegisterOperand listty, ZPRRegOp zprty>
4005 : I<(outs), (ins listty:$Zt, PPR3bAny:$Pg, zprty:$Zn, GPR64:$Rm),
38914006 asm, "\t$Zt, $Pg, [$Zn, $Rm]",
38924007 "",
38934008 []>, Sched<[]> {
39074022 let mayStore = 1;
39084023 }
39094024
3910 multiclass sve2_mem_cstnt_vs opc, string asm,
4025 multiclass sve2_mem_sstnt_vs opc, string asm,
39114026 RegisterOperand listty, ZPRRegOp zprty> {
3912 def _REAL : sve2_mem_cstnt_vs_base
3913 asm, listty>;
4027 def _REAL : sve2_mem_sstnt_vs_basety>;
39144028
39154029 def : InstAlias
39164030 (!cast(NAME # _REAL) zprty:$Zt, PPR3bAny:$Pg, zprty:$Zn, GPR64:$Rm), 0>;
39174031 def : InstAlias
39184032 (!cast(NAME # _REAL) zprty:$Zt, PPR3bAny:$Pg, zprty:$Zn, XZR), 0>;
3919 def : InstAlias
3920 (!cast(NAME # _REAL) listty:$Zt, PPR3bAny:$Pg, zprty:$Zn, GPR64:$Rm), 0>;
39214033 def : InstAlias
39224034 (!cast(NAME # _REAL) listty:$Zt, PPR3bAny:$Pg, zprty:$Zn, XZR), 1>;
39234035 }
50935205 (!cast(NAME) PPRAny:$Pt, GPR64sp:$Rn, 0), 1>;
50945206 }
50955207
5096 class sve2_mem_cldnt_vs_base opc, dag iops, string asm,
5208 class sve2_mem_gldnt_vs_base opc, dag iops, string asm,
50975209 RegisterOperand VecList>
50985210 : I<(outs VecList:$Zt), iops,
50995211 asm, "\t$Zt, $Pg/z, [$Zn, $Rm]",
51185230 let mayLoad = 1;
51195231 }
51205232
5121 multiclass sve2_mem_cldnt_vs opc, string asm,
5233 multiclass sve2_mem_gldnt_vs opc, string asm,
51225234 RegisterOperand listty, ZPRRegOp zprty> {
5123 def _REAL : sve2_mem_cldnt_vs_base
5235 def _REAL : sve2_mem_gldnt_vs_base
51245236 asm, listty>;
51255237
51265238 def : InstAlias
51275239 (!cast(NAME # _REAL) zprty:$Zt, PPR3bAny:$Pg, zprty:$Zn, GPR64:$Rm), 0>;
51285240 def : InstAlias
51295241 (!cast(NAME # _REAL) zprty:$Zt, PPR3bAny:$Pg, zprty:$Zn, XZR), 0>;
5130 def : InstAlias
5131 (!cast(NAME # _REAL) listty:$Zt, PPR3bAny:$Pg, zprty:$Zn, GPR64:$Rm), 0>;
51325242 def : InstAlias
51335243 (!cast(NAME # _REAL) listty:$Zt, PPR3bAny:$Pg, zprty:$Zn, XZR), 1>;
51345244 }
None // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+bitperm 2>&1 < %s| FileCheck %s
0 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2-bitperm 2>&1 < %s| FileCheck %s
11
22
33 // ------------------------------------------------------------------------- //
None // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+bitperm < %s \
0 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2-bitperm < %s \
11 // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
22 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
33 // RUN: | FileCheck %s --check-prefix=CHECK-ERROR
4 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+bitperm < %s \
5 // RUN: | llvm-objdump -d -mattr=+bitperm - | FileCheck %s --check-prefix=CHECK-INST
6 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+bitperm < %s \
4 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2-bitperm < %s \
5 // RUN: | llvm-objdump -d -mattr=+sve2-bitperm - | FileCheck %s --check-prefix=CHECK-INST
6 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2-bitperm < %s \
77 // RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
88
99 bdep z0.b, z1.b, z31.b
1010 // CHECK-INST: bdep z0.b, z1.b, z31.b
1111 // CHECK-ENCODING: [0x20,0xb4,0x1f,0x45]
12 // CHECK-ERROR: instruction requires: bitperm
12 // CHECK-ERROR: instruction requires: sve2-bitperm
1313 // CHECK-UNKNOWN: 20 b4 1f 45
1414
1515 bdep z0.h, z1.h, z31.h
1616 // CHECK-INST: bdep z0.h, z1.h, z31.h
1717 // CHECK-ENCODING: [0x20,0xb4,0x5f,0x45]
18 // CHECK-ERROR: instruction requires: bitperm
18 // CHECK-ERROR: instruction requires: sve2-bitperm
1919 // CHECK-UNKNOWN: 20 b4 5f 45
2020
2121 bdep z0.s, z1.s, z31.s
2222 // CHECK-INST: bdep z0.s, z1.s, z31.s
2323 // CHECK-ENCODING: [0x20,0xb4,0x9f,0x45]
24 // CHECK-ERROR: instruction requires: bitperm
24 // CHECK-ERROR: instruction requires: sve2-bitperm
2525 // CHECK-UNKNOWN: 20 b4 9f 45
2626
2727 bdep z0.d, z1.d, z31.d
2828 // CHECK-INST: bdep z0.d, z1.d, z31.d
2929 // CHECK-ENCODING: [0x20,0xb4,0xdf,0x45]
30 // CHECK-ERROR: instruction requires: bitperm
30 // CHECK-ERROR: instruction requires: sve2-bitperm
3131 // CHECK-UNKNOWN: 20 b4 df 45
None // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+bitperm 2>&1 < %s| FileCheck %s
0 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2-bitperm 2>&1 < %s| FileCheck %s
11
22
33 // ------------------------------------------------------------------------- //
None // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+bitperm < %s \
0 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2-bitperm < %s \
11 // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
22 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
33 // RUN: | FileCheck %s --check-prefix=CHECK-ERROR
4 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+bitperm < %s \
5 // RUN: | llvm-objdump -d -mattr=+bitperm - | FileCheck %s --check-prefix=CHECK-INST
6 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+bitperm < %s \
4 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2-bitperm < %s \
5 // RUN: | llvm-objdump -d -mattr=+sve2-bitperm - | FileCheck %s --check-prefix=CHECK-INST
6 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2-bitperm < %s \
77 // RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
88
99 bext z0.b, z1.b, z31.b
1010 // CHECK-INST: bext z0.b, z1.b, z31.b
1111 // CHECK-ENCODING: [0x20,0xb0,0x1f,0x45]
12 // CHECK-ERROR: instruction requires: bitperm
12 // CHECK-ERROR: instruction requires: sve2-bitperm
1313 // CHECK-UNKNOWN: 20 b0 1f 45
1414
1515 bext z0.h, z1.h, z31.h
1616 // CHECK-INST: bext z0.h, z1.h, z31.h
1717 // CHECK-ENCODING: [0x20,0xb0,0x5f,0x45]
18 // CHECK-ERROR: instruction requires: bitperm
18 // CHECK-ERROR: instruction requires: sve2-bitperm
1919 // CHECK-UNKNOWN: 20 b0 5f 45
2020
2121 bext z0.s, z1.s, z31.s
2222 // CHECK-INST: bext z0.s, z1.s, z31.s
2323 // CHECK-ENCODING: [0x20,0xb0,0x9f,0x45]
24 // CHECK-ERROR: instruction requires: bitperm
24 // CHECK-ERROR: instruction requires: sve2-bitperm
2525 // CHECK-UNKNOWN: 20 b0 9f 45
2626
2727 bext z0.d, z1.d, z31.d
2828 // CHECK-INST: bext z0.d, z1.d, z31.d
2929 // CHECK-ENCODING: [0x20,0xb0,0xdf,0x45]
30 // CHECK-ERROR: instruction requires: bitperm
30 // CHECK-ERROR: instruction requires: sve2-bitperm
3131 // CHECK-UNKNOWN: 20 b0 df 45
None // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+bitperm 2>&1 < %s| FileCheck %s
0 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2-bitperm 2>&1 < %s| FileCheck %s
11
22
33 // ------------------------------------------------------------------------- //
None // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+bitperm < %s \
0 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2-bitperm < %s \
11 // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
22 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
33 // RUN: | FileCheck %s --check-prefix=CHECK-ERROR
4 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+bitperm < %s \
5 // RUN: | llvm-objdump -d -mattr=+bitperm - | FileCheck %s --check-prefix=CHECK-INST
6 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+bitperm < %s \
4 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2-bitperm < %s \
5 // RUN: | llvm-objdump -d -mattr=+sve2-bitperm - | FileCheck %s --check-prefix=CHECK-INST
6 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2-bitperm < %s \
77 // RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
88
99 bgrp z0.b, z1.b, z31.b
1010 // CHECK-INST: bgrp z0.b, z1.b, z31.b
1111 // CHECK-ENCODING: [0x20,0xb8,0x1f,0x45]
12 // CHECK-ERROR: instruction requires: bitperm
12 // CHECK-ERROR: instruction requires: sve2-bitperm
1313 // CHECK-UNKNOWN: 20 b8 1f 45
1414
1515 bgrp z0.h, z1.h, z31.h
1616 // CHECK-INST: bgrp z0.h, z1.h, z31.h
1717 // CHECK-ENCODING: [0x20,0xb8,0x5f,0x45]
18 // CHECK-ERROR: instruction requires: bitperm
18 // CHECK-ERROR: instruction requires: sve2-bitperm
1919 // CHECK-UNKNOWN: 20 b8 5f 45
2020
2121 bgrp z0.s, z1.s, z31.s
2222 // CHECK-INST: bgrp z0.s, z1.s, z31.s
2323 // CHECK-ENCODING: [0x20,0xb8,0x9f,0x45]
24 // CHECK-ERROR: instruction requires: bitperm
24 // CHECK-ERROR: instruction requires: sve2-bitperm
2525 // CHECK-UNKNOWN: 20 b8 9f 45
2626
2727 bgrp z0.d, z1.d, z31.d
2828 // CHECK-INST: bgrp z0.d, z1.d, z31.d
2929 // CHECK-ENCODING: [0x20,0xb8,0xdf,0x45]
30 // CHECK-ERROR: instruction requires: bitperm
30 // CHECK-ERROR: instruction requires: sve2-bitperm
3131 // CHECK-UNKNOWN: 20 b8 df 45
2323 // CHECK: error: instruction requires: sve2-sha3
2424 // CHECK-NEXT: rax1 z0.d, z0.d, z0.d
2525
26 .arch armv8-a+bitperm
27 .arch armv8-a+nobitperm
26 .arch armv8-a+sve2-bitperm
27 .arch armv8-a+nosve2-bitperm
2828 bgrp z21.s, z10.s, z21.s
29 // CHECK: error: instruction requires: bitperm
29 // CHECK: error: instruction requires: sve2-bitperm
3030 // CHECK-NEXT: bgrp z21.s, z10.s, z21.s
1515 rax1 z0.d, z0.d, z0.d
1616 // CHECK: rax1 z0.d, z0.d, z0.d
1717
18 .arch armv8-a+bitperm
18 .arch armv8-a+sve2-bitperm
1919 bgrp z21.s, z10.s, z21.s
2020 // CHECK: bgrp z21.s, z10.s, z21.s
2323 // CHECK: error: instruction requires: sve2-sha3
2424 // CHECK-NEXT: rax1 z0.d, z0.d, z0.d
2525
26 .arch_extension bitperm
27 .arch_extension nobitperm
26 .arch_extension sve2-bitperm
27 .arch_extension nosve2-bitperm
2828 bgrp z21.s, z10.s, z21.s
29 // CHECK: error: instruction requires: bitperm
29 // CHECK: error: instruction requires: sve2-bitperm
3030 // CHECK-NEXT: bgrp z21.s, z10.s, z21.s
1515 rax1 z0.d, z0.d, z0.d
1616 // CHECK: rax1 z0.d, z0.d, z0.d
1717
18 .arch_extension bitperm
18 .arch_extension sve2-bitperm
1919 bgrp z21.s, z10.s, z21.s
2020 // CHECK: bgrp z21.s, z10.s, z21.s
2323 // CHECK: error: instruction requires: sve2-sha3
2424 // CHECK-NEXT: rax1 z0.d, z0.d, z0.d
2525
26 .cpu generic+bitperm
27 .cpu generic+nobitperm
26 .cpu generic+sve2-bitperm
27 .cpu generic+nosve2-bitperm
2828 bgrp z21.s, z10.s, z21.s
29 // CHECK: error: instruction requires: bitperm
29 // CHECK: error: instruction requires: sve2-bitperm
3030 // CHECK-NEXT: bgrp z21.s, z10.s, z21.s
1515 rax1 z0.d, z0.d, z0.d
1616 // CHECK: rax1 z0.d, z0.d, z0.d
1717
18 .cpu generic+bitperm
18 .cpu generic+sve2-bitperm
1919 bgrp z21.s, z10.s, z21.s
2020 // CHECK: bgrp z21.s, z10.s, z21.s
10471047 AArch64::AEK_RDM, AArch64::AEK_DOTPROD,
10481048 AArch64::AEK_SVE, AArch64::AEK_SVE2,
10491049 AArch64::AEK_SVE2AES, AArch64::AEK_SVE2SM4,
1050 AArch64::AEK_SVE2SHA3, AArch64::AEK_BITPERM,
1050 AArch64::AEK_SVE2SHA3, AArch64::AEK_SVE2BITPERM,
10511051 AArch64::AEK_RCPC, AArch64::AEK_FP16FML };
10521052
10531053 std::vector Features;
10821082 EXPECT_TRUE(std::find(B, E, "+sve2-aes") != E);
10831083 EXPECT_TRUE(std::find(B, E, "+sve2-sm4") != E);
10841084 EXPECT_TRUE(std::find(B, E, "+sve2-sha3") != E);
1085 EXPECT_TRUE(std::find(B, E, "+bitperm") != E);
1085 EXPECT_TRUE(std::find(B, E, "+sve2-bitperm") != E);
10861086 }
10871087
10881088 TEST(TargetParserTest, AArch64ArchFeatures) {
11131113 "-sve2-sm4"},
11141114 {"sve2-sha3", "nosve2-sha3", "+sve2-sha3",
11151115 "-sve2-sha3"},
1116 {"bitperm", "nobitperm", "+bitperm", "-bitperm"},
1116 {"sve2-bitperm", "nosve2-bitperm",
1117 "+sve2-bitperm", "-sve2-bitperm"},
11171118 {"dotprod", "nodotprod", "+dotprod", "-dotprod"},
11181119 {"rcpc", "norcpc", "+rcpc", "-rcpc" },
11191120 {"rng", "norng", "+rand", "-rand"},