llvm.org GIT mirror llvm / 2310900
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand. Summary: This avoids needing an isel pattern for each condition code. And it removes translation switches for converting between Jcc instructions and condition codes. Now the printer, encoder and disassembler take care of converting the immediate. We use InstAliases to handle the assembly matching. But we print using the asm string in the instruction definition. The instruction itself is marked IsCodeGenOnly=1 to hide it from the assembly parser. Reviewers: spatel, lebedev.ri, courbet, gchatelet, RKSimon Reviewed By: RKSimon Subscribers: MatzeB, qcolombet, eraman, hiraditya, arphaman, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60228 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357802 91177308-0d34-0410-b5e6-96231b3b80d8 Craig Topper 1 year, 7 months ago
114 changed file(s) with 627 addition(s) and 672 deletion(s). Raw diff Collapse all Expand all
781781 translateRegister(mcInst, insn.opcodeRegister);
782782 return false;
783783 case ENCODING_CC:
784 mcInst.addOperand(MCOperand::createImm(insn.immediates[0]));
784 mcInst.addOperand(MCOperand::createImm(insn.immediates[1]));
785785 return false;
786786 case ENCODING_FP:
787787 translateFPRegister(mcInst, insn.modRM & 7);
18461846 return -1;
18471847 break;
18481848 case ENCODING_CC:
1849 insn->immediates[0] = insn->opcode & 0xf;
1849 insn->immediates[1] = insn->opcode & 0xf;
18501850 break;
18511851 case ENCODING_FP:
18521852 break;
135135 switch (Op) {
136136 default:
137137 return Op;
138 case X86::JAE_1:
139 return (is16BitMode) ? X86::JAE_2 : X86::JAE_4;
140 case X86::JA_1:
141 return (is16BitMode) ? X86::JA_2 : X86::JA_4;
142 case X86::JBE_1:
143 return (is16BitMode) ? X86::JBE_2 : X86::JBE_4;
144 case X86::JB_1:
145 return (is16BitMode) ? X86::JB_2 : X86::JB_4;
146 case X86::JE_1:
147 return (is16BitMode) ? X86::JE_2 : X86::JE_4;
148 case X86::JGE_1:
149 return (is16BitMode) ? X86::JGE_2 : X86::JGE_4;
150 case X86::JG_1:
151 return (is16BitMode) ? X86::JG_2 : X86::JG_4;
152 case X86::JLE_1:
153 return (is16BitMode) ? X86::JLE_2 : X86::JLE_4;
154 case X86::JL_1:
155 return (is16BitMode) ? X86::JL_2 : X86::JL_4;
138 case X86::JCC_1:
139 return (is16BitMode) ? X86::JCC_2 : X86::JCC_4;
156140 case X86::JMP_1:
157141 return (is16BitMode) ? X86::JMP_2 : X86::JMP_4;
158 case X86::JNE_1:
159 return (is16BitMode) ? X86::JNE_2 : X86::JNE_4;
160 case X86::JNO_1:
161 return (is16BitMode) ? X86::JNO_2 : X86::JNO_4;
162 case X86::JNP_1:
163 return (is16BitMode) ? X86::JNP_2 : X86::JNP_4;
164 case X86::JNS_1:
165 return (is16BitMode) ? X86::JNS_2 : X86::JNS_4;
166 case X86::JO_1:
167 return (is16BitMode) ? X86::JO_2 : X86::JO_4;
168 case X86::JP_1:
169 return (is16BitMode) ? X86::JP_2 : X86::JP_4;
170 case X86::JS_1:
171 return (is16BitMode) ? X86::JS_2 : X86::JS_4;
172142 }
173143 }
174144
319319 /// the imm encoding) and the second is a 16-bit fixed value. In the AMD
320320 /// manual, this operand is described as pntr16:32 and pntr16:16
321321 RawFrmImm16 = 8,
322
323 /// AddCCFrm - This form is used for Jcc that encode the condition code
324 /// in the lower 4 bits of the opcode.
325 AddCCFrm = 9,
322326
323327 /// MRM[0-7][rm] - These forms are used to represent instructions that use
324328 /// a Mod/RM byte, and use the middle field to hold extended opcode
768772 case X86II::RawFrmSrc:
769773 case X86II::RawFrmDst:
770774 case X86II::RawFrmDstSrc:
775 case X86II::AddCCFrm:
771776 return -1;
772777 case X86II::MRMDestMem:
773778 return 0;
12721272 if ((TSFlags & X86II::OpMapMask) == X86II::ThreeDNow)
12731273 BaseOpcode = 0x0F; // Weird 3DNow! encoding.
12741274
1275 unsigned OpcodeOffset = 0;
1276
12751277 uint64_t Form = TSFlags & X86II::FormMask;
12761278 switch (Form) {
12771279 default: errs() << "FORM: " << Form << "\n";
13181320 EmitByte(BaseOpcode, CurByte, OS);
13191321 break;
13201322 }
1321 case X86II::RawFrm: {
1322 EmitByte(BaseOpcode, CurByte, OS);
1323 case X86II::AddCCFrm: {
1324 // This will be added to the opcode in the fallthrough.
1325 OpcodeOffset = MI.getOperand(NumOps - 1).getImm();
1326 assert(OpcodeOffset < 16 && "Unexpected opcode offset!");
1327 --NumOps; // Drop the operand from the end.
1328 LLVM_FALLTHROUGH;
1329 case X86II::RawFrm:
1330 EmitByte(BaseOpcode + OpcodeOffset, CurByte, OS);
13231331
13241332 if (!is64BitMode(STI) || !isPCRel32Branch(MI))
13251333 break;
688688 MBB->addSuccessor(SinkMBB);
689689
690690 // Create the conditional branch instruction.
691 BuildMI(MBB, DL, TII->get(X86::GetCondBranchFromCond(CC))).addMBB(SinkMBB);
691 BuildMI(MBB, DL, TII->get(X86::JCC_1)).addMBB(SinkMBB).addImm(CC);
692692
693693 // Add the sink block to the false block successors.
694694 FalseMBB->addSuccessor(SinkMBB);
224224 MachineInstr *BrMI;
225225 if (MBBInfo->TBB == OrigDest) {
226226 BrMI = MBBInfo->BrInstr;
227 unsigned JNCC = GetCondBranchFromCond(MBBInfo->BranchCode);
228227 MachineInstrBuilder MIB =
229 BuildMI(*MBB, BrMI, MBB->findDebugLoc(BrMI), TII->get(JNCC))
230 .addMBB(NewDest);
228 BuildMI(*MBB, BrMI, MBB->findDebugLoc(BrMI), TII->get(X86::JCC_1))
229 .addMBB(NewDest).addImm(MBBInfo->BranchCode);
231230 MBBInfo->TBB = NewDest;
232231 MBBInfo->BrInstr = MIB.getInstr();
233232 } else { // Should be the unconditional jump stmt.
253252 MachineInstr *BrMI = MBBInfo->BrInstr;
254253 X86::CondCode CC = MBBInfo->BranchCode;
255254 MachineInstrBuilder MIB = BuildMI(*MBB, BrMI, MBB->findDebugLoc(BrMI),
256 TII->get(GetCondBranchFromCond(CC)))
257 .addMBB(MBBInfo->TBB);
255 TII->get(X86::JCC_1))
256 .addMBB(MBBInfo->TBB).addImm(CC);
258257 BrMI->eraseFromParent();
259258 MBBInfo->BrInstr = MIB.getInstr();
260259
322321 llvm_unreachable("unexpected condtional code.");
323322 }
324323 BuildMI(*RootMBB, UncondBrI, RootMBB->findDebugLoc(UncondBrI),
325 TII->get(GetCondBranchFromCond(NewCC)))
326 .addMBB(RootMBBInfo->FBB);
324 TII->get(X86::JCC_1))
325 .addMBB(RootMBBInfo->FBB).addImm(NewCC);
327326
328327 // RootMBB: Jump to TargetMBB
329328 BuildMI(*RootMBB, UncondBrI, RootMBB->findDebugLoc(UncondBrI),
511510 if (I->isBranch()) {
512511 if (TBB)
513512 return nullptr;
514 CC = X86::getCondFromBranchOpc(I->getOpcode());
513 CC = X86::getCondFromBranch(*I);
515514 switch (CC) {
516515 default:
517516 return nullptr;
9999 return NewMBB;
100100 };
101101
102 auto EmitCondJump = [&](unsigned Opcode, MachineBasicBlock *ThenMBB) {
103 BuildMI(*MBB, MBBI, DL, TII->get(Opcode)).addMBB(ThenMBB);
102 auto EmitCondJump = [&](unsigned CC, MachineBasicBlock *ThenMBB) {
103 BuildMI(*MBB, MBBI, DL, TII->get(X86::JCC_1)).addMBB(ThenMBB).addImm(CC);
104104
105105 auto *ElseMBB = CreateMBB();
106106 MF->insert(InsPt, ElseMBB);
108108 MBBI = MBB->end();
109109 };
110110
111 auto EmitCondJumpTarget = [&](unsigned Opcode, unsigned Target) {
111 auto EmitCondJumpTarget = [&](unsigned CC, unsigned Target) {
112112 auto *ThenMBB = CreateMBB();
113113 TargetMBBs.push_back({ThenMBB, Target});
114 EmitCondJump(Opcode, ThenMBB);
114 EmitCondJump(CC, ThenMBB);
115115 };
116116
117117 auto EmitTailCall = [&](unsigned Target) {
128128
129129 if (NumTargets == 2) {
130130 CmpTarget(FirstTarget + 1);
131 EmitCondJumpTarget(X86::JB_1, FirstTarget);
131 EmitCondJumpTarget(X86::COND_B, FirstTarget);
132132 EmitTailCall(FirstTarget + 1);
133133 return;
134134 }
135135
136136 if (NumTargets < 6) {
137137 CmpTarget(FirstTarget + 1);
138 EmitCondJumpTarget(X86::JB_1, FirstTarget);
139 EmitCondJumpTarget(X86::JE_1, FirstTarget + 1);
138 EmitCondJumpTarget(X86::COND_B, FirstTarget);
139 EmitCondJumpTarget(X86::COND_E, FirstTarget + 1);
140140 EmitBranchFunnel(FirstTarget + 2, NumTargets - 2);
141141 return;
142142 }
143143
144144 auto *ThenMBB = CreateMBB();
145145 CmpTarget(FirstTarget + (NumTargets / 2));
146 EmitCondJump(X86::JB_1, ThenMBB);
147 EmitCondJumpTarget(X86::JE_1, FirstTarget + (NumTargets / 2));
146 EmitCondJump(X86::COND_B, ThenMBB);
147 EmitCondJumpTarget(X86::COND_E, FirstTarget + (NumTargets / 2));
148148 EmitBranchFunnel(FirstTarget + (NumTargets / 2) + 1,
149149 NumTargets - (NumTargets / 2) - 1);
150150
16891689 }
16901690
16911691 bool SwapArgs;
1692 unsigned BranchOpc;
16931692 std::tie(CC, SwapArgs) = X86::getX86ConditionCode(Predicate);
16941693 assert(CC <= X86::LAST_VALID_COND && "Unexpected condition code.");
16951694
1696 BranchOpc = X86::GetCondBranchFromCond(CC);
16971695 if (SwapArgs)
16981696 std::swap(CmpLHS, CmpRHS);
16991697
17011699 if (!X86FastEmitCompare(CmpLHS, CmpRHS, VT, CI->getDebugLoc()))
17021700 return false;
17031701
1704 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(BranchOpc))
1705 .addMBB(TrueMBB);
1702 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::JCC_1))
1703 .addMBB(TrueMBB).addImm(CC);
17061704
17071705 // X86 requires a second branch to handle UNE (and OEQ, which is mapped
17081706 // to UNE above).
17091707 if (NeedExtraBranch) {
1710 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::JP_1))
1711 .addMBB(TrueMBB);
1708 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::JCC_1))
1709 .addMBB(TrueMBB).addImm(X86::COND_P);
17121710 }
17131711
17141712 finishCondBranch(BI->getParent(), TrueMBB, FalseMBB);
17351733 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TestOpc))
17361734 .addReg(OpReg).addImm(1);
17371735
1738 unsigned JmpOpc = X86::JNE_1;
1736 unsigned JmpCond = X86::COND_NE;
17391737 if (FuncInfo.MBB->isLayoutSuccessor(TrueMBB)) {
17401738 std::swap(TrueMBB, FalseMBB);
1741 JmpOpc = X86::JE_1;
1739 JmpCond = X86::COND_E;
17421740 }
17431741
1744 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(JmpOpc))
1745 .addMBB(TrueMBB);
1742 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::JCC_1))
1743 .addMBB(TrueMBB).addImm(JmpCond);
17461744
17471745 finishCondBranch(BI->getParent(), TrueMBB, FalseMBB);
17481746 return true;
17551753 if (TmpReg == 0)
17561754 return false;
17571755
1758 unsigned BranchOpc = X86::GetCondBranchFromCond(CC);
1759
1760 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(BranchOpc))
1761 .addMBB(TrueMBB);
1756 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::JCC_1))
1757 .addMBB(TrueMBB).addImm(CC);
17621758 finishCondBranch(BI->getParent(), TrueMBB, FalseMBB);
17631759 return true;
17641760 }
17821778 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::TEST8ri))
17831779 .addReg(OpReg)
17841780 .addImm(1);
1785 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::JNE_1))
1786 .addMBB(TrueMBB);
1781 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::JCC_1))
1782 .addMBB(TrueMBB).addImm(X86::COND_NE);
17871783 finishCondBranch(BI->getParent(), TrueMBB, FalseMBB);
17881784 return true;
17891785 }
250250 "Split instruction must be in the split block!");
251251 assert(SplitI.isBranch() &&
252252 "Only designed to split a tail of branch instructions!");
253 assert(X86::getCondFromBranchOpc(SplitI.getOpcode()) != X86::COND_INVALID &&
253 assert(X86::getCondFromBranch(SplitI) != X86::COND_INVALID &&
254254 "Must split on an actual jCC instruction!");
255255
256256 // Dig out the previous instruction to the split point.
257257 MachineInstr &PrevI = *std::prev(SplitI.getIterator());
258258 assert(PrevI.isBranch() && "Must split after a branch!");
259 assert(X86::getCondFromBranchOpc(PrevI.getOpcode()) != X86::COND_INVALID &&
259 assert(X86::getCondFromBranch(PrevI) != X86::COND_INVALID &&
260260 "Must split after an actual jCC instruction!");
261261 assert(!std::prev(PrevI.getIterator())->isTerminator() &&
262262 "Must only have this one terminator prior to the split!");
586586 // branch folding or black placement. As a consequence, we get to deal
587587 // with the simpler formulation of conditional branches followed by tail
588588 // calls.
589 if (X86::getCondFromBranchOpc(MI.getOpcode()) != X86::COND_INVALID) {
589 if (X86::getCondFromBranch(MI) != X86::COND_INVALID) {
590590 auto JmpIt = MI.getIterator();
591591 do {
592592 JmpIs.push_back(&*JmpIt);
593593 ++JmpIt;
594594 } while (JmpIt != UseMBB.instr_end() &&
595 X86::getCondFromBranchOpc(JmpIt->getOpcode()) !=
595 X86::getCondFromBranch(*JmpIt) !=
596596 X86::COND_INVALID);
597597 break;
598598 }
862862 MachineBasicBlock &TestMBB, MachineBasicBlock::iterator TestPos,
863863 DebugLoc TestLoc, MachineInstr &JmpI, CondRegArray &CondRegs) {
864864 // First get the register containing this specific condition.
865 X86::CondCode Cond = X86::getCondFromBranchOpc(JmpI.getOpcode());
865 X86::CondCode Cond = X86::getCondFromBranch(JmpI);
866866 unsigned CondReg;
867867 bool Inverted;
868868 std::tie(CondReg, Inverted) =
875875
876876 // Rewrite the jump to use the !ZF flag from the test, and kill its use of
877877 // flags afterward.
878 JmpI.setDesc(TII->get(
879 X86::GetCondBranchFromCond(Inverted ? X86::COND_E : X86::COND_NE)));
880 const int ImplicitEFLAGSOpIdx = 1;
881 JmpI.getOperand(ImplicitEFLAGSOpIdx).setIsKill(true);
878 JmpI.getOperand(1).setImm(Inverted ? X86::COND_E : X86::COND_NE);
879 JmpI.findRegisterUseOperand(X86::EFLAGS)->setIsKill(true);
882880 LLVM_DEBUG(dbgs() << " fixed jCC: "; JmpI.dump());
883881 }
884882
672672 .addReg(X86::GS);
673673 BuildMI(&MBB, DL, TII.get(X86::CMP64rr)).addReg(FinalReg).addReg(LimitReg);
674674 // Jump if the desired stack pointer is at or above the stack limit.
675 BuildMI(&MBB, DL, TII.get(X86::JAE_1)).addMBB(ContinueMBB);
675 BuildMI(&MBB, DL, TII.get(X86::JCC_1)).addMBB(ContinueMBB).addImm(X86::COND_AE);
676676
677677 // Add code to roundMBB to round the final stack pointer to a page boundary.
678678 RoundMBB->addLiveIn(FinalReg);
709709 BuildMI(LoopMBB, DL, TII.get(X86::CMP64rr))
710710 .addReg(RoundedReg)
711711 .addReg(ProbeReg);
712 BuildMI(LoopMBB, DL, TII.get(X86::JNE_1)).addMBB(LoopMBB);
712 BuildMI(LoopMBB, DL, TII.get(X86::JCC_1)).addMBB(LoopMBB).addImm(X86::COND_NE);
713713
714714 MachineBasicBlock::iterator ContinueMBBI = ContinueMBB->getFirstNonPHI();
715715
24152415
24162416 // This jump is taken if SP >= (Stacklet Limit + Stack Space required).
24172417 // It jumps to normal execution of the function body.
2418 BuildMI(checkMBB, DL, TII.get(X86::JA_1)).addMBB(&PrologueMBB);
2418 BuildMI(checkMBB, DL, TII.get(X86::JCC_1)).addMBB(&PrologueMBB).addImm(X86::COND_A);
24192419
24202420 // On 32 bit we first push the arguments size and then the frame size. On 64
24212421 // bit, we pass the stack frame size in r10 and the argument size in r11.
26452645 // SPLimitOffset is in a fixed heap location (pointed by BP).
26462646 addRegOffset(BuildMI(stackCheckMBB, DL, TII.get(CMPop))
26472647 .addReg(ScratchReg), PReg, false, SPLimitOffset);
2648 BuildMI(stackCheckMBB, DL, TII.get(X86::JAE_1)).addMBB(&PrologueMBB);
2648 BuildMI(stackCheckMBB, DL, TII.get(X86::JCC_1)).addMBB(&PrologueMBB).addImm(X86::COND_AE);
26492649
26502650 // Create new MBB for IncStack:
26512651 BuildMI(incStackMBB, DL, TII.get(CALLop)).
26542654 SPReg, false, -MaxStack);
26552655 addRegOffset(BuildMI(incStackMBB, DL, TII.get(CMPop))
26562656 .addReg(ScratchReg), PReg, false, SPLimitOffset);
2657 BuildMI(incStackMBB, DL, TII.get(X86::JLE_1)).addMBB(incStackMBB);
2657 BuildMI(incStackMBB, DL, TII.get(X86::JCC_1)).addMBB(incStackMBB).addImm(X86::COND_LE);
26582658
26592659 stackCheckMBB->addSuccessor(&PrologueMBB, {99, 100});
26602660 stackCheckMBB->addSuccessor(incStackMBB, {1, 100});
23232323 static X86::CondCode getCondFromNode(SDNode *N) {
23242324 assert(N->isMachineOpcode() && "Unexpected node");
23252325 X86::CondCode CC = X86::COND_INVALID;
2326 if (CC == X86::COND_INVALID)
2327 CC = X86::getCondFromBranchOpc(N->getMachineOpcode());
2328 if (CC == X86::COND_INVALID) {
2329 unsigned Opc = N->getMachineOpcode();
2330 if (Opc == X86::SETCCr)
2331 CC = static_cast(N->getConstantOperandVal(0));
2332 else if (Opc == X86::SETCCm)
2333 CC = static_cast(N->getConstantOperandVal(5));
2334 else if (Opc == X86::CMOV16rr || Opc == X86::CMOV32rr ||
2335 Opc == X86::CMOV64rr)
2336 CC = static_cast(N->getConstantOperandVal(2));
2337 else if (Opc == X86::CMOV16rm || Opc == X86::CMOV32rm ||
2338 Opc == X86::CMOV64rm)
2339 CC = static_cast(N->getConstantOperandVal(6));
2340 }
2326 unsigned Opc = N->getMachineOpcode();
2327 if (Opc == X86::JCC_1)
2328 CC = static_cast(N->getConstantOperandVal(1));
2329 else if (Opc == X86::SETCCr)
2330 CC = static_cast(N->getConstantOperandVal(0));
2331 else if (Opc == X86::SETCCm)
2332 CC = static_cast(N->getConstantOperandVal(5));
2333 else if (Opc == X86::CMOV16rr || Opc == X86::CMOV32rr ||
2334 Opc == X86::CMOV64rr)
2335 CC = static_cast(N->getConstantOperandVal(2));
2336 else if (Opc == X86::CMOV16rm || Opc == X86::CMOV32rm ||
2337 Opc == X86::CMOV64rm)
2338 CC = static_cast(N->getConstantOperandVal(6));
23412339
23422340 return CC;
23432341 }
2842128421
2842228422 // Branch to "overflowMBB" if offset >= max
2842328423 // Fall through to "offsetMBB" otherwise
28424 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
28425 .addMBB(overflowMBB);
28424 BuildMI(thisMBB, DL, TII->get(X86::JCC_1))
28425 .addMBB(overflowMBB).addImm(X86::COND_AE);
2842628426 }
2842728427
2842828428 // In offsetMBB, emit code to use the reg_save_area.
2857928579 if (!Subtarget.isCallingConvWin64(F->getFunction().getCallingConv())) {
2858028580 // If %al is 0, branch around the XMM save block.
2858128581 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
28582 BuildMI(MBB, DL, TII->get(X86::JE_1)).addMBB(EndMBB);
28582 BuildMI(MBB, DL, TII->get(X86::JCC_1)).addMBB(EndMBB).addImm(X86::COND_E);
2858328583 MBB->addSuccessor(EndMBB);
2858428584 }
2858528585
2885928859
2886028860 // Create the conditional branch instructions.
2886128861 X86::CondCode FirstCC = X86::CondCode(FirstCMOV.getOperand(3).getImm());
28862 unsigned Opc = X86::GetCondBranchFromCond(FirstCC);
28863 BuildMI(ThisMBB, DL, TII->get(Opc)).addMBB(SinkMBB);
28862 BuildMI(ThisMBB, DL, TII->get(X86::JCC_1)).addMBB(SinkMBB).addImm(FirstCC);
2886428863
2886528864 X86::CondCode SecondCC =
2886628865 X86::CondCode(SecondCascadedCMOV.getOperand(3).getImm());
28867 unsigned Opc2 = X86::GetCondBranchFromCond(SecondCC);
28868 BuildMI(FirstInsertedMBB, DL, TII->get(Opc2)).addMBB(SinkMBB);
28866 BuildMI(FirstInsertedMBB, DL, TII->get(X86::JCC_1)).addMBB(SinkMBB).addImm(SecondCC);
2886928867
2887028868 // SinkMBB:
2887128869 // %Result = phi [ %FalseValue, SecondInsertedMBB ], [ %TrueValue, ThisMBB ]
2902129019 FalseMBB->addSuccessor(SinkMBB);
2902229020
2902329021 // Create the conditional branch instruction.
29024 unsigned Opc = X86::GetCondBranchFromCond(CC);
29025 BuildMI(ThisMBB, DL, TII->get(Opc)).addMBB(SinkMBB);
29022 BuildMI(ThisMBB, DL, TII->get(X86::JCC_1)).addMBB(SinkMBB).addImm(CC);
2902629023
2902729024 // SinkMBB:
2902829025 // %Result = phi [ %FalseValue, FalseMBB ], [ %TrueValue, ThisMBB ]
2915129148 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
2915229149 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
2915329150 .addReg(SPLimitVReg);
29154 BuildMI(BB, DL, TII->get(X86::JG_1)).addMBB(mallocMBB);
29151 BuildMI(BB, DL, TII->get(X86::JCC_1)).addMBB(mallocMBB).addImm(X86::COND_G);
2915529152
2915629153 // bumpMBB simply decreases the stack pointer, since we know the current
2915729154 // stacklet has enough space.
2977829775 BuildMI(checkSspMBB, DL, TII->get(TestRROpc))
2977929776 .addReg(SSPCopyReg)
2978029777 .addReg(SSPCopyReg);
29781 BuildMI(checkSspMBB, DL, TII->get(X86::JE_1)).addMBB(sinkMBB);
29778 BuildMI(checkSspMBB, DL, TII->get(X86::JCC_1)).addMBB(sinkMBB).addImm(X86::COND_E);
2978229779 checkSspMBB->addSuccessor(sinkMBB);
2978329780 checkSspMBB->addSuccessor(fallMBB);
2978429781
2980829805 .addReg(SSPCopyReg);
2980929806
2981029807 // Jump to sink in case PrevSSPReg <= SSPCopyReg.
29811 BuildMI(fallMBB, DL, TII->get(X86::JBE_1)).addMBB(sinkMBB);
29808 BuildMI(fallMBB, DL, TII->get(X86::JCC_1)).addMBB(sinkMBB).addImm(X86::COND_BE);
2981229809 fallMBB->addSuccessor(sinkMBB);
2981329810 fallMBB->addSuccessor(fixShadowMBB);
2981429811
2983129828 .addImm(8);
2983229829
2983329830 // Jump if the result of the shift is zero.
29834 BuildMI(fixShadowMBB, DL, TII->get(X86::JE_1)).addMBB(sinkMBB);
29831 BuildMI(fixShadowMBB, DL, TII->get(X86::JCC_1)).addMBB(sinkMBB).addImm(X86::COND_E);
2983529832 fixShadowMBB->addSuccessor(sinkMBB);
2983629833 fixShadowMBB->addSuccessor(fixShadowLoopPrepareMBB);
2983729834
2986629863 BuildMI(fixShadowLoopMBB, DL, TII->get(DecROpc), DecReg).addReg(CounterReg);
2986729864
2986829865 // Jump if the counter is not zero yet.
29869 BuildMI(fixShadowLoopMBB, DL, TII->get(X86::JNE_1)).addMBB(fixShadowLoopMBB);
29866 BuildMI(fixShadowLoopMBB, DL, TII->get(X86::JCC_1)).addMBB(fixShadowLoopMBB).addImm(X86::COND_NE);
2987029867 fixShadowLoopMBB->addSuccessor(sinkMBB);
2987129868 fixShadowLoopMBB->addSuccessor(fixShadowLoopMBB);
2987229869
3011230109 BuildMI(DispatchBB, DL, TII->get(X86::CMP32ri))
3011330110 .addReg(IReg)
3011430111 .addImm(LPadList.size());
30115 BuildMI(DispatchBB, DL, TII->get(X86::JAE_1)).addMBB(TrapBB);
30112 BuildMI(DispatchBB, DL, TII->get(X86::JCC_1)).addMBB(TrapBB).addImm(X86::COND_AE);
3011630113
3011730114 if (Subtarget.is64Bit()) {
3011830115 unsigned BReg = MRI->createVirtualRegister(&X86::GR64RegClass);
6969 }
7070
7171 // Conditional Branches.
72 let isBranch = 1, isTerminator = 1, Uses = [EFLAGS], SchedRW = [WriteJump] in {
73 multiclass ICBr opc1, bits<8> opc4, string asm, PatFrag Cond> {
74 def _1 : Ii8PCRel
75 [(X86brcond bb:$dst, Cond, EFLAGS)]>;
76 let hasSideEffects = 0, isCodeGenOnly = 1, ForceDisassemble = 1 in {
77 def _2 : Ii16PCRel
78 []>, OpSize16, TB;
79 def _4 : Ii32PCRel
80 []>, TB, OpSize32;
81 }
82 }
83 }
84
85 defm JO : ICBr<0x70, 0x80, "jo\t$dst" , X86_COND_O>;
86 defm JNO : ICBr<0x71, 0x81, "jno\t$dst", X86_COND_NO>;
87 defm JB : ICBr<0x72, 0x82, "jb\t$dst" , X86_COND_B>;
88 defm JAE : ICBr<0x73, 0x83, "jae\t$dst", X86_COND_AE>;
89 defm JE : ICBr<0x74, 0x84, "je\t$dst" , X86_COND_E>;
90 defm JNE : ICBr<0x75, 0x85, "jne\t$dst", X86_COND_NE>;
91 defm JBE : ICBr<0x76, 0x86, "jbe\t$dst", X86_COND_BE>;
92 defm JA : ICBr<0x77, 0x87, "ja\t$dst" , X86_COND_A>;
93 defm JS : ICBr<0x78, 0x88, "js\t$dst" , X86_COND_S>;
94 defm JNS : ICBr<0x79, 0x89, "jns\t$dst", X86_COND_NS>;
95 defm JP : ICBr<0x7A, 0x8A, "jp\t$dst" , X86_COND_P>;
96 defm JNP : ICBr<0x7B, 0x8B, "jnp\t$dst", X86_COND_NP>;
97 defm JL : ICBr<0x7C, 0x8C, "jl\t$dst" , X86_COND_L>;
98 defm JGE : ICBr<0x7D, 0x8D, "jge\t$dst", X86_COND_GE>;
99 defm JLE : ICBr<0x7E, 0x8E, "jle\t$dst", X86_COND_LE>;
100 defm JG : ICBr<0x7F, 0x8F, "jg\t$dst" , X86_COND_G>;
72 let isBranch = 1, isTerminator = 1, Uses = [EFLAGS], SchedRW = [WriteJump],
73 isCodeGenOnly = 1, ForceDisassemble = 1 in {
74 def JCC_1 : Ii8PCRel <0x70, AddCCFrm, (outs),
75 (ins brtarget8:$dst, ccode:$cond),
76 "j${cond}\t$dst",
77 [(X86brcond bb:$dst, imm:$cond, EFLAGS)]>;
78 let hasSideEffects = 0 in {
79 def JCC_2 : Ii16PCRel<0x80, AddCCFrm, (outs),
80 (ins brtarget16:$dst, ccode:$cond),
81 "j${cond}\t$dst",
82 []>, OpSize16, TB;
83 def JCC_4 : Ii32PCRel<0x80, AddCCFrm, (outs),
84 (ins brtarget32:$dst, ccode:$cond),
85 "j${cond}\t$dst",
86 []>, TB, OpSize32;
87 }
88 }
89
90 def : InstAlias<"jo\t$dst", (JCC_1 brtarget8:$dst, 0), 0>;
91 def : InstAlias<"jno\t$dst", (JCC_1 brtarget8:$dst, 1), 0>;
92 def : InstAlias<"jb\t$dst", (JCC_1 brtarget8:$dst, 2), 0>;
93 def : InstAlias<"jae\t$dst", (JCC_1 brtarget8:$dst, 3), 0>;
94 def : InstAlias<"je\t$dst", (JCC_1 brtarget8:$dst, 4), 0>;
95 def : InstAlias<"jne\t$dst", (JCC_1 brtarget8:$dst, 5), 0>;
96 def : InstAlias<"jbe\t$dst", (JCC_1 brtarget8:$dst, 6), 0>;
97 def : InstAlias<"ja\t$dst", (JCC_1 brtarget8:$dst, 7), 0>;
98 def : InstAlias<"js\t$dst", (JCC_1 brtarget8:$dst, 8), 0>;
99 def : InstAlias<"jns\t$dst", (JCC_1 brtarget8:$dst, 9), 0>;
100 def : InstAlias<"jp\t$dst", (JCC_1 brtarget8:$dst, 10), 0>;
101 def : InstAlias<"jnp\t$dst", (JCC_1 brtarget8:$dst, 11), 0>;
102 def : InstAlias<"jl\t$dst", (JCC_1 brtarget8:$dst, 12), 0>;
103 def : InstAlias<"jge\t$dst", (JCC_1 brtarget8:$dst, 13), 0>;
104 def : InstAlias<"jle\t$dst", (JCC_1 brtarget8:$dst, 14), 0>;
105 def : InstAlias<"jg\t$dst", (JCC_1 brtarget8:$dst, 15), 0>;
101106
102107 // jcx/jecx/jrcx instructions.
103108 let isBranch = 1, isTerminator = 1, hasSideEffects = 0, SchedRW = [WriteJump] in {
2525 def RawFrmDstSrc : Format<6>;
2626 def RawFrmImm8 : Format<7>;
2727 def RawFrmImm16 : Format<8>;
28 def AddCCFrm : Format<9>;
2829 def MRMDestMem : Format<32>;
2930 def MRMSrcMem : Format<33>;
3031 def MRMSrcMem4VOp3 : Format<34>;
19781978 return false;
19791979 }
19801980
1981 X86::CondCode X86::getCondFromBranchOpc(unsigned BrOpc) {
1982 switch (BrOpc) {
1981 X86::CondCode X86::getCondFromBranch(const MachineInstr &MI) {
1982 switch (MI.getOpcode()) {
19831983 default: return X86::COND_INVALID;
1984 case X86::JE_1: return X86::COND_E;
1985 case X86::JNE_1: return X86::COND_NE;
1986 case X86::JL_1: return X86::COND_L;
1987 case X86::JLE_1: return X86::COND_LE;
1988 case X86::JG_1: return X86::COND_G;
1989 case X86::JGE_1: return X86::COND_GE;
1990 case X86::JB_1: return X86::COND_B;
1991 case X86::JBE_1: return X86::COND_BE;
1992 case X86::JA_1: return X86::COND_A;
1993 case X86::JAE_1: return X86::COND_AE;
1994 case X86::JS_1: return X86::COND_S;
1995 case X86::JNS_1: return X86::COND_NS;
1996 case X86::JP_1: return X86::COND_P;
1997 case X86::JNP_1: return X86::COND_NP;
1998 case X86::JO_1: return X86::COND_O;
1999 case X86::JNO_1: return X86::COND_NO;
1984 case X86::JCC_1:
1985 return static_cast(
1986 MI.getOperand(MI.getDesc().getNumOperands() - 1).getImm());
20001987 }
20011988 }
20021989
20182005 case X86::CMOV16rm: case X86::CMOV32rm: case X86::CMOV64rm:
20192006 return static_cast(
20202007 MI.getOperand(MI.getDesc().getNumOperands() - 1).getImm());
2021 }
2022 }
2023
2024 unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
2025 switch (CC) {
2026 default: llvm_unreachable("Illegal condition code!");
2027 case X86::COND_E: return X86::JE_1;
2028 case X86::COND_NE: return X86::JNE_1;
2029 case X86::COND_L: return X86::JL_1;
2030 case X86::COND_LE: return X86::JLE_1;
2031 case X86::COND_G: return X86::JG_1;
2032 case X86::COND_GE: return X86::JGE_1;
2033 case X86::COND_B: return X86::JB_1;
2034 case X86::COND_BE: return X86::JBE_1;
2035 case X86::COND_A: return X86::JA_1;
2036 case X86::COND_AE: return X86::JAE_1;
2037 case X86::COND_S: return X86::JS_1;
2038 case X86::COND_NS: return X86::JNS_1;
2039 case X86::COND_P: return X86::JP_1;
2040 case X86::COND_NP: return X86::JNP_1;
2041 case X86::COND_O: return X86::JO_1;
2042 case X86::COND_NO: return X86::JNO_1;
20432008 }
20442009 }
20452010
22622227 if (!I->isBranch())
22632228 assert(0 && "Can't find the branch to replace!");
22642229
2265 X86::CondCode CC = X86::getCondFromBranchOpc(I->getOpcode());
2230 X86::CondCode CC = X86::getCondFromBranch(*I);
22662231 assert(BranchCond.size() == 1);
22672232 if (CC != BranchCond[0].getImm())
22682233 continue;
23692334 }
23702335
23712336 // Handle conditional branches.
2372 X86::CondCode BranchCode = X86::getCondFromBranchOpc(I->getOpcode());
2337 X86::CondCode BranchCode = X86::getCondFromBranch(*I);
23732338 if (BranchCode == X86::COND_INVALID)
23742339 return true; // Can't handle indirect branch.
23752340
23762341 // In practice we should never have an undef eflags operand, if we do
23772342 // abort here as we are not prepared to preserve the flag.
2378 if (I->getOperand(1).isUndef())
2343 if (I->findRegisterUseOperand(X86::EFLAGS)->isUndef())
23792344 return true;
23802345
23812346 // Working from the bottom, handle the first conditional branch.
24012366 // Which is a bit more efficient.
24022367 // We conditionally jump to the fall-through block.
24032368 BranchCode = GetOppositeBranchCondition(BranchCode);
2404 unsigned JNCC = GetCondBranchFromCond(BranchCode);
24052369 MachineBasicBlock::iterator OldInst = I;
24062370
2407 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(JNCC))
2408 .addMBB(UnCondBrIter->getOperand(0).getMBB());
2371 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JCC_1))
2372 .addMBB(UnCondBrIter->getOperand(0).getMBB())
2373 .addImm(BranchCode);
24092374 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_1))
24102375 .addMBB(TargetBB);
24112376
25702535 if (I->isDebugInstr())
25712536 continue;
25722537 if (I->getOpcode() != X86::JMP_1 &&
2573 X86::getCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
2538 X86::getCondFromBranch(*I) == X86::COND_INVALID)
25742539 break;
25752540 // Remove the branch.
25762541 I->eraseFromParent();
26092574 switch (CC) {
26102575 case X86::COND_NE_OR_P:
26112576 // Synthesize NE_OR_P with two branches.
2612 BuildMI(&MBB, DL, get(X86::JNE_1)).addMBB(TBB);
2577 BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(X86::COND_NE);
26132578 ++Count;
2614 BuildMI(&MBB, DL, get(X86::JP_1)).addMBB(TBB);
2579 BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(X86::COND_P);
26152580 ++Count;
26162581 break;
26172582 case X86::COND_E_AND_NP:
26222587 "body is a fall-through.");
26232588 }
26242589 // Synthesize COND_E_AND_NP with two branches.
2625 BuildMI(&MBB, DL, get(X86::JNE_1)).addMBB(FBB);
2590 BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(FBB).addImm(X86::COND_NE);
26262591 ++Count;
2627 BuildMI(&MBB, DL, get(X86::JNP_1)).addMBB(TBB);
2592 BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(X86::COND_NP);
26282593 ++Count;
26292594 break;
26302595 default: {
2631 unsigned Opc = GetCondBranchFromCond(CC);
2632 BuildMI(&MBB, DL, get(Opc)).addMBB(TBB);
2596 BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(CC);
26332597 ++Count;
26342598 }
26352599 }
35403504 if (IsCmpZero || IsSwapped) {
35413505 // We decode the condition code from opcode.
35423506 if (Instr.isBranch())
3543 OldCC = X86::getCondFromBranchOpc(Instr.getOpcode());
3507 OldCC = X86::getCondFromBranch(Instr);
35443508 else {
35453509 OldCC = X86::getCondFromSETCC(Instr);
35463510 if (OldCC == X86::COND_INVALID)
36473611
36483612 // Modify the condition code of instructions in OpsToUpdate.
36493613 for (auto &Op : OpsToUpdate) {
3650 if (Op.first->isBranch())
3651 Op.first->setDesc(get(GetCondBranchFromCond(Op.second)));
3652 else
3653 Op.first->getOperand(Op.first->getDesc().getNumOperands() - 1)
3654 .setImm(Op.second);
3614 Op.first->getOperand(Op.first->getDesc().getNumOperands() - 1)
3615 .setImm(Op.second);
36553616 }
36563617 return true;
36573618 }
3434 AC_EVEX_2_VEX = MachineInstr::TAsmComments
3535 };
3636
37 // Turn condition code into conditional branch opcode.
38 unsigned GetCondBranchFromCond(CondCode CC);
39
4037 /// Return a pair of condition code for the given predicate and whether
4138 /// the instruction operands should be swaped to match the condition code.
4239 std::pair getX86ConditionCode(CmpInst::Predicate Predicate);
4744 /// Return a cmov opcode for the given register size in bytes, and operand type.
4845 unsigned getCMovOpcode(unsigned RegBytes, bool HasMemoryOperand = false);
4946
50 // Turn jCC opcode into condition code.
51 CondCode getCondFromBranchOpc(unsigned Opc);
52
53 // Turn setCC opcode into condition code.
47 // Turn jCC instruction into condition code.
48 CondCode getCondFromBranch(const MachineInstr &MI);
49
50 // Turn setCC instruction into condition code.
5451 CondCode getCondFromSETCC(const MachineInstr &MI);
5552
56 // Turn CMov opcode into condition code.
53 // Turn CMov instruction into condition code.
5754 CondCode getCondFromCMov(const MachineInstr &MI);
5855
5956 /// GetOppositeBranchCondition - Return the inverse of the specified cond,
14171417 *BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::TEST8ri))
14181418 .addReg(CondReg)
14191419 .addImm(1);
1420 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::JNE_1))
1421 .addMBB(DestMBB);
1420 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::JCC_1))
1421 .addMBB(DestMBB).addImm(X86::COND_NE);
14221422
14231423 constrainSelectedInstRegOperands(TestInst, TII, TRI, RBI);
14241424
549549 case X86::TAILJMPd64:
550550 Opcode = X86::JMP_1;
551551 goto SetTailJmpOpcode;
552 case X86::TAILJMPd_CC:
553 case X86::TAILJMPd64_CC:
554 Opcode = X86::GetCondBranchFromCond(
555 static_cast(MI->getOperand(1).getImm()));
556 goto SetTailJmpOpcode;
557552
558553 SetTailJmpOpcode:
559554 MCOperand Saved = OutMI.getOperand(0);
562557 OutMI.addOperand(Saved);
563558 break;
564559 }
560
561 case X86::TAILJMPd_CC:
562 case X86::TAILJMPd64_CC: {
563 MCOperand Saved = OutMI.getOperand(0);
564 MCOperand Saved2 = OutMI.getOperand(1);
565 OutMI = MCInst();
566 OutMI.setOpcode(X86::JCC_1);
567 OutMI.addOperand(Saved);
568 OutMI.addOperand(Saved2);
569 break;
570 }
565571
566572 case X86::DEC16r:
567573 case X86::DEC32r:
144144 }
145145
146146 static JumpKind classifySecond(const MachineInstr &MI) {
147 switch (MI.getOpcode()) {
147 X86::CondCode CC = X86::getCondFromBranch(MI);
148 if (CC == X86::COND_INVALID)
149 return JumpKind::Invalid;
150
151 switch (CC) {
148152 default:
149153 return JumpKind::Invalid;
150 case X86::JE_1:
151 case X86::JNE_1:
152 case X86::JL_1:
153 case X86::JLE_1:
154 case X86::JG_1:
155 case X86::JGE_1:
154 case X86::COND_E:
155 case X86::COND_NE:
156 case X86::COND_L:
157 case X86::COND_LE:
158 case X86::COND_G:
159 case X86::COND_GE:
156160 return JumpKind::ELG;
157 case X86::JB_1:
158 case X86::JBE_1:
159 case X86::JA_1:
160 case X86::JAE_1:
161 case X86::COND_B:
162 case X86::COND_BE:
163 case X86::COND_A:
164 case X86::COND_AE:
161165 return JumpKind::AB;
162 case X86::JS_1:
163 case X86::JNS_1:
164 case X86::JP_1:
165 case X86::JNP_1:
166 case X86::JO_1:
167 case X86::JNO_1:
166 case X86::COND_S:
167 case X86::COND_NS:
168 case X86::COND_P:
169 case X86::COND_NP:
170 case X86::COND_O:
171 case X86::COND_NO:
168172 return JumpKind::SPO;
169173 }
170174 }
659659 // jmpq *%rax
660660 // ```
661661 // We still want to harden the edge to `L1`.
662 if (X86::getCondFromBranchOpc(MI.getOpcode()) == X86::COND_INVALID) {
662 if (X86::getCondFromBranch(MI) == X86::COND_INVALID) {
663663 Info.CondBrs.clear();
664664 Info.UncondBr = &MI;
665665 continue;
788788 MachineBasicBlock &Succ = *CondBr->getOperand(0).getMBB();
789789 int &SuccCount = SuccCounts[&Succ];
790790
791 X86::CondCode Cond = X86::getCondFromBranchOpc(CondBr->getOpcode());
791 X86::CondCode Cond = X86::getCondFromBranch(*CondBr);
792792 X86::CondCode InvCond = X86::GetOppositeBranchCondition(Cond);
793793 UncondCodeSeq.push_back(Cond);
794794
33 # CHECK-LABEL: name: func0
44 # CHECK: bb.0:
55 # CHECK-NOT: successors
6 # CHECK: JE_1 %bb.1, implicit undef $eflags
6 # CHECK: JCC_1 %bb.1, 4, implicit undef $eflags
77 # CHECK: JMP_1 %bb.3
88 # CHECK: bb.1:
99 # CHECK-NOT: successors
1010 # CHECK: bb.2:
1111 # CHECK-NOT: successors
12 # CHECK: JE_1 %bb.1, implicit undef $eflags
12 # CHECK: JCC_1 %bb.1, 4, implicit undef $eflags
1313 # CHECK: bb.3:
1414 # CHECK: RETQ undef $eax
1515 name: func0
1616 body: |
1717 bb.0:
18 JE_1 %bb.1, implicit undef $eflags
18 JCC_1 %bb.1, 4, implicit undef $eflags
1919 JMP_1 %bb.3
2020
2121 bb.1:
2222
2323 bb.2:
24 JE_1 %bb.1, implicit undef $eflags
24 JCC_1 %bb.1, 4, implicit undef $eflags
2525
2626 bb.3:
27 JE_1 %bb.4, implicit undef $eflags ; condjump+fallthrough to same block
27 JCC_1 %bb.4, 4, implicit undef $eflags ; condjump+fallthrough to same block
2828
2929 bb.4:
3030 RETQ undef $eax
3838 ; CHECK: bb.0:
3939 ; CHECK: successors: %bb.3, %bb.1
4040 successors: %bb.3, %bb.1 ; different order than operands
41 JE_1 %bb.1, implicit undef $eflags
41 JCC_1 %bb.1, 4, implicit undef $eflags
4242 JMP_1 %bb.3
4343
4444 bb.1:
4545 ; CHECK: bb.1:
4646 ; CHECK: successors: %bb.2, %bb.1
4747 successors: %bb.2, %bb.1 ; different order (fallthrough variant)
48 JE_1 %bb.1, implicit undef $eflags
48 JCC_1 %bb.1, 4, implicit undef $eflags
4949
5050 bb.2:
5151 ; CHECK: bb.2:
5252 ; CHECK: successors: %bb.1(0x60000000), %bb.3(0x20000000)
5353 successors: %bb.1(3), %bb.3(1) ; branch probabilities not normalized
54 JE_1 %bb.1, implicit undef $eflags
54 JCC_1 %bb.1, 4, implicit undef $eflags
5555
5656 bb.3:
5757 ; CHECK: bb.3:
2525 liveins: $edi 44
2626
2727 CMP32ri8 $edi, 10, implicit-def $eflags
28 JG_1 %bb.2.exit, implicit killed $eflags
28 JCC_1 %bb.2.exit, 15, implicit killed $eflags
2929
3030 ; CHECK: [[@LINE+1]]:8: basic block definition should be located at the start of the line
3131 less bb.1:
234234 renamable $edi = MOV32rm $rdi, 1, $noreg, 0, $noreg :: (load 4 from %ir.out)
235235 CALL64pcrel32 @foo, csr_64, implicit $rsp, implicit $ssp, implicit $edi, implicit-def $rsp, implicit-def $ssp, implicit-def $eax, debug-location !9
236236 TEST32rr renamable $eax, renamable $eax, implicit-def $eflags
237 JNS_1 %bb.2, implicit killed $eflags
238 ; CHECK: JS_1 %bb.2, implicit $eflags
237 JCC_1 %bb.2, 9, implicit killed $eflags
238 ; CHECK: JCC_1 %bb.2, 8, implicit $eflags
239239
240240 bb.1:
241241 successors: %bb.3(0x80000000)
320320 renamable $rdi = LEA64r $rsp, 1, $noreg, 4, $noreg
321321 CALL64pcrel32 @baz, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit-def $rsp, implicit-def $ssp, implicit-def $eax, debug-location !22
322322 TEST32rr renamable $eax, renamable $eax, implicit-def $eflags
323 JNS_1 %bb.2, implicit killed $eflags
324 ; CHECK: JS_1 %bb.5, implicit $eflags
323 JCC_1 %bb.2, 9, implicit killed $eflags
324 ; CHECK: JCC_1 %bb.5, 8, implicit $eflags
325325
326326 bb.1:
327327 successors: %bb.5(0x80000000)
344344 $rdi = COPY renamable $r14, debug-location !22
345345 CALL64pcrel32 @baz, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit-def $rsp, implicit-def $ssp, implicit-def $eax, debug-location !22
346346 TEST32rr renamable $eax, renamable $eax, implicit-def $eflags
347 JNS_1 %bb.6, implicit killed $eflags
347 JCC_1 %bb.6, 9, implicit killed $eflags
348348
349349 bb.4:
350350 successors: %bb.5(0x80000000)
367367 liveins: $rbx, $r14
368368
369369 CMP32mi8 $rsp, 1, $noreg, 4, $noreg, 0, implicit-def $eflags :: (dereferenceable load 4 from %ir.idx)
370 JS_1 %bb.8, implicit killed $eflags
370 JCC_1 %bb.8, 8, implicit killed $eflags
371371 JMP_1 %bb.7
372372
373373 bb.7.lor.rhs:
375375 liveins: $rbx, $r14
376376
377377 CMP32mi8 renamable $rbx, 1, $noreg, 0, $noreg, 0, implicit-def $eflags :: (load 4 from %ir.1)
378 JNE_1 %bb.3, implicit killed $eflags
378 JCC_1 %bb.3, 5, implicit killed $eflags
379379 JMP_1 %bb.8
380380
381381 bb.8.do.body.backedge:
385385 $rdi = COPY renamable $r14, debug-location !22
386386 CALL64pcrel32 @baz, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit-def $rsp, implicit-def $ssp, implicit-def $eax, debug-location !22
387387 TEST32rr renamable $eax, renamable $eax, implicit-def $eflags
388 JNS_1 %bb.6, implicit killed $eflags
388 JCC_1 %bb.6, 9, implicit killed $eflags
389389
390390 bb.9:
391391 successors: %bb.5(0x80000000)
77 body: |
88 bb.0:
99 successors: %bb.1(4), %bb.2(1)
10 JE_1 %bb.2, implicit undef $eflags
10 JCC_1 %bb.2, 4, implicit undef $eflags
1111
1212 bb.1:
1313 NOOP
7474 liveins: $ebx
7575
7676 CMP32ri8 $ebx, 10, implicit-def $eflags
77 JG_1 %bb.3.exit, implicit killed $eflags
77 JCC_1 %bb.3.exit, 15, implicit killed $eflags
7878 JMP_1 %bb.2.loop
7979
8080 bb.2.loop:
2121 successors: %bb.1.less, %bb.2.exit
2222
2323 CMP32ri8 $edi, 10, implicit-def $eflags
24 ; CHECK: [[@LINE+1]]:31: duplicate 'implicit' register flag
25 JG_1 %bb.2.exit, implicit implicit $eflags
24 ; CHECK: [[@LINE+1]]:36: duplicate 'implicit' register flag
25 JCC_1 %bb.2.exit, 15, implicit implicit $eflags
2626
2727 bb.1.less:
2828 $eax = MOV32r0 implicit-def $eflags
2525 liveins: $edi 44
2626
2727 CMP32ri8 $edi, 10, implicit-def $eflags
28 JG_1 %bb.2.exit, implicit killed $eflags
28 JCC_1 %bb.2.exit, 15, implicit killed $eflags
2929
3030 bb.1.less:
3131 $eax = MOV32r0 implicit-def dead $eflags
2222 bb.0.entry:
2323 $eax = MOV32rm $rdi, 1, _, 0, _
2424 CMP32ri8 $eax, 10, implicit-def $eflags
25 ; CHECK: [[@LINE+1]]:35: missing implicit register operand 'implicit $eflags'
26 JG_1 %bb.2.exit, implicit $eax
25 ; CHECK: [[@LINE+1]]:40: missing implicit register operand 'implicit $eflags'
26 JCC_1 %bb.2.exit, 15, implicit $eax
2727
2828 bb.1.less:
2929 $eax = MOV32r0 implicit-def $eflags
2222 bb.0.entry:
2323 $eax = MOV32rm $rdi, 1, _, 0, _
2424 CMP32ri8 $eax, 10, implicit-def $eflags
25 ; CHECK: [[@LINE+1]]:42: missing implicit register operand 'implicit $eflags'
26 JG_1 %bb.2.exit, implicit-def $eflags
25 ; CHECK: [[@LINE+1]]:47: missing implicit register operand 'implicit $eflags'
26 JCC_1 %bb.2.exit, 15, implicit-def $eflags
2727
2828 bb.1.less:
2929 $eax = MOV32r0 implicit-def $eflags
2323 liveins: $edi
2424
2525 CMP32ri8 $edi, 10, implicit-def $eflags
26 JG_1 %bb.2.exit, implicit killed $eflags
26 JCC_1 %bb.2.exit, 15, implicit killed $eflags
2727
2828 bb.1.less:
2929 $eax = MOV32r0 implicit-def dead $eflags
6666 liveins: $ebx
6767
6868 CMP32ri8 $ebx, 10, implicit-def $eflags
69 JG_1 %bb.3.exit, implicit killed $eflags
69 JCC_1 %bb.3.exit, 15, implicit killed $eflags
7070 JMP_1 %bb.2.loop
7171
7272 bb.2.loop:
2626 liveins: $edi 44
2727
2828 CMP32ri8 $edi, 10, implicit-def $eflags
29 JG_1 %bb.2.exit, implicit killed $eflags
29 JCC_1 %bb.2.exit, 15, implicit killed $eflags
3030
3131 bb.1.less:
3232 $eax = MOV32r0 implicit-def dead $eflags
2121 bb.0.entry:
2222 $eax = MOV32rm $rdi, 1, _, 0, _
2323 CMP32ri8 $eax, 10, implicit-def $eflags
24 ; CHECK: [[@LINE+1]]:14: expected a number after '%bb.'
25 JG_1 %bb.nah, implicit $eflags
24 ; CHECK: [[@LINE+1]]:15: expected a number after '%bb.'
25 JCC_1 %bb.nah, 15, implicit $eflags
2626
2727 bb.1.true:
2828 $eax = MOV32r0 implicit-def $eflags
3939 $rax = MOVSX64rr32 $edi
4040 $eax = MOV32rm $rsp, 4, $rax, 0, _
4141 CMP64rm $rcx, $rsp, 1, _, 512, _, implicit-def $eflags
42 JNE_1 %bb.2.entry, implicit $eflags
42 JCC_1 %bb.2.entry, 5, implicit $eflags
4343
4444 bb.1.entry:
4545 liveins: $eax
4646
4747 $eax = COPY $edi
4848 CMP32rr $eax, killed $esi, implicit-def $eflags
49 JL_1 %bb.2, implicit killed $eflags
49 JCC_1 %bb.2, 12, implicit killed $eflags
5050
5151 bb.1:
5252 successors: %bb.3
6464 dead $eax = MOV32r0 implicit-def dead $eflags, implicit-def $al
6565 CALL64pcrel32 @printf, csr_64, implicit $rsp, implicit $rdi, implicit $rsi, implicit $al, implicit-def $rsp, implicit-def $eax
6666 CMP64rm killed $rbx, $rsp, 1, _, 24, _, implicit-def $eflags
67 JNE_1 %bb.2.entry, implicit $eflags
67 JCC_1 %bb.2.entry, 5, implicit $eflags
6868
6969 bb.1.entry:
7070 liveins: $eax
3232 bb.0.entry:
3333 successors: %bb.1, %bb.2
3434 ; CHECK: CMP32ri8 $edi, 10, implicit-def $eflags
35 ; CHECK-NEXT: JG_1 %bb.2, implicit $eflags
35 ; CHECK-NEXT: JCC_1 %bb.2, 15, implicit $eflags
3636 CMP32ri8 $edi, 10, implicit-def $eflags
37 JG_1 %bb.2, implicit $eflags
37 JCC_1 %bb.2, 15, implicit $eflags
3838
3939 bb.1.less:
4040 ; CHECK: $eax = MOV32r0 implicit-def $eflags
7373
7474 $eax = MOV32rr $edi, implicit-def $rax
7575 CMP32ri8 $edi, 3, implicit-def $eflags
76 JA_1 %bb.2, implicit $eflags
76 JCC_1 %bb.2, 7, implicit $eflags
7777
7878 bb.1.entry:
7979 successors: %bb.3, %bb.4, %bb.5, %bb.6
116116
117117 $eax = MOV32rr $edi, implicit-def $rax
118118 CMP32ri8 $edi, 3, implicit-def $eflags
119 JA_1 %bb.2, implicit $eflags
119 JCC_1 %bb.2, 7, implicit $eflags
120120
121121 bb.1.entry:
122122 successors: %bb.3, %bb.4, %bb.5, %bb.6
4343
4444 $eax = MOV32rr $edi, implicit-def $rax
4545 CMP32ri8 $edi, 3, implicit-def $eflags
46 JA_1 %bb.2.def, implicit $eflags
46 JCC_1 %bb.2.def, 7, implicit $eflags
4747
4848 bb.1.entry:
4949 successors: %bb.3.lbl1, %bb.4.lbl2, %bb.5.lbl3, %bb.6.lbl4
2323 successors: %bb.1.less, %bb.2.exit
2424
2525 CMP32ri8 $edi, 10, implicit-def $eflags
26 JG_1 %bb.2.exit, implicit $eflags
26 JCC_1 %bb.2.exit, 15, implicit $eflags
2727
2828 bb.1.less:
2929 ; CHECK: $eax = MOV32r0
2121 bb.0.entry:
2222 $eax = MOV32rm $rdi, 1, _, 0, _
2323 CMP32ri8 $eax, 10, implicit-def $eflags
24 ; CHECK: [[@LINE+1]]:10: expected 32-bit integer (too large)
25 JG_1 %bb.123456789123456, implicit $eflags
24 ; CHECK: [[@LINE+1]]:11: expected 32-bit integer (too large)
25 JCC_1 %bb.123456789123456, 15, implicit $eflags
2626
2727 bb.1:
2828 $eax = MOV32r0 implicit-def $eflags
3939
4040 $eax = MOV32rm $rdi, 1, _, 0, _
4141 ; CHECK: CMP32ri8 $eax, 10
42 ; CHECK-NEXT: JG_1 %bb.2
42 ; CHECK-NEXT: JCC_1 %bb.2, 15
4343 CMP32ri8 $eax, 10, implicit-def $eflags
44 JG_1 %bb.2, implicit $eflags
44 JCC_1 %bb.2, 15, implicit $eflags
4545 ; CHECK: bb.1.less:
4646
4747 bb.1.less:
6060
6161 $eax = MOV32rm $rdi, 1, _, 0, _
6262 ; CHECK: CMP32ri8 $eax, 10
63 ; CHECK-NEXT: JG_1 %bb.2
63 ; CHECK-NEXT: JCC_1 %bb.2, 15
6464 CMP32ri8 $eax, 10, implicit-def $eflags
65 JG_1 %bb.3, implicit $eflags
65 JCC_1 %bb.3, 15, implicit $eflags
6666
6767 bb.1:
6868 $eax = MOV32r0 implicit-def $eflags
408408
409409 $eax = MOV32rr $edi, implicit-def $rax
410410 CMP32ri8 killed $edi, 3, implicit-def $eflags
411 JA_1 %bb.2.def, implicit killed $eflags
411 JCC_1 %bb.2.def, 7, implicit killed $eflags
412412
413413 bb.1.entry:
414414 successors: %bb.3.lbl1, %bb.4.lbl2, %bb.5.lbl3, %bb.6.lbl4
2626
2727 $eax = MOV32rm $rdi, 1, _, 0, _
2828 CMP32ri8 $eax, 10, implicit-def $eflags
29 ; CHECK: [[@LINE+1]]:20: missing implicit register operand 'implicit $eflags'
30 JG_1 %bb.2.exit
29 ; CHECK: [[@LINE+1]]:25: missing implicit register operand 'implicit $eflags'
30 JCC_1 %bb.2.exit, 15
3131
3232 bb.1.less:
3333 $eax = MOV32r0 implicit-def $eflags
3737 # CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
3838 # CHECK-NEXT: liveins: $edi
3939 # CHECK: CMP32ri8 $edi, 10, implicit-def $eflags
40 # CHECK-NEXT: JG_1 %bb.2, implicit killed $eflags
40 # CHECK-NEXT: JCC_1 %bb.2, 15, implicit killed $eflags
4141
4242 # CHECK: bb.1.less:
4343 # CHECK-NEXT: $eax = MOV32r0 implicit-def dead $eflags
5555
5656 CMP32ri8 $edi, 10, implicit-def $eflags
5757
58 JG_1 %bb.2, implicit killed $eflags
58 JCC_1 %bb.2, 15, implicit killed $eflags
5959
6060 bb.1.less:
6161
8181 # CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
8282 # CHECK-NEXT: liveins: $edi
8383 # CHECK: CMP32ri8 $edi, 10, implicit-def $eflags
84 # CHECK-NEXT: JG_1 %bb.2, implicit killed $eflags
84 # CHECK-NEXT: JCC_1 %bb.2, 15, implicit killed $eflags
8585
8686 # CHECK: bb.1.less:
8787 # CHECK-NEXT: $eax = MOV32r0 implicit-def dead $eflags
9797 successors: %bb.1, %bb.2
9898 liveins: $edi
9999 CMP32ri8 $edi, 10, implicit-def $eflags
100 JG_1 %bb.2, implicit killed $eflags
100 JCC_1 %bb.2, 15, implicit killed $eflags
101101 bb.1.less: $eax = MOV32r0 implicit-def dead $eflags
102102 RETQ killed $eax
103103
2727 liveins: $edi
2828
2929 CMP32ri8 $edi, 10, implicit-def $eflags
30 JG_1 %bb.2, implicit killed $eflags
30 JCC_1 %bb.2, 15, implicit killed $eflags
3131
3232 bb.1.less:
3333 $eax = MOV32r0 implicit-def dead $eflags
3737 liveins: $edi
3838
3939 CMP32ri8 $edi, 10, implicit-def $eflags
40 JG_1 %bb.2.exit, implicit killed $eflags
40 JCC_1 %bb.2.exit, 15, implicit killed $eflags
4141
4242 bb.1.less:
4343 $eax = MOV32r0 implicit-def dead $eflags
6363 successors: %bb.2
6464
6565 CMP32ri8 $edi, 10, implicit-def $eflags
66 JG_1 %bb.2, implicit killed $eflags
66 JCC_1 %bb.2, 15, implicit killed $eflags
6767
6868 ; Verify that we can have an empty list of successors.
6969 ; CHECK-LABEL: bb.1:
4040
4141 $eax = MOV32rr $edi, implicit-def $rax
4242 CMP32ri8 $edi, 3, implicit-def $eflags
43 JA_1 %bb.2.def, implicit $eflags
43 JCC_1 %bb.2.def, 7, implicit $eflags
4444
4545 bb.1.entry:
4646 successors: %bb.3.lbl1, %bb.4.lbl2, %bb.5.lbl3, %bb.6.lbl4
2424 bb.0.entry:
2525 $eax = MOV32rm $rdi, 1, _, 0, _
2626 CMP32ri8 $eax, 10, implicit-def $eflags
27 ; CHECK: [[@LINE+1]]:10: use of undefined machine basic block #4
28 JG_1 %bb.4, implicit $eflags
27 ; CHECK: [[@LINE+1]]:11: use of undefined machine basic block #4
28 JCC_1 %bb.4, 15, implicit $eflags
2929
3030 bb.1:
3131 $eax = MOV32r0 implicit-def $eflags
2323 bb.0.entry:
2424 $eax = MOV32rm $rdi, 1, _, 0, _
2525 CMP32ri8 $eax, 10, implicit-def $eflags
26 ; CHECK: [[@LINE+1]]:10: the name of machine basic block #2 isn't 'hit'
27 JG_1 %bb.2.hit, implicit $eflags
26 ; CHECK: [[@LINE+1]]:11: the name of machine basic block #2 isn't 'hit'
27 JCC_1 %bb.2.hit, 15, implicit $eflags
2828
2929 bb.1.less:
3030 $eax = MOV32r0 implicit-def $eflags
4747 ; CHECK-NEXT: %1:gr32 = SUB32ri8 %0, 10
4848 %0 = COPY $edi
4949 %1 = SUB32ri8 %0, 10, implicit-def $eflags
50 JG_1 %bb.2.exit, implicit $eflags
50 JCC_1 %bb.2.exit, 15, implicit $eflags
5151 JMP_1 %bb.1.less
5252
5353 bb.1.less:
8181 ; CHECK-NEXT: %1:gr32 = SUB32ri8 %0, 10
8282 %2 = COPY $edi
8383 %0 = SUB32ri8 %2, 10, implicit-def $eflags
84 JG_1 %bb.2.exit, implicit $eflags
84 JCC_1 %bb.2.exit, 15, implicit $eflags
8585 JMP_1 %bb.1.less
8686
8787 bb.1.less:
3232 # CHECK-NEXT: %3:gr32 = MOV32ri 1
3333 # CHECK-NEXT: %1:gr8 = COPY %0.sub_8bit
3434 # CHECK-NEXT: TEST8ri %1, 1, implicit-def $eflags
35 # CHECK-NEXT: JNE_1 %[[TRUE:bb.[0-9]+]], implicit $eflags
35 # CHECK-NEXT: JCC_1 %[[TRUE:bb.[0-9]+]], 5, implicit $eflags
3636 # CHECK-NEXT: JMP_1 %[[FALSE:bb.[0-9]+]]
3737 # CHECK: [[TRUE]].{{[a-zA-Z0-9]+}}:
3838 # CHECK-NEXT: $eax = COPY %2
128128 ; ALL: CMP32rr [[COPY]], [[MOV32r0_]], implicit-def $eflags
129129 ; ALL: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 15, implicit $eflags
130130 ; ALL: TEST8ri [[SETCCr]], 1, implicit-def $eflags
131 ; ALL: JNE_1 %bb.2, implicit $eflags
131 ; ALL: JCC_1 %bb.2, 5, implicit $eflags
132132 ; ALL: bb.1.cond.false:
133133 ; ALL: successors: %bb.2(0x80000000)
134134 ; ALL: bb.2.cond.end:
187187 ; ALL: CMP32rr [[COPY]], [[MOV32r0_]], implicit-def $eflags
188188 ; ALL: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 15, implicit $eflags
189189 ; ALL: TEST8ri [[SETCCr]], 1, implicit-def $eflags
190 ; ALL: JNE_1 %bb.2, implicit $eflags
190 ; ALL: JCC_1 %bb.2, 5, implicit $eflags
191191 ; ALL: bb.1.cond.false:
192192 ; ALL: successors: %bb.2(0x80000000)
193193 ; ALL: bb.2.cond.end:
242242 ; ALL: CMP32rr [[COPY]], [[MOV32r0_]], implicit-def $eflags
243243 ; ALL: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 15, implicit $eflags
244244 ; ALL: TEST8ri [[SETCCr]], 1, implicit-def $eflags
245 ; ALL: JNE_1 %bb.1, implicit $eflags
245 ; ALL: JCC_1 %bb.1, 5, implicit $eflags
246246 ; ALL: JMP_1 %bb.2
247247 ; ALL: bb.1.cond.true:
248248 ; ALL: successors: %bb.3(0x80000000)
305305 ; ALL: CMP32rr [[COPY]], [[MOV32r0_]], implicit-def $eflags
306306 ; ALL: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 15, implicit $eflags
307307 ; ALL: TEST8ri [[SETCCr]], 1, implicit-def $eflags
308 ; ALL: JNE_1 %bb.1, implicit $eflags
308 ; ALL: JCC_1 %bb.1, 5, implicit $eflags
309309 ; ALL: JMP_1 %bb.2
310310 ; ALL: bb.1.cond.true:
311311 ; ALL: successors: %bb.3(0x80000000)
377377 ; ALL: CMP32rr [[COPY]], [[MOV32r0_]], implicit-def $eflags
378378 ; ALL: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 15, implicit $eflags
379379 ; ALL: TEST8ri [[SETCCr]], 1, implicit-def $eflags
380 ; ALL: JNE_1 %bb.2, implicit $eflags
380 ; ALL: JCC_1 %bb.2, 5, implicit $eflags
381381 ; ALL: bb.1.cond.false:
382382 ; ALL: successors: %bb.2(0x80000000)
383383 ; ALL: bb.2.cond.end:
438438 ; ALL: CMP32rr [[COPY]], [[MOV32r0_]], implicit-def $eflags
439439 ; ALL: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 15, implicit $eflags
440440 ; ALL: TEST8ri [[SETCCr]], 1, implicit-def $eflags
441 ; ALL: JNE_1 %bb.2, implicit $eflags
441 ; ALL: JCC_1 %bb.2, 5, implicit $eflags
442442 ; ALL: bb.1.cond.false:
443443 ; ALL: successors: %bb.2(0x80000000)
444444 ; ALL: bb.2.cond.end:
113113
114114 %0:gr32 = COPY $edi
115115 %1:gr32 = SUB32ri8 %0, 3, implicit-def $eflags
116 JE_1 %bb.3, implicit $eflags
116 JCC_1 %bb.3, 4, implicit $eflags
117117 JMP_1 %bb.1
118118
119119 bb.1.if.then:
5959 frame-setup PUSH64r undef $rax, implicit-def $rsp, implicit $rsp
6060 CFI_INSTRUCTION def_cfa_offset 16
6161 TEST8ri $sil, 1, implicit-def $eflags, implicit killed $esi
62 JE_1 %bb.3, implicit killed $eflags
62 JCC_1 %bb.3, 4, implicit killed $eflags
6363
6464 bb.1.left:
6565 successors: %bb.2(0x7ffff800), %bb.4(0x00000800)
1515 tracksRegLiveness: true
1616 body: |
1717 bb.0:
18 JE_1 %bb.1, implicit undef $eflags
18 JCC_1 %bb.1, 4, implicit undef $eflags
1919 JMP_1 %bb.2
2020
2121 bb.1:
66 name: foo
77 body: |
88 bb.0:
9 JE_1 %bb.3, implicit $eflags
9 JCC_1 %bb.3, 4, implicit $eflags
1010 bb.1:
1111 CFI_INSTRUCTION def_cfa_offset 24
1212 bb.2:
77 body: |
88 bb.0:
99 CFI_INSTRUCTION def_cfa_offset 24
10 JNE_1 %bb.2, implicit undef $eflags
10 JCC_1 %bb.2, 5, implicit undef $eflags
1111
1212 bb.1:
1313 CFI_INSTRUCTION def_cfa_offset 32
1515 body: |
1616 bb.0:
1717 CFI_INSTRUCTION def_cfa_offset 24
18 JNE_1 %bb.2, implicit undef $eflags
18 JCC_1 %bb.2, 5, implicit undef $eflags
1919
2020 bb.1:
2121 CFI_INSTRUCTION def_cfa_offset 32
1515 body: |
1616 bb.0:
1717 CFI_INSTRUCTION def_cfa_register $rbp
18 JNE_1 %bb.2, implicit undef $eflags
18 JCC_1 %bb.2, 5, implicit undef $eflags
1919
2020 bb.1:
2121 CFI_INSTRUCTION def_cfa $rsp, 8
311311 ;
312312 ; The first two cmovs got expanded to:
313313 ; %bb.0:
314 ; JL_1 %bb.9
314 ; JCC_1 %bb.9, 12
315315 ; %bb.7:
316 ; JG_1 %bb.9
316 ; JCC_1 %bb.9, 15
317317 ; %bb.8:
318318 ; %bb.9:
319319 ; %12 = phi(%7, %bb.8, %11, %bb.0, %12, %bb.7)
104104 liveins: $edi
105105
106106 CMP32ri8 killed $edi, 2, implicit-def $eflags
107 JB_1 %bb.2, implicit $eflags
107 JCC_1 %bb.2, 2, implicit $eflags
108108 JMP_1 %bb.1
109109
110110 bb.1.entry:
111111 successors: %bb.4(0x40000000), %bb.5(0x40000000)
112112 liveins: $eflags
113113
114 JE_1 %bb.4, implicit killed $eflags
114 JCC_1 %bb.4, 4, implicit killed $eflags
115115 JMP_1 %bb.5
116116
117117 bb.2.sw.bb:
119119
120120 $al = MOV8rm $rip, 1, $noreg, @static_local_guard, $noreg :: (volatile load acquire 1 from `i8* bitcast (i64* @static_local_guard to i8*)`, align 8)
121121 TEST8rr killed $al, $al, implicit-def $eflags
122 JNE_1 %bb.6, implicit killed $eflags
122 JCC_1 %bb.6, 5, implicit killed $eflags
123123 JMP_1 %bb.3
124124
125125 bb.3.init.check.i:
7777 # CHECK: bb.10.for.body.9
7878 # CHECK: renamable $al
7979 # CHECK-NEXT: TEST8rr killed renamable $al
80 # CHECK-NEXT: JNE_1
80 # CHECK-NEXT: JCC_1
8181 # CHECK-NOT: $al = IMPLICIT_DEF
8282 # CHECK: bb.12.for.body.10
8383
9292
9393 renamable $al = MOV8ri 1
9494 TEST8rr renamable $al, renamable $al, implicit-def $eflags
95 JNE_1 %bb.4, implicit killed $eflags
95 JCC_1 %bb.4, 5, implicit killed $eflags
9696
9797 bb.1.for.cond.cleanup:
9898 successors: %bb.3, %bb.2
100100
101101 renamable $eax = MOV32rm $rsp, 1, $noreg, -16, $noreg
102102 CMP32rm killed renamable $eax, $rip, 1, $noreg, $noreg, $noreg, implicit-def $eflags
103 JBE_1 %bb.3, implicit $eflags
103 JCC_1 %bb.3, 6, implicit $eflags
104104
105105 bb.2:
106106 successors: %bb.3
116116
117117 renamable $ecx = XOR32rr undef $ecx, undef $ecx, implicit-def dead $eflags
118118 TEST8rr killed renamable $al, renamable $al, implicit-def $eflags
119 JNE_1 %bb.1, implicit $eflags
119 JCC_1 %bb.1, 5, implicit $eflags
120120
121121 bb.5.for.body.1:
122122 successors: %bb.1, %bb.6
124124
125125 renamable $al = MOV8ri 1
126126 TEST8rr killed renamable $al, renamable $al, implicit-def $eflags
127 JNE_1 %bb.1, implicit $eflags
127 JCC_1 %bb.1, 5, implicit $eflags
128128
129129 bb.6.for.body.2:
130130 successors: %bb.1, %bb.7
131131 liveins: $ecx, $eflags, $rdi
132132
133 JNE_1 %bb.1, implicit $eflags
133 JCC_1 %bb.1, 5, implicit $eflags
134134
135135 bb.7.for.body.3:
136136 successors: %bb.1, %bb.8
138138
139139 renamable $al = MOV8ri 1
140140 TEST8rr killed renamable $al, renamable $al, implicit-def $eflags
141 JNE_1 %bb.1, implicit $eflags
141 JCC_1 %bb.1, 5, implicit $eflags
142142
143143 bb.8.for.body.4:
144144 successors: %bb.1, %bb.9
145145 liveins: $ecx, $eflags, $rdi
146146
147 JNE_1 %bb.1, implicit $eflags
147 JCC_1 %bb.1, 5, implicit $eflags
148148
149149 bb.9.for.body.5:
150150 successors: %bb.1, %bb.10
152152
153153 renamable $al = MOV8ri 1
154154 TEST8rr killed renamable $al, renamable $al, implicit-def $eflags
155 JNE_1 %bb.1, implicit $eflags
155 JCC_1 %bb.1, 5, implicit $eflags
156156
157157 bb.10.for.body.6:
158158 successors: %bb.1, %bb.11
159159 liveins: $ecx, $eflags, $rdi
160160
161 JNE_1 %bb.1, implicit $eflags
161 JCC_1 %bb.1, 5, implicit $eflags
162162
163163 bb.11.for.body.7:
164164 successors: %bb.1, %bb.12
166166
167167 renamable $al = MOV8ri 1
168168 TEST8rr killed renamable $al, renamable $al, implicit-def $eflags
169 JNE_1 %bb.1, implicit $eflags
169 JCC_1 %bb.1, 5, implicit $eflags
170170
171171 bb.12.for.body.8:
172172 successors: %bb.1, %bb.13
173173 liveins: $ecx, $eflags, $rdi
174174
175 JNE_1 %bb.1, implicit $eflags
175 JCC_1 %bb.1, 5, implicit $eflags
176176
177177 bb.13.for.body.9:
178178 successors: %bb.14, %bb.15
180180
181181 renamable $al = MOV8ri 1
182182 TEST8rr killed renamable $al, renamable $al, implicit-def $eflags
183 JE_1 %bb.15, implicit $eflags
183 JCC_1 %bb.15, 4, implicit $eflags
184184
185185 bb.14:
186186 successors: %bb.1
193193 successors: %bb.16, %bb.17
194194 liveins: $eflags, $rdi
195195
196 JE_1 %bb.17, implicit killed $eflags
196 JCC_1 %bb.17, 4, implicit killed $eflags
197197
198198 bb.16:
199199 successors: %bb.1
66 ; CHECK: JMP{{.*}}%bb.4, debug-location ![[JUMPLOC:[0-9]+]]
77 ; CHECK: bb.4.entry:
88 ; CHECK: successors:
9 ; CHECK: JE{{.*}}debug-location ![[JUMPLOC]]
9 ; CHECK: JCC{{.*}}debug-location ![[JUMPLOC]]
1010 ; CHECK: JMP{{.*}}debug-location ![[JUMPLOC]]
1111
1212 define i32 @main() !dbg !12 {
122122 ; CHECK: [[COPY7:%[0-9]+]]:gr32 = COPY $edi
123123 ; CHECK: [[COPY8:%[0-9]+]]:gr8 = COPY [[COPY7]].sub_8bit
124124 ; CHECK: TEST8ri killed [[COPY8]], 1, implicit-def $eflags
125 ; CHECK: JE_1 %bb.2, implicit $eflags
125 ; CHECK: JCC_1 %bb.2, 4, implicit $eflags
126126 ; CHECK: JMP_1 %bb.1
127127 ; CHECK: bb.1.if:
128128 ; CHECK: successors: %bb.3(0x80000000)
159159 %3 = COPY $edi
160160 %11 = COPY %3.sub_8bit
161161 TEST8ri killed %11, 1, implicit-def $eflags
162 JE_1 %bb.2, implicit $eflags
162 JCC_1 %bb.2, 4, implicit $eflags
163163 JMP_1 %bb.1
164164
165165 bb.1.if:
309309
310310 ; FIXME We can't replace TEST with KTEST due to flag differences
311311 ; TEST8rr %18, %18, implicit-def $eflags
312 ; JE_1 %bb.1, implicit $eflags
312 ; JCC_1 %bb.1, 4, implicit $eflags
313313 ; JMP_1 %bb.2
314314
315315 bb.1:
426426
427427 ; FIXME We can't replace TEST with KTEST due to flag differences
428428 ; FIXME TEST16rr %17, %17, implicit-def $eflags
429 ; FIXME JE_1 %bb.1, implicit $eflags
429 ; FIXME JCC_1 %bb.1, 4, implicit $eflags
430430 ; FIXME JMP_1 %bb.2
431431
432432 bb.1:
529529
530530 ; FIXME We can't replace TEST with KTEST due to flag differences
531531 ; FIXME TEST32rr %13, %13, implicit-def $eflags
532 ; FIXME JE_1 %bb.1, implicit $eflags
532 ; FIXME JCC_1 %bb.1, 4, implicit $eflags
533533 ; FIXME JMP_1 %bb.2
534534
535535 bb.1:
632632
633633 ; FIXME We can't replace TEST with KTEST due to flag differences
634634 ; FIXME TEST64rr %13, %13, implicit-def $eflags
635 ; FIXME JE_1 %bb.1, implicit $eflags
635 ; FIXME JCC_1 %bb.1, 4, implicit $eflags
636636 ; FIXME JMP_1 %bb.2
637637
638638 bb.1:
9696 liveins: $rdi
9797
9898 TEST64rr $rdi, $rdi, implicit-def $eflags
99 JE_1 %bb.1, implicit $eflags
99 JCC_1 %bb.1, 4, implicit $eflags
100100
101101 bb.2.if.then:
102102 liveins: $rdi
127127 ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
128128
129129 $eflags = COPY %2
130 JA_1 %bb.1, implicit $eflags
131 JB_1 %bb.2, implicit $eflags
130 JCC_1 %bb.1, 7, implicit $eflags
131 JCC_1 %bb.2, 2, implicit $eflags
132132 JMP_1 %bb.3
133133 ; CHECK-NOT: $eflags =
134134 ;
135135 ; CHECK: TEST8rr %[[A_REG]], %[[A_REG]], implicit-def $eflags
136 ; CHECK-NEXT: JNE_1 %bb.1, implicit killed $eflags
136 ; CHECK-NEXT: JCC_1 %bb.1, 5, implicit killed $eflags
137137 ; CHECK-SAME: {{$[[:space:]]}}
138138 ; CHECK-NEXT: bb.4:
139139 ; CHECK-NEXT: successors: {{.*$}}
140140 ; CHECK-SAME: {{$[[:space:]]}}
141141 ; CHECK-NEXT: TEST8rr %[[B_REG]], %[[B_REG]], implicit-def $eflags
142 ; CHECK-NEXT: JNE_1 %bb.2, implicit killed $eflags
142 ; CHECK-NEXT: JCC_1 %bb.2, 5, implicit killed $eflags
143143 ; CHECK-NEXT: JMP_1 %bb.3
144144
145145 bb.1:
183183 ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
184184
185185 $eflags = COPY %2
186 JA_1 %bb.2, implicit $eflags
187 JB_1 %bb.3, implicit $eflags
186 JCC_1 %bb.2, 7, implicit $eflags
187 JCC_1 %bb.3, 2, implicit $eflags
188188 ; CHECK-NOT: $eflags =
189189 ;
190190 ; CHECK: TEST8rr %[[A_REG]], %[[A_REG]], implicit-def $eflags
191 ; CHECK-NEXT: JNE_1 %bb.2, implicit killed $eflags
191 ; CHECK-NEXT: JCC_1 %bb.2, 5, implicit killed $eflags
192192 ; CHECK-SAME: {{$[[:space:]]}}
193193 ; CHECK-NEXT: bb.4:
194194 ; CHECK-NEXT: successors: {{.*$}}
195195 ; CHECK-SAME: {{$[[:space:]]}}
196196 ; CHECK-NEXT: TEST8rr %[[B_REG]], %[[B_REG]], implicit-def $eflags
197 ; CHECK-NEXT: JNE_1 %bb.3, implicit killed $eflags
197 ; CHECK-NEXT: JCC_1 %bb.3, 5, implicit killed $eflags
198198 ; CHECK-SAME: {{$[[:space:]]}}
199199 ; CHECK-NEXT: bb.1:
200200
609609 ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
610610
611611 $eflags = COPY %2
612 JA_1 %bb.1, implicit $eflags
613 JB_1 %bb.2, implicit $eflags
612 JCC_1 %bb.1, 7, implicit $eflags
613 JCC_1 %bb.2, 2, implicit $eflags
614614 JMP_1 %bb.3
615615 ; CHECK-NOT: $eflags =
616616 ;
617617 ; CHECK: TEST8rr %[[A_REG]], %[[A_REG]], implicit-def $eflags
618 ; CHECK-NEXT: JNE_1 %bb.1, implicit killed $eflags
618 ; CHECK-NEXT: JCC_1 %bb.1, 5, implicit killed $eflags
619619 ; CHECK-SAME: {{$[[:space:]]}}
620620 ; CHECK-NEXT: bb.4:
621621 ; CHECK-NEXT: successors: {{.*$}}
622622 ; CHECK-SAME: {{$[[:space:]]}}
623623 ; CHECK-NEXT: TEST8rr %[[B_REG]], %[[B_REG]], implicit-def $eflags
624 ; CHECK-NEXT: JNE_1 %bb.2, implicit killed $eflags
624 ; CHECK-NEXT: JCC_1 %bb.2, 5, implicit killed $eflags
625625 ; CHECK-NEXT: JMP_1 %bb.3
626626
627627 bb.1:
684684 ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
685685
686686 $eflags = COPY %2
687 JA_1 %bb.1, implicit $eflags
688 JB_1 %bb.2, implicit $eflags
687 JCC_1 %bb.1, 7, implicit $eflags
688 JCC_1 %bb.2, 2, implicit $eflags
689689 JMP_1 %bb.5
690690 ; CHECK-NOT: $eflags =
691691 ;
692692 ; CHECK: TEST8rr %[[A_REG]], %[[A_REG]], implicit-def $eflags
693 ; CHECK-NEXT: JNE_1 %bb.1, implicit killed $eflags
693 ; CHECK-NEXT: JCC_1 %bb.1, 5, implicit killed $eflags
694694 ; CHECK-SAME: {{$[[:space:]]}}
695695 ; CHECK-NEXT: bb.6:
696696 ; CHECK-NEXT: successors: {{.*$}}
697697 ; CHECK-SAME: {{$[[:space:]]}}
698698 ; CHECK-NEXT: TEST8rr %[[B_REG]], %[[B_REG]], implicit-def $eflags
699 ; CHECK-NEXT: JNE_1 %bb.2, implicit killed $eflags
699 ; CHECK-NEXT: JCC_1 %bb.2, 5, implicit killed $eflags
700700 ; CHECK-NEXT: JMP_1 %bb.5
701701
702702 bb.1:
716716 successors: %bb.3, %bb.4
717717 liveins: $eflags
718718
719 JO_1 %bb.3, implicit $eflags
719 JCC_1 %bb.3, 0, implicit $eflags
720720 JMP_1 %bb.4
721721 ; CHECK-NOT: $eflags =
722722 ;
723723 ; CHECK: TEST8rr %[[O_REG]], %[[O_REG]], implicit-def $eflags
724 ; CHECK-NEXT: JNE_1 %bb.3, implicit killed $eflags
724 ; CHECK-NEXT: JCC_1 %bb.3, 5, implicit killed $eflags
725725 ; CHECK-NEXT: JMP_1 %bb.4
726726
727727 bb.3:
819819 liveins: $eflags
820820
821821 ; Outer loop header, target for one set of hoisting.
822 JE_1 %bb.2, implicit $eflags
822 JCC_1 %bb.2, 4, implicit $eflags
823823 JMP_1 %bb.4
824824 ; CHECK: bb.1:
825825 ; CHECK-NOT: COPY{{( killed)?}} $eflags
835835 ; Inner loop with a local copy. We should eliminate this but can't hoist.
836836 %2:gr64 = COPY $eflags
837837 $eflags = COPY %2
838 JE_1 %bb.2, implicit $eflags
838 JCC_1 %bb.2, 4, implicit $eflags
839839 JMP_1 %bb.3
840840 ; CHECK: bb.2:
841841 ; CHECK-NOT: COPY{{( killed)?}} $eflags
842842 ; CHECK: TEST8rr %[[E_REG]], %[[E_REG]], implicit-def $eflags
843 ; CHECK-NEXT: JNE_1 %bb.2, implicit killed $eflags
843 ; CHECK-NEXT: JCC_1 %bb.2, 5, implicit killed $eflags
844844 ; CHECK-NOT: COPY{{( killed)?}} $eflags
845845
846846 bb.3:
862862 liveins: $eflags
863863
864864 ; Another inner loop, this one with a diamond.
865 JE_1 %bb.5, implicit $eflags
865 JCC_1 %bb.5, 4, implicit $eflags
866866 JMP_1 %bb.6
867867 ; CHECK: bb.4:
868868 ; CHECK-NOT: COPY{{( killed)?}} $eflags
869869 ; CHECK: TEST8rr %[[E_REG]], %[[E_REG]], implicit-def $eflags
870 ; CHECK-NEXT: JNE_1 %bb.5, implicit killed $eflags
870 ; CHECK-NEXT: JCC_1 %bb.5, 5, implicit killed $eflags
871871 ; CHECK-NOT: COPY{{( killed)?}} $eflags
872872
873873 bb.5:
913913 liveins: $eflags
914914
915915 ; Inner loop latch.
916 JE_1 %bb.4, implicit $eflags
916 JCC_1 %bb.4, 4, implicit $eflags
917917 JMP_1 %bb.8
918918 ; CHECK: bb.7:
919919 ; CHECK-NOT: COPY{{( killed)?}} $eflags
920920 ; CHECK: TEST8rr %[[E_REG]], %[[E_REG]], implicit-def $eflags
921 ; CHECK-NEXT: JNE_1 %bb.4, implicit killed $eflags
921 ; CHECK-NEXT: JCC_1 %bb.4, 5, implicit killed $eflags
922922 ; CHECK-NOT: COPY{{( killed)?}} $eflags
923923
924924 bb.8:
927927 ; Outer loop latch. Note that we cannot have EFLAGS live-in here as that
928928 ; immediately require PHIs.
929929 CMP64rr %0, %1, implicit-def $eflags
930 JE_1 %bb.1, implicit $eflags
930 JCC_1 %bb.1, 4, implicit $eflags
931931 JMP_1 %bb.9
932932 ; CHECK: bb.8:
933933 ; CHECK-NOT: COPY{{( killed)?}} $eflags
934934 ; CHECK: CMP64rr %0, %1, implicit-def $eflags
935 ; CHECK-NEXT: JE_1 %bb.1, implicit $eflags
935 ; CHECK-NEXT: JCC_1 %bb.1, 4, implicit $eflags
936936 ; CHECK-NOT: COPY{{( killed)?}} $eflags
937937
938938 bb.9:
974974 ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
975975
976976 $eflags = COPY %4
977 JA_1 %bb.1, implicit $eflags
978 JB_1 %bb.2, implicit $eflags
977 JCC_1 %bb.1, 7, implicit $eflags
978 JCC_1 %bb.2, 2, implicit $eflags
979979 JMP_1 %bb.3
980980 ; CHECK-NOT: $eflags =
981981 ;
982982 ; CHECK: TEST8rr %[[A_REG]], %[[A_REG]], implicit-def $eflags
983 ; CHECK-NEXT: JNE_1 %bb.1, implicit killed $eflags
983 ; CHECK-NEXT: JCC_1 %bb.1, 5, implicit killed $eflags
984984 ; CHECK-SAME: {{$[[:space:]]}}
985985 ; CHECK-NEXT: bb.4:
986986 ; CHECK-NEXT: successors: {{.*$}}
987987 ; CHECK-SAME: {{$[[:space:]]}}
988988 ; CHECK-NEXT: TEST8rr %[[AE_REG]], %[[AE_REG]], implicit-def $eflags
989 ; CHECK-NEXT: JE_1 %bb.2, implicit killed $eflags
989 ; CHECK-NEXT: JCC_1 %bb.2, 4, implicit killed $eflags
990990 ; CHECK-NEXT: JMP_1 %bb.3
991991
992992 bb.1:
10351035 ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
10361036
10371037 $eflags = COPY %2
1038 JE_1 %bb.1, implicit $eflags
1038 JCC_1 %bb.1, 4, implicit $eflags
10391039 JMP_1 %bb.2
10401040 ; CHECK-NOT: $eflags =
10411041 ;
10421042 ; CHECK: TEST8rr %[[E_REG]], %[[E_REG]], implicit-def $eflags
1043 ; CHECK-NEXT: JNE_1 %bb.1, implicit killed $eflags
1043 ; CHECK-NEXT: JCC_1 %bb.1, 5, implicit killed $eflags
10441044 ; CHECK-NEXT: JMP_1 %bb.2
10451045
10461046 bb.1:
398398 liveins: $esi, $rdi
399399
400400 TEST64rr $rdi, $rdi, implicit-def $eflags
401 JE_1 %bb.3, implicit $eflags
401 JCC_1 %bb.3, 4, implicit $eflags
402402
403403 bb.1.not_null:
404404 liveins: $esi, $rdi
406406 $eax = MOV32ri 2200000
407407 $eax = AND32rm killed $eax, killed $rdi, 1, $noreg, 0, $noreg, implicit-def dead $eflags :: (load 4 from %ir.x)
408408 CMP32rr killed $eax, killed $esi, implicit-def $eflags
409 JE_1 %bb.4, implicit $eflags
409 JCC_1 %bb.4, 4, implicit $eflags
410410
411411 bb.2.ret_200:
412412 $eax = MOV32ri 200
432432 # CHECK: bb.0.entry:
433433 # CHECK: $eax = MOV32rm killed $rdx, 1, $noreg, 0, $noreg :: (volatile load 4 from %ir.ptr)
434434 # CHECK-NEXT: TEST64rr $rdi, $rdi, implicit-def $eflags
435 # CHECK-NEXT: JE_1 %bb.3, implicit $eflags
435 # CHECK-NEXT: JCC_1 %bb.3, 4, implicit $eflags
436436
437437 body: |
438438 bb.0.entry:
440440
441441 $eax = MOV32rm killed $rdx, 1, $noreg, 0, $noreg :: (volatile load 4 from %ir.ptr)
442442 TEST64rr $rdi, $rdi, implicit-def $eflags
443 JE_1 %bb.3, implicit $eflags
443 JCC_1 %bb.3, 4, implicit $eflags
444444
445445 bb.1.not_null:
446446 liveins: $esi, $rdi
448448 $eax = MOV32ri 2200000
449449 $eax = AND32rm killed $eax, killed $rdi, 1, $noreg, 0, $noreg, implicit-def dead $eflags :: (load 4 from %ir.x)
450450 CMP32rr killed $eax, killed $esi, implicit-def $eflags
451 JE_1 %bb.4, implicit $eflags
451 JCC_1 %bb.4, 4, implicit $eflags
452452
453453 bb.2.ret_200:
454454
474474 - { reg: '$esi' }
475475 # CHECK: bb.0.entry:
476476 # CHECK: TEST64rr $rdi, $rdi, implicit-def $eflags
477 # CHECK-NEXT: JE_1 %bb.3, implicit $eflags
477 # CHECK-NEXT: JCC_1 %bb.3, 4, implicit $eflags
478478
479479 body: |
480480 bb.0.entry:
481481 liveins: $esi, $rdi
482482
483483 TEST64rr $rdi, $rdi, implicit-def $eflags
484 JE_1 %bb.3, implicit $eflags
484 JCC_1 %bb.3, 4, implicit $eflags
485485
486486 bb.1.not_null:
487487 liveins: $esi, $rdi
490490 $eax = ADD32ri killed $eax, 100, implicit-def dead $eflags
491491 $eax = AND32rm killed $eax, killed $rdi, 1, $noreg, 0, $noreg, implicit-def dead $eflags :: (load 4 from %ir.x)
492492 CMP32rr killed $eax, killed $esi, implicit-def $eflags
493 JE_1 %bb.4, implicit $eflags
493 JCC_1 %bb.4, 4, implicit $eflags
494494
495495 bb.2.ret_200:
496496 $eax = MOV32ri 200
515515 - { reg: '$rsi' }
516516 # CHECK: bb.0.entry:
517517 # CHECK: TEST64rr $rdi, $rdi, implicit-def $eflags
518 # CHECK-NEXT: JE_1 %bb.3, implicit $eflags
518 # CHECK-NEXT: JCC_1 %bb.3, 4, implicit $eflags
519519
520520 body: |
521521 bb.0.entry:
522522 liveins: $rsi, $rdi
523523
524524 TEST64rr $rdi, $rdi, implicit-def $eflags
525 JE_1 %bb.3, implicit $eflags
525 JCC_1 %bb.3, 4, implicit $eflags
526526
527527 bb.1.not_null:
528528 liveins: $rsi, $rdi
530530 $rdi = MOV64ri 5000
531531 $rdi = AND64rm killed $rdi, killed $rdi, 1, $noreg, 0, $noreg, implicit-def dead $eflags :: (load 4 from %ir.x)
532532 CMP64rr killed $rdi, killed $rsi, implicit-def $eflags
533 JE_1 %bb.4, implicit $eflags
533 JCC_1 %bb.4, 4, implicit $eflags
534534
535535 bb.2.ret_200:
536536 $eax = MOV32ri 200
562562 liveins: $rsi, $rdi, $rdx
563563
564564 TEST64rr $rdi, $rdi, implicit-def $eflags
565 JE_1 %bb.3, implicit $eflags
565 JCC_1 %bb.3, 4, implicit $eflags
566566
567567 bb.1.not_null:
568568 liveins: $rsi, $rdi, $rdx
571571 $rbx = AND64rm killed $rbx, killed $rdi, 1, $noreg, 0, $noreg, implicit-def dead $eflags :: (load 4 from %ir.x)
572572 $rdx = MOV64ri 0
573573 CMP64rr killed $rbx, killed $rsi, implicit-def $eflags
574 JE_1 %bb.4, implicit $eflags
574 JCC_1 %bb.4, 4, implicit $eflags
575575
576576 bb.2.ret_200:
577577 $eax = MOV32ri 200
610610 CFI_INSTRUCTION offset $rbx, -16
611611 $rbx = MOV64rr $rdi
612612 TEST64rr $rbx, $rbx, implicit-def $eflags
613 JE_1 %bb.2, implicit killed $eflags
613 JCC_1 %bb.2, 4, implicit killed $eflags
614614
615615 bb.1.stay:
616616 liveins: $rbx
647647 liveins: $rdi, $rsi
648648
649649 TEST64rr $rdi, $rdi, implicit-def $eflags
650 JE_1 %bb.2, implicit killed $eflags
650 JCC_1 %bb.2, 4, implicit killed $eflags
651651
652652 bb.1.not_null:
653653 liveins: $rdi, $rsi
681681 liveins: $rdi, $rsi
682682
683683 TEST64rr $rdi, $rdi, implicit-def $eflags
684 JE_1 %bb.2, implicit killed $eflags
684 JCC_1 %bb.2, 4, implicit killed $eflags
685685
686686 bb.1.not_null:
687687 liveins: $rdi, $rsi
712712 liveins: $rsi, $rdi
713713
714714 TEST64rr $rdi, $rdi, implicit-def $eflags
715 JE_1 %bb.1, implicit $eflags
715 JCC_1 %bb.1, 4, implicit $eflags
716716
717717 bb.2.not_null:
718718 liveins: $rdi, $rsi
744744 liveins: $rsi, $rdi
745745
746746 TEST64rr $rdi, $rdi, implicit-def $eflags
747 JE_1 %bb.1, implicit $eflags
747 JCC_1 %bb.1, 4, implicit $eflags
748748
749749 bb.2.not_null:
750750 liveins: $rdi, $rsi
777777 liveins: $rdi, $rsi
778778
779779 TEST64rr $rdi, $rdi, implicit-def $eflags
780 JE_1 %bb.2, implicit killed $eflags
780 JCC_1 %bb.2, 4, implicit killed $eflags
781781
782782 bb.1.not_null:
783783 liveins: $rdi, $rsi
807807 liveins: $rdi, $rsi
808808
809809 TEST64rr $rdi, $rdi, implicit-def $eflags
810 JE_1 %bb.2, implicit killed $eflags
810 JCC_1 %bb.2, 4, implicit killed $eflags
811811
812812 bb.1.not_null:
813813 liveins: $rdi, $rsi
838838 liveins: $rdi, $rsi
839839
840840 TEST64rr $rdi, $rdi, implicit-def $eflags
841 JE_1 %bb.2, implicit killed $eflags
841 JCC_1 %bb.2, 4, implicit killed $eflags
842842
843843 bb.1.not_null:
844844 liveins: $rdi, $rsi
856856 # CHECK-LABEL: inc_store_with_dep_in_null
857857 # CHECK: bb.0.entry:
858858 # CHECK: TEST64rr $rdi, $rdi, implicit-def $eflags
859 # CHECK-NEXT: JE_1 %bb.2, implicit killed $eflags
860 # CHECK: bb.1.not_null
861
862 alignment: 4
863 tracksRegLiveness: true
864 liveins:
865 - { reg: '$rdi' }
866 - { reg: '$rsi' }
867 body: |
868 bb.0.entry:
869 liveins: $rdi, $rsi
870
871 TEST64rr $rdi, $rdi, implicit-def $eflags
872 JE_1 %bb.2, implicit killed $eflags
859 # CHECK-NEXT: JCC_1 %bb.2, 4, implicit killed $eflags
860 # CHECK: bb.1.not_null
861
862 alignment: 4
863 tracksRegLiveness: true
864 liveins:
865 - { reg: '$rdi' }
866 - { reg: '$rsi' }
867 body: |
868 bb.0.entry:
869 liveins: $rdi, $rsi
870
871 TEST64rr $rdi, $rdi, implicit-def $eflags
872 JCC_1 %bb.2, 4, implicit killed $eflags
873873
874874 bb.1.not_null:
875875 liveins: $rdi, $rsi
891891 # CHECK-LABEL: inc_store_with_volatile
892892 # CHECK: bb.0.entry:
893893 # CHECK: TEST64rr $rdi, $rdi, implicit-def $eflags
894 # CHECK-NEXT: JE_1 %bb.2, implicit killed $eflags
895 # CHECK: bb.1.not_null
896
897 alignment: 4
898 tracksRegLiveness: true
899 liveins:
900 - { reg: '$rdi' }
901 - { reg: '$rsi' }
902 body: |
903 bb.0.entry:
904 liveins: $rdi, $rsi
905
906 TEST64rr $rdi, $rdi, implicit-def $eflags
907 JE_1 %bb.2, implicit killed $eflags
894 # CHECK-NEXT: JCC_1 %bb.2, 4, implicit killed $eflags
895 # CHECK: bb.1.not_null
896
897 alignment: 4
898 tracksRegLiveness: true
899 liveins:
900 - { reg: '$rdi' }
901 - { reg: '$rsi' }
902 body: |
903 bb.0.entry:
904 liveins: $rdi, $rsi
905
906 TEST64rr $rdi, $rdi, implicit-def $eflags
907 JCC_1 %bb.2, 4, implicit killed $eflags
908908
909909 bb.1.not_null:
910910 liveins: $rdi, $rsi
921921 # CHECK-LABEL: inc_store_with_two_dep
922922 # CHECK: bb.0.entry:
923923 # CHECK: TEST64rr $rdi, $rdi, implicit-def $eflags
924 # CHECK-NEXT: JE_1 %bb.2, implicit killed $eflags
925 # CHECK: bb.1.not_null
926
927 alignment: 4
928 tracksRegLiveness: true
929 liveins:
930 - { reg: '$rdi' }
931 - { reg: '$rsi' }
932 body: |
933 bb.0.entry:
934 liveins: $rdi, $rsi
935
936 TEST64rr $rdi, $rdi, implicit-def $eflags
937 JE_1 %bb.2, implicit killed $eflags
924 # CHECK-NEXT: JCC_1 %bb.2, 4, implicit killed $eflags
925 # CHECK: bb.1.not_null
926
927 alignment: 4
928 tracksRegLiveness: true
929 liveins:
930 - { reg: '$rdi' }
931 - { reg: '$rsi' }
932 body: |
933 bb.0.entry:
934 liveins: $rdi, $rsi
935
936 TEST64rr $rdi, $rdi, implicit-def $eflags
937 JCC_1 %bb.2, 4, implicit killed $eflags
938938
939939 bb.1.not_null:
940940 liveins: $rdi, $rsi
953953 # CHECK-LABEL: inc_store_with_redefined_base
954954 # CHECK: bb.0.entry:
955955 # CHECK: TEST64rr $rdi, $rdi, implicit-def $eflags
956 # CHECK-NEXT: JE_1 %bb.2, implicit killed $eflags
957 # CHECK: bb.1.not_null
958
959 alignment: 4
960 tracksRegLiveness: true
961 liveins:
962 - { reg: '$rdi' }
963 - { reg: '$rsi' }
964 body: |
965 bb.0.entry:
966 liveins: $rdi, $rsi
967
968 TEST64rr $rdi, $rdi, implicit-def $eflags
969 JE_1 %bb.2, implicit killed $eflags
956 # CHECK-NEXT: JCC_1 %bb.2, 4, implicit killed $eflags
957 # CHECK: bb.1.not_null
958
959 alignment: 4
960 tracksRegLiveness: true
961 liveins:
962 - { reg: '$rdi' }
963 - { reg: '$rsi' }
964 body: |
965 bb.0.entry:
966 liveins: $rdi, $rsi
967
968 TEST64rr $rdi, $rdi, implicit-def $eflags
969 JCC_1 %bb.2, 4, implicit killed $eflags
970970
971971 bb.1.not_null:
972972 liveins: $rdi, $rsi
997997 liveins: $rdi, $rsi
998998
999999 TEST64rr $rdi, $rdi, implicit-def $eflags
1000 JE_1 %bb.2, implicit killed $eflags
1000 JCC_1 %bb.2, 4, implicit killed $eflags
10011001
10021002 bb.1.not_null:
10031003 liveins: $rdi, $rsi
10161016 # CHECK-LABEL: inc_store_across_call
10171017 # CHECK: bb.0.entry:
10181018 # CHECK: TEST64rr $rbx, $rbx, implicit-def $eflags
1019 # CHECK-NEXT: JE_1 %bb.2, implicit killed $eflags
1019 # CHECK-NEXT: JCC_1 %bb.2, 4, implicit killed $eflags
10201020 # CHECK: bb.1.not_null
10211021
10221022 alignment: 4
10361036 CFI_INSTRUCTION offset $rbx, -16
10371037 $rbx = MOV64rr killed $rdi
10381038 TEST64rr $rbx, $rbx, implicit-def $eflags
1039 JE_1 %bb.2, implicit killed $eflags
1039 JCC_1 %bb.2, 4, implicit killed $eflags
10401040
10411041 bb.1.not_null:
10421042 liveins: $rbx
10581058 # CHECK-LABEL: inc_store_with_dep_in_dep
10591059 # CHECK: bb.0.entry:
10601060 # CHECK: TEST64rr $rdi, $rdi, implicit-def $eflags
1061 # CHECK-NEXT: JE_1 %bb.2, implicit killed $eflags
1062 # CHECK: bb.1.not_null
1063
1064 alignment: 4
1065 tracksRegLiveness: true
1066 liveins:
1067 - { reg: '$rdi' }
1068 - { reg: '$rsi' }
1069 body: |
1070 bb.0.entry:
1071 liveins: $rdi, $rsi
1072
1073 TEST64rr $rdi, $rdi, implicit-def $eflags
1074 JE_1 %bb.2, implicit killed $eflags
1061 # CHECK-NEXT: JCC_1 %bb.2, 4, implicit killed $eflags
1062 # CHECK: bb.1.not_null
1063
1064 alignment: 4
1065 tracksRegLiveness: true
1066 liveins:
1067 - { reg: '$rdi' }
1068 - { reg: '$rsi' }
1069 body: |
1070 bb.0.entry:
1071 liveins: $rdi, $rsi
1072
1073 TEST64rr $rdi, $rdi, implicit-def $eflags
1074 JCC_1 %bb.2, 4, implicit killed $eflags
10751075
10761076 bb.1.not_null:
10771077 liveins: $rdi, $rsi
10911091 # CHECK-LABEL: inc_store_with_load_over_store
10921092 # CHECK: bb.0.entry:
10931093 # CHECK: TEST64rr $rdi, $rdi, implicit-def $eflags
1094 # CHECK-NEXT: JE_1 %bb.2, implicit killed $eflags
1095 # CHECK: bb.1.not_null
1096
1097 alignment: 4
1098 tracksRegLiveness: true
1099 liveins:
1100 - { reg: '$rdi' }
1101 - { reg: '$rsi' }
1102 body: |
1103 bb.0.entry:
1104 liveins: $rdi, $rsi
1105
1106 TEST64rr $rdi, $rdi, implicit-def $eflags
1107 JE_1 %bb.2, implicit killed $eflags
1094 # CHECK-NEXT: JCC_1 %bb.2, 4, implicit killed $eflags
1095 # CHECK: bb.1.not_null
1096
1097 alignment: 4
1098 tracksRegLiveness: true
1099 liveins:
1100 - { reg: '$rdi' }
1101 - { reg: '$rsi' }
1102 body: |
1103 bb.0.entry:
1104 liveins: $rdi, $rsi
1105
1106 TEST64rr $rdi, $rdi, implicit-def $eflags
1107 JCC_1 %bb.2, 4, implicit killed $eflags
11081108
11091109 bb.1.not_null:
11101110 liveins: $rdi, $rsi
11231123 # CHECK-LABEL: inc_store_with_store_over_load
11241124 # CHECK: bb.0.entry:
11251125 # CHECK: TEST64rr $rdi, $rdi, implicit-def $eflags
1126 # CHECK-NEXT: JE_1 %bb.2, implicit killed $eflags
1127 # CHECK: bb.1.not_null
1128
1129 alignment: 4
1130 tracksRegLiveness: true
1131 liveins:
1132 - { reg: '$rdi' }
1133 - { reg: '$rsi' }
1134 body: |
1135 bb.0.entry:
1136 liveins: $rdi, $rsi
1137
1138 TEST64rr $rdi, $rdi, implicit-def $eflags
1139 JE_1 %bb.2, implicit killed $eflags
1126 # CHECK-NEXT: JCC_1 %bb.2, 4, implicit killed $eflags
1127 # CHECK: bb.1.not_null
1128
1129 alignment: 4
1130 tracksRegLiveness: true
1131 liveins:
1132 - { reg: '$rdi' }
1133 - { reg: '$rsi' }
1134 body: |
1135 bb.0.entry:
1136 liveins: $rdi, $rsi
1137
1138 TEST64rr $rdi, $rdi, implicit-def $eflags
1139 JCC_1 %bb.2, 4, implicit killed $eflags
11401140
11411141 bb.1.not_null:
11421142 liveins: $rdi, $rsi
11551155 # CHECK-LABEL: inc_store_with_store_over_store
11561156 # CHECK: bb.0.entry:
11571157 # CHECK: TEST64rr $rdi, $rdi, implicit-def $eflags
1158 # CHECK-NEXT: JE_1 %bb.2, implicit killed $eflags
1159 # CHECK: bb.1.not_null
1160
1161 alignment: 4
1162 tracksRegLiveness: true
1163 liveins:
1164 - { reg: '$rdi' }
1165 - { reg: '$rsi' }
1166 body: |
1167 bb.0.entry:
1168 liveins: $rdi, $rsi
1169
1170 TEST64rr $rdi, $rdi, implicit-def $eflags
1171 JE_1 %bb.2, implicit killed $eflags
1158 # CHECK-NEXT: JCC_1 %bb.2, 4, implicit killed $eflags
1159 # CHECK: bb.1.not_null
1160
1161 alignment: 4
1162 tracksRegLiveness: true
1163 liveins:
1164 - { reg: '$rdi' }
1165 - { reg: '$rsi' }
1166 body: |
1167 bb.0.entry:
1168 liveins: $rdi, $rsi
1169
1170 TEST64rr $rdi, $rdi, implicit-def $eflags
1171 JCC_1 %bb.2, 4, implicit killed $eflags
11721172
11731173 bb.1.not_null:
11741174 liveins: $rdi, $rsi
11991199 liveins: $rdi, $rsi
12001200
12011201 TEST64rr $rdi, $rdi, implicit-def $eflags
1202 JE_1 %bb.2, implicit killed $eflags
1202 JCC_1 %bb.2, 4, implicit killed $eflags
12031203
12041204 bb.1.not_null:
12051205 liveins: $rdi, $rsi
12301230 liveins: $rdi, $rsi
12311231
12321232 TEST64rr $rdi, $rdi, implicit-def $eflags
1233 JE_1 %bb.2, implicit killed $eflags
1233 JCC_1 %bb.2, 4, implicit killed $eflags
12341234
12351235 bb.1.not_null:
12361236 liveins: $rdi, $rsi
12491249 # CHECK-LABEL: inc_store_and_load_alias
12501250 # CHECK: bb.0.entry:
12511251 # CHECK: TEST64rr $rdi, $rdi, implicit-def $eflags
1252 # CHECK-NEXT: JE_1 %bb.2, implicit killed $eflags
1253 # CHECK: bb.1.not_null
1254
1255 alignment: 4
1256 tracksRegLiveness: true
1257 liveins:
1258 - { reg: '$rdi' }
1259 - { reg: '$rsi' }
1260 body: |
1261 bb.0.entry:
1262 liveins: $rdi, $rsi
1263
1264 TEST64rr $rdi, $rdi, implicit-def $eflags
1265 JE_1 %bb.2, implicit killed $eflags
1252 # CHECK-NEXT: JCC_1 %bb.2, 4, implicit killed $eflags
1253 # CHECK: bb.1.not_null
1254
1255 alignment: 4
1256 tracksRegLiveness: true
1257 liveins:
1258 - { reg: '$rdi' }
1259 - { reg: '$rsi' }
1260 body: |
1261 bb.0.entry:
1262 liveins: $rdi, $rsi
1263
1264 TEST64rr $rdi, $rdi, implicit-def $eflags
1265 JCC_1 %bb.2, 4, implicit killed $eflags
12661266
12671267 bb.1.not_null:
12681268 liveins: $rdi, $rsi
12811281 # CHECK-LABEL: inc_spill_dep
12821282 # CHECK: bb.0.entry:
12831283 # CHECK: TEST64rr $rdi, $rdi, implicit-def $eflags
1284 # CHECK-NEXT: JE_1 %bb.2, implicit killed $eflags
1284 # CHECK-NEXT: JCC_1 %bb.2, 4, implicit killed $eflags
12851285 # CHECK: bb.1.not_null
12861286
12871287 alignment: 4
12981298 $rsp = frame-setup SUB64ri8 $rsp, 8, implicit-def dead $eflags
12991299 MOV32mr $rsp, 1, $noreg, 0, $noreg, $esi :: (store 4 into %stack.0)
13001300 TEST64rr $rdi, $rdi, implicit-def $eflags
1301 JE_1 %bb.2, implicit killed $eflags
1301 JCC_1 %bb.2, 4, implicit killed $eflags
13021302
13031303 bb.1.not_null:
13041304 liveins: $rdi, $rsi
3434 ; CHECK-LABEL: bb.0.entry
3535 ; CHECK-NOT: FAULTING_OP
3636 renamable $rdi = MOV64ri 5000
37 JE_1 %bb.2, implicit $eflags
37 JCC_1 %bb.2, 4, implicit $eflags
3838
3939 bb.1.not_null:
4040 liveins: $rdi, $rsi
1515 - { id: 0, class: gr32 }
1616 body: |
1717 bb.0:
18 JG_1 %bb.2, implicit $eflags
18 JCC_1 %bb.2, 15, implicit $eflags
1919 JMP_1 %bb.3
2020
2121 bb.2:
3737
3838 %t1:gr64 = MOV64ri32 -11
3939 CMP64ri8 %t1, 1, implicit-def $eflags
40 JE_1 %bb.2, implicit killed $eflags
40 JCC_1 %bb.2, 4, implicit killed $eflags
4141 JMP_1 %bb.1
4242
4343 bb.1:
4747 %t2:gr64 = ADD64ri8 %t2, 5, implicit-def $eflags
4848 $rax = COPY %t2
4949 CMP64ri8 %t2, 1, implicit-def $eflags
50 JE_1 %bb.1, implicit killed $eflags
50 JCC_1 %bb.1, 4, implicit killed $eflags
5151 RET 0, $rax
5252
5353 bb.2:
7878
7979 INLINEASM &"", 1, 12, implicit-def dead early-clobber $r10, 12, implicit-def dead early-clobber $r11, 12, implicit-def dead early-clobber $r12, 12, implicit-def dead early-clobber $r13, 12, implicit-def dead early-clobber $r14, 12, implicit-def dead early-clobber $r15, 12, implicit-def dead early-clobber $eflags, !3
8080 CMP32ri8 %0, 2, implicit-def $eflags
81 JE_1 %bb.6, implicit killed $eflags
81 JCC_1 %bb.6, 4, implicit killed $eflags
8282 JMP_1 %bb.2
8383
8484 bb.2.do.body:
8585 successors: %bb.5(0x19999999), %bb.3(0x66666667)
8686
8787 CMP32ri8 %0, 1, implicit-def $eflags
88 JE_1 %bb.5, implicit killed $eflags
88 JCC_1 %bb.5, 4, implicit killed $eflags
8989 JMP_1 %bb.3
9090
9191 bb.3.do.body:
9292 successors: %bb.4(0x20000000), %bb.1(0x60000000)
9393
9494 TEST32rr %0, %0, implicit-def $eflags
95 JNE_1 %bb.1, implicit killed $eflags
95 JCC_1 %bb.1, 5, implicit killed $eflags
9696 JMP_1 %bb.4
9797
9898 bb.4.sw.bb:
495495
496496 CMP32rr $eax, killed $ebx, implicit-def $eflags
497497 $ebx = LEA32r killed $eax, 4, killed $eax, 5, $noreg
498 JE_1 %bb.1, implicit $eflags
498 JCC_1 %bb.1, 4, implicit $eflags
499499 RETQ $ebx
500500 bb.1:
501501 liveins: $eax, $ebp, $ebx
951951
952952 CMP64rr $rax, killed $rbx, implicit-def $eflags
953953 $rbx = LEA64r killed $rax, 4, killed $rax, 5, $noreg
954 JE_1 %bb.1, implicit $eflags
954 JCC_1 %bb.1, 4, implicit $eflags
955955 RETQ $ebx
956956 bb.1:
957957 liveins: $rax, $rbp, $rbx
10271027
10281028 CMP64rr $rax, killed $rbx, implicit-def $eflags
10291029 $ebx = LEA64_32r killed $rax, 4, killed $rax, 5, $noreg
1030 JE_1 %bb.1, implicit $eflags
1030 JCC_1 %bb.1, 4, implicit $eflags
10311031 RETQ $ebx
10321032 bb.1:
10331033 liveins: $rax, $rbp, $rbx
101101
102102 INLINEASM &"", 1, 12, implicit-def dead early-clobber $r10, 12, implicit-def dead early-clobber $r11, 12, implicit-def dead early-clobber $r12, 12, implicit-def dead early-clobber $r13, 12, implicit-def dead early-clobber $r14, 12, implicit-def dead early-clobber $r15, 12, implicit-def dead early-clobber $eflags, !3
103103 CMP32ri8 %0, 2, implicit-def $eflags
104 JE_1 %bb.6, implicit killed $eflags
104 JCC_1 %bb.6, 4, implicit killed $eflags
105105 JMP_1 %bb.2
106106
107107 bb.2.do.body:
108108 successors: %bb.5(0x2aaaaaab), %bb.3(0x55555555)
109109
110110 CMP32ri8 %0, 1, implicit-def $eflags
111 JE_1 %bb.5, implicit killed $eflags
111 JCC_1 %bb.5, 4, implicit killed $eflags
112112 JMP_1 %bb.3
113113
114114 bb.3.do.body:
115115 successors: %bb.4, %bb.7
116116
117117 TEST32rr %0, %0, implicit-def $eflags
118 JNE_1 %bb.7, implicit killed $eflags
118 JCC_1 %bb.7, 5, implicit killed $eflags
119119 JMP_1 %bb.4
120120
121121 bb.4.sw.bb:
140140 successors: %bb.8(0x04000000), %bb.1(0x7c000000)
141141
142142 CMP32mi8 %6, 1, $noreg, 0, $noreg, 5, implicit-def $eflags :: (dereferenceable load 4 from @m, !tbaa !4)
143 JNE_1 %bb.1, implicit killed $eflags
143 JCC_1 %bb.1, 5, implicit killed $eflags
144144 JMP_1 %bb.8
145145
146146 bb.8.do.end:
44 body: |
55 bb.0:
66 CMP32ri8 $edi, 40, implicit-def $eflags
7 JNE_1 %bb.7, implicit killed $eflags
7 JCC_1 %bb.7, 5, implicit killed $eflags
88 JMP_1 %bb.1
99
1010 bb.1:
1111 CMP32ri8 $edi, 1, implicit-def $eflags
12 JNE_1 %bb.11, implicit killed $eflags
12 JCC_1 %bb.11, 5, implicit killed $eflags
1313 JMP_1 %bb.2
1414
1515 bb.2:
1616 CMP32ri8 $edi, 2, implicit-def $eflags
17 JNE_1 %bb.5, implicit killed $eflags
17 JCC_1 %bb.5, 5, implicit killed $eflags
1818 JMP_1 %bb.3
1919
2020 bb.3:
2121 CMP32ri8 $edi, 90, implicit-def $eflags
22 JNE_1 %bb.5, implicit killed $eflags
22 JCC_1 %bb.5, 5, implicit killed $eflags
2323 JMP_1 %bb.4
2424
2525 bb.4:
2626
2727 bb.5:
2828 CMP32ri8 $edi, 4, implicit-def $eflags
29 JNE_1 %bb.11, implicit killed $eflags
29 JCC_1 %bb.11, 5, implicit killed $eflags
3030 JMP_1 %bb.6
3131
3232 bb.6:
3434
3535 bb.7:
3636 CMP32ri8 $edi, 5, implicit-def $eflags
37 JE_1 %bb.9, implicit killed $eflags
37 JCC_1 %bb.9, 4, implicit killed $eflags
3838 JMP_1 %bb.8
3939
4040 bb.8:
4141
4242 bb.9:
4343 CMP32ri8 $edi, 6, implicit-def $eflags
44 JE_1 %bb.11, implicit killed $eflags
44 JCC_1 %bb.11, 4, implicit killed $eflags
4545 JMP_1 %bb.10
4646
4747 bb.10:
153153 $rsp = frame-setup SUB64ri8 $rsp, 56, implicit-def dead $eflags
154154 CALL64r undef $rax, csr_64, implicit $rsp, implicit undef $rdi, implicit undef $rsi, implicit-def $rsp, implicit-def $rax
155155 TEST64rr $rax, $rax, implicit-def $eflags
156 JNE_1 %bb.3.bb3, implicit killed $eflags
156 JCC_1 %bb.3.bb3, 5, implicit killed $eflags
157157
158158 bb.1.bb2:
159159 successors: %bb.2(0x40000000), %bb.13.bb59(0x40000000)
160160
161161 $ebp = XOR32rr undef $ebp, undef $ebp, implicit-def dead $eflags
162162 TEST8rr $bpl, $bpl, implicit-def $eflags
163 JE_1 %bb.13.bb59, implicit killed $eflags
163 JCC_1 %bb.13.bb59, 4, implicit killed $eflags
164164
165165 bb.2:
166166 successors: %bb.12.bb51(0x80000000)
193193 $ebx = MOV32rr killed $eax, implicit-def $rbx
194194 $r14d = MOV32rr $ebx, implicit-def $r14
195195 TEST8rr $sil, $sil, implicit-def $eflags
196 JNE_1 %bb.6.bb26, implicit $eflags
196 JCC_1 %bb.6.bb26, 5, implicit $eflags
197197
198198 bb.5.bb15:
199199 successors: %bb.6.bb26(0x80000000)
226226 $r13 = MOV64rm killed $rax, 1, $noreg, 768, $noreg :: (load 8 from %ir.tmp33)
227227 TEST8rr $sil, $sil, implicit-def $eflags
228228 $rax = IMPLICIT_DEF
229 JNE_1 %bb.8.bb37, implicit $eflags
229 JCC_1 %bb.8.bb37, 5, implicit $eflags
230230
231231 bb.7.bb35:
232232 successors: %bb.8.bb37(0x80000000)
243243
244244 $rcx = MOV64rm killed $rax, 1, $noreg, 760, $noreg :: (load 8 from %ir.tmp40)
245245 CMP64rr $r13, $rcx, implicit-def $eflags
246 JL_1 %bb.10.bb37, implicit $eflags
246 JCC_1 %bb.10.bb37, 12, implicit $eflags
247247
248248 bb.9.bb37:
249249 successors: %bb.10.bb37(0x80000000)
263263 $ecx = MOV32ri 6
264264 CMP32ri $eax, 15141, implicit-def $eflags
265265 $xmm0 = MOVSDrm $rsp, 1, $noreg, 40, $noreg :: (load 8 from %stack.4)
266 JL_1 %bb.4.bb7, implicit $eflags
266 JCC_1 %bb.4.bb7, 12, implicit $eflags
267267
268268 bb.11.bb51.loopexit:
269269 successors: %bb.12.bb51(0x80000000)
2929 %15:gr32 = SUB32rr %7, %14, implicit-def dead $eflags
3030 %10:gr64_nosp = SUBREG_TO_REG 0, %15, %subreg.sub_32bit
3131 %16:gr32 = SUB32ri8 %15, 3, implicit-def $eflags
32 JA_1 %bb.8, implicit $eflags
32 JCC_1 %bb.8, 7, implicit $eflags
3333
3434 bb.9:
3535 JMP64m $noreg, 8, %10, %jump-table.0, $noreg :: (load 8 from jump-table)
101101 %0 = PHI %5, %bb.0, %3, %bb.5
102102 %6 = MOV32ri 1
103103 TEST32rr %4, %4, implicit-def $eflags
104 JE_1 %bb.3, implicit $eflags
104 JCC_1 %bb.3, 4, implicit $eflags
105105 JMP_1 %bb.2
106106
107107 bb.2.bb3:
114114
115115 %1 = PHI %6, %bb.1, %7, %bb.2
116116 TEST32rr %1, %1, implicit-def $eflags
117 JE_1 %bb.5, implicit $eflags
117 JCC_1 %bb.5, 4, implicit $eflags
118118 JMP_1 %bb.4
119119
120120 bb.4.bb6:
135135 ; CHECK-SAME: %10,
136136 ; CHECK-SAME: %2,
137137 %11 = SUB32ri8 %3, 10, implicit-def $eflags
138 JL_1 %bb.1, implicit $eflags
138 JCC_1 %bb.1, 12, implicit $eflags
139139 JMP_1 %bb.6
140140
141141 bb.6.bb8:
185185 ; CHECK: %0:gr32 = PHI %6, %bb.0, %3, %bb.5
186186 %7 = MOV32ri 1
187187 TEST32rr %4, %4, implicit-def $eflags
188 JE_1 %bb.3, implicit $eflags
188 JCC_1 %bb.3, 4, implicit $eflags
189189 JMP_1 %bb.2
190190
191191 bb.2.bb3:
198198
199199 %1 = PHI %7, %bb.1, %8, %bb.2
200200 TEST32rr %1, %1, implicit-def $eflags
201 JE_1 %bb.5, implicit $eflags
201 JCC_1 %bb.5, 4, implicit $eflags
202202 JMP_1 %bb.4
203203
204204 bb.4.bb6:
220220 ; CHECK-SAME: %2,
221221 ; CHECK-SAME: %11,
222222 %12 = SUB32ri8 %3, 10, implicit-def $eflags
223 JL_1 %bb.1, implicit $eflags
223 JCC_1 %bb.1, 12, implicit $eflags
224224 JMP_1 %bb.6
225225
226226 bb.6.bb8:
292292 $rcx = OR64rr killed $rcx, killed $rsi, implicit-def dead $eflags
293293 $rdx = MOVSX64rm32 $rbx, 1, $noreg, 0, $noreg :: (load 4, align 8)
294294 TEST32mr killed $rcx, 4, killed $rdx, 0, $noreg, killed $eax, implicit-def $eflags :: (load 4)
295 JNE_1 %bb.2, implicit $eflags
295 JCC_1 %bb.2, 5, implicit $eflags
296296 JMP_1 %bb.3
297297
298298 bb.1:
312312 $eax = LEA64_32r killed $rax, 1, killed $rcx, -1, $noreg
313313 $eax = SAR32r1 killed $eax, implicit-def dead $eflags
314314 CMP32mr $rbx, 1, $noreg, 0, $noreg, killed $eax, implicit-def $eflags :: (load 4, align 8), (load 4, align 8)
315 JG_1 %bb.1, implicit killed $eflags
315 JCC_1 %bb.1, 15, implicit killed $eflags
316316
317317 bb.3:
318318 liveins: $rbp
7474 renamable $eax = COPY $edi
7575 DBG_VALUE $eax, $noreg, !14, !DIExpression(), debug-location !16
7676 CMP32mi8 $rip, 1, $noreg, @x0, $noreg, 0, implicit-def $eflags, debug-location !16
77 JE_1 %bb.2, implicit killed $eflags, debug-location !16
77 JCC_1 %bb.2, 4, implicit killed $eflags, debug-location !16
7878 JMP_1 %bb.1, debug-location !16
7979
8080 bb.1:
6060 $cl = AND8rr killed $cl, killed $bl, implicit-def dead $eflags
6161 CMP32ri8 $ebp, -1, implicit-def $eflags
6262 $edx = MOV32ri 0
63 JE_1 %bb.3, implicit $eflags
63 JCC_1 %bb.3, 4, implicit $eflags
6464
6565 bb.2:
6666 liveins: $cl, $eax, $ebp, $esi
7676 renamable $eax = MOV32r0 implicit-def dead $eflags
7777 DBG_VALUE $ebx, $noreg, !21, !DIExpression()
7878 CMP32ri $edi, 255, implicit-def $eflags
79 JG_1 %bb.2, implicit killed $eflags
79 JCC_1 %bb.2, 15, implicit killed $eflags
8080 JMP_1 %bb.1
8181
8282 bb.1.if.end:
4242 # CHECK: [[L1:bb.3]].{{[a-zA-Z0-9.]+}}:
4343 # CHECK: %[[REGA:.*]] = COPY %[[REGB:.*]]
4444 # CHECK-NOT: %[[REGB]] = COPY %[[REGA]]
45 # CHECK: JNE_1 %[[L1]]
45 # CHECK: JCC_1 %[[L1]], 5
4646
4747 name: foo
4848 alignment: 4
8686 %12 = MOV8rm %0, 1, $noreg, 0, $noreg :: (load 1 from %ir.t0)
8787 TEST8rr %12, %12, implicit-def $eflags
8888 %11 = MOV32rm $rip, 1, $noreg, @a, $noreg :: (dereferenceable load 4 from @a)
89 JNE_1 %bb.1, implicit killed $eflags
89 JCC_1 %bb.1, 5, implicit killed $eflags
9090
9191 bb.4:
9292 %10 = COPY %11
104104 %12 = MOV8rm %0, 1, $noreg, 0, $noreg :: (load 1 from %ir.t0)
105105 TEST8rr %12, %12, implicit-def $eflags
106106 %11 = COPY %10
107 JNE_1 %bb.2, implicit killed $eflags
107 JCC_1 %bb.2, 5, implicit killed $eflags
108108 JMP_1 %bb.3
109109
110110 bb.3.while.end:
111111
112112 %13:gr32_abcd = MOV32r0 implicit-def dead $eflags
113113 TEST8rr %13.sub_8bit, %13.sub_8bit, implicit-def $eflags
114 JNE_1 %bb.2, implicit killed $eflags
114 JCC_1 %bb.2, 5, implicit killed $eflags
115115 JMP_1 %bb.1
116116
117117 bb.1:
123123
124124 %15:gr32_abcd = MOV32r0 implicit-def dead $eflags
125125 TEST8rr %15.sub_8bit, %15.sub_8bit, implicit-def $eflags
126 JNE_1 %bb.4, implicit killed $eflags
126 JCC_1 %bb.4, 5, implicit killed $eflags
127127 JMP_1 %bb.3
128128
129129 bb.3:
138138 MOV32mr undef %17:gr32, 1, $noreg, 0, $noreg, %1
139139 %18:gr32_abcd = MOV32r0 implicit-def dead $eflags
140140 TEST8rr %18.sub_8bit, %18.sub_8bit, implicit-def $eflags
141 JNE_1 %bb.6, implicit killed $eflags
141 JCC_1 %bb.6, 5, implicit killed $eflags
142142 JMP_1 %bb.5
143143
144144 bb.5:
150150
151151 %20:gr32_abcd = MOV32r0 implicit-def dead $eflags
152152 TEST8rr %20.sub_8bit, %20.sub_8bit, implicit-def $eflags
153 JNE_1 %bb.8, implicit killed $eflags
153 JCC_1 %bb.8, 5, implicit killed $eflags
154154 JMP_1 %bb.7
155155
156156 bb.7:
162162
163163 %22:gr32_abcd = MOV32r0 implicit-def dead $eflags
164164 TEST8rr %22.sub_8bit, %22.sub_8bit, implicit-def $eflags
165 JNE_1 %bb.10, implicit killed $eflags
165 JCC_1 %bb.10, 5, implicit killed $eflags
166166 JMP_1 %bb.9
167167
168168 bb.9:
174174
175175 %24:gr32_abcd = MOV32r0 implicit-def dead $eflags
176176 TEST8rr %24.sub_8bit, %24.sub_8bit, implicit-def $eflags
177 JNE_1 %bb.12, implicit killed $eflags
177 JCC_1 %bb.12, 5, implicit killed $eflags
178178 JMP_1 %bb.11
179179
180180 bb.11:
186186
187187 %26:gr32_abcd = MOV32r0 implicit-def dead $eflags
188188 TEST8rr %26.sub_8bit, %26.sub_8bit, implicit-def $eflags
189 JNE_1 %bb.14, implicit killed $eflags
189 JCC_1 %bb.14, 5, implicit killed $eflags
190190 JMP_1 %bb.13
191191
192192 bb.13:
197197 %0:gr32 = LEA32r %12, 1, $noreg, 80, $noreg
198198 %28:gr32_abcd = MOV32r0 implicit-def dead $eflags
199199 TEST8rr %28.sub_8bit, %28.sub_8bit, implicit-def $eflags
200 JNE_1 %bb.20, implicit killed $eflags
200 JCC_1 %bb.20, 5, implicit killed $eflags
201201 JMP_1 %bb.15
202202
203203 bb.15:
205205
206206 %78:gr32_abcd = MOV32r0 implicit-def dead $eflags
207207 TEST8rr %78.sub_8bit, %78.sub_8bit, implicit-def $eflags
208 JNE_1 %bb.17, implicit killed $eflags
208 JCC_1 %bb.17, 5, implicit killed $eflags
209209 JMP_1 %bb.16
210210
211211 bb.16:
216216 successors: %bb.18(0x7fffffff), %bb.19(0x00000001)
217217
218218 TEST8rr %78.sub_8bit, %78.sub_8bit, implicit-def $eflags
219 JE_1 %bb.19, implicit killed $eflags
219 JCC_1 %bb.19, 4, implicit killed $eflags
220220
221221 bb.18:
222222 %79:gr32 = LEA32r %12, 1, $noreg, 80, $noreg
236236 %35:gr32_abcd = MOV32r0 implicit-def dead $eflags
237237 TEST8rr %35.sub_8bit, %35.sub_8bit, implicit-def $eflags
238238 %80:gr32 = IMPLICIT_DEF
239 JNE_1 %bb.23, implicit killed $eflags
239 JCC_1 %bb.23, 5, implicit killed $eflags
240240 JMP_1 %bb.22
241241
242242 bb.22:
256256 MOV32mi %80, 1, $noreg, 52, $noreg, @_ZN15COLLADASaxFWL1429ColladaParserAutoGen14Private15_preEnd__authorEv
257257 %39:gr32_abcd = MOV32r0 implicit-def dead $eflags
258258 TEST8rr %39.sub_8bit, %39.sub_8bit, implicit-def $eflags
259 JNE_1 %bb.25, implicit killed $eflags
259 JCC_1 %bb.25, 5, implicit killed $eflags
260260 JMP_1 %bb.24
261261
262262 bb.24:
268268
269269 %41:gr32_abcd = MOV32r0 implicit-def dead $eflags
270270 TEST8rr %41.sub_8bit, %41.sub_8bit, implicit-def $eflags
271 JNE_1 %bb.27, implicit killed $eflags
271 JCC_1 %bb.27, 5, implicit killed $eflags
272272 JMP_1 %bb.26
273273
274274 bb.26:
280280
281281 %43:gr32_abcd = MOV32r0 implicit-def dead $eflags
282282 TEST8rr %43.sub_8bit, %43.sub_8bit, implicit-def $eflags
283 JNE_1 %bb.29, implicit killed $eflags
283 JCC_1 %bb.29, 5, implicit killed $eflags
284284 JMP_1 %bb.28
285285
286286 bb.28:
292292
293293 %45:gr32_abcd = MOV32r0 implicit-def dead $eflags
294294 TEST8rr %45.sub_8bit, %45.sub_8bit, implicit-def $eflags
295 JNE_1 %bb.31, implicit killed $eflags
295 JCC_1 %bb.31, 5, implicit killed $eflags
296296 JMP_1 %bb.30
297297
298298 bb.30:
304304
305305 %47:gr32_abcd = MOV32r0 implicit-def dead $eflags
306306 TEST8rr %47.sub_8bit, %47.sub_8bit, implicit-def $eflags
307 JNE_1 %bb.33, implicit killed $eflags
307 JCC_1 %bb.33, 5, implicit killed $eflags
308308 JMP_1 %bb.32
309309
310310 bb.32:
316316
317317 %49:gr8 = MOV8ri 1
318318 TEST8rr %49, %49, implicit-def $eflags
319 JNE_1 %bb.37, implicit killed $eflags
319 JCC_1 %bb.37, 5, implicit killed $eflags
320320 JMP_1 %bb.34
321321
322322 bb.34:
324324
325325 %81:gr32_abcd = MOV32r0 implicit-def dead $eflags
326326 TEST8rr %81.sub_8bit, %81.sub_8bit, implicit-def $eflags
327 JE_1 %bb.36, implicit killed $eflags
327 JCC_1 %bb.36, 4, implicit killed $eflags
328328
329329 bb.35:
330330 %82:gr32 = LEA32r %12, 1, $noreg, 80, $noreg
354354 MOV32mr undef %54:gr32, 1, $noreg, 0, $noreg, %1
355355 %55:gr32 = MOV32rm %12, 1, $noreg, 140, $noreg
356356 CMP32mi8 %55, 1, $noreg, 0, $noreg, 0, implicit-def $eflags
357 JE_1 %bb.40, implicit killed $eflags
357 JCC_1 %bb.40, 4, implicit killed $eflags
358358 JMP_1 %bb.39
359359
360360 bb.39:
366366
367367 %56:gr32_abcd = MOV32r0 implicit-def dead $eflags
368368 TEST8rr %56.sub_8bit, %56.sub_8bit, implicit-def $eflags
369 JNE_1 %bb.42, implicit killed $eflags
369 JCC_1 %bb.42, 5, implicit killed $eflags
370370 JMP_1 %bb.41
371371
372372 bb.41:
374374
375375 %58:gr32_abcd = MOV32r0 implicit-def dead $eflags
376376 TEST8rr %58.sub_8bit, %58.sub_8bit, implicit-def $eflags
377 JNE_1 %bb.43, implicit killed $eflags
377 JCC_1 %bb.43, 5, implicit killed $eflags
378378 JMP_1 %bb.44
379379
380380 bb.42:
390390
391391 %60:gr32_abcd = MOV32r0 implicit-def dead $eflags
392392 TEST8rr %60.sub_8bit, %60.sub_8bit, implicit-def $eflags
393 JNE_1 %bb.46, implicit killed $eflags
393 JCC_1 %bb.46, 5, implicit killed $eflags
394394 JMP_1 %bb.45
395395
396396 bb.45:
402402
403403 %62:gr32_abcd = MOV32r0 implicit-def dead $eflags
404404 TEST8rr %62.sub_8bit, %62.sub_8bit, implicit-def $eflags
405 JNE_1 %bb.48, implicit killed $eflags
405 JCC_1 %bb.48, 5, implicit killed $eflags
406406 JMP_1 %bb.47
407407
408408 bb.47:
414414
415415 %64:gr32_abcd = MOV32r0 implicit-def dead $eflags
416416 TEST8rr %64.sub_8bit, %64.sub_8bit, implicit-def $eflags
417 JNE_1 %bb.50, implicit killed $eflags
417 JCC_1 %bb.50, 5, implicit killed $eflags
418418 JMP_1 %bb.49
419419
420420 bb.49:
426426
427427 %66:gr32_abcd = MOV32r0 implicit-def dead $eflags
428428 TEST8rr %66.sub_8bit, %66.sub_8bit, implicit-def $eflags
429 JNE_1 %bb.52, implicit killed $eflags
429 JCC_1 %bb.52, 5, implicit killed $eflags
430430 JMP_1 %bb.51
431431
432432 bb.51:
438438
439439 %68:gr32_abcd = MOV32r0 implicit-def dead $eflags
440440 TEST8rr %68.sub_8bit, %68.sub_8bit, implicit-def $eflags
441 JNE_1 %bb.54, implicit killed $eflags
441 JCC_1 %bb.54, 5, implicit killed $eflags
442442 JMP_1 %bb.53
443443
444444 bb.53:
450450
451451 %70:gr32_abcd = MOV32r0 implicit-def dead $eflags
452452 TEST8rr %70.sub_8bit, %70.sub_8bit, implicit-def $eflags
453 JNE_1 %bb.56, implicit killed $eflags
453 JCC_1 %bb.56, 5, implicit killed $eflags
454454 JMP_1 %bb.55
455455
456456 bb.55:
462462
463463 %72:gr32_abcd = MOV32r0 implicit-def dead $eflags
464464 TEST8rr %72.sub_8bit, %72.sub_8bit, implicit-def $eflags
465 JNE_1 %bb.58, implicit killed $eflags
465 JCC_1 %bb.58, 5, implicit killed $eflags
466466 JMP_1 %bb.57
467467
468468 bb.57:
473473 successors: %bb.62(0x00000001), %bb.59(0x7fffffff)
474474
475475 CMP32mi8 %0, 1, $noreg, 0, $noreg, 0, implicit-def $eflags
476 JE_1 %bb.62, implicit killed $eflags
476 JCC_1 %bb.62, 4, implicit killed $eflags
477477 JMP_1 %bb.59
478478
479479 bb.59:
482482 successors: %bb.60(0x7fffffff), %bb.61(0x00000001)
483483
484484 CMP32ri undef %75:gr32, 95406325, implicit-def $eflags
485 JB_1 %bb.61, implicit killed $eflags
485 JCC_1 %bb.61, 2, implicit killed $eflags
486486 JMP_1 %bb.60
487487
488488 bb.61:
494494
495495 %76:gr32_abcd = MOV32r0 implicit-def dead $eflags
496496 TEST8rr %76.sub_8bit, %76.sub_8bit, implicit-def $eflags
497 JNE_1 %bb.64, implicit killed $eflags
497 JCC_1 %bb.64, 5, implicit killed $eflags
498498 JMP_1 %bb.63
499499
500500 bb.63:
141141 DBG_VALUE %fixed-stack.0, 0, !16, !DIExpression(), debug-location !26
142142 DBG_VALUE %fixed-stack.1, 0, !15, !DIExpression(), debug-location !25
143143 CMP32rr $eax, killed $edx, implicit-def $eflags, debug-location !27
144 JL_1 %bb.4, implicit killed $eflags, debug-location !29
144 JCC_1 %bb.4, 12, implicit killed $eflags, debug-location !29
145145 JMP_1 %bb.1, debug-location !29
146146
147147 bb.1.for.cond.preheader:
166166 ADJCALLSTACKUP32 4, 0, implicit-def dead $esp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $esp, implicit $ssp, debug-location !33
167167 $edi = INC32r killed $edi, implicit-def dead $eflags, debug-location !30
168168 CMP32rr $edi, $esi, implicit-def $eflags, debug-location !30
169 JL_1 %bb.2, implicit killed $eflags, debug-location !34
169 JCC_1 %bb.2, 12, implicit killed $eflags, debug-location !34
170170
171171 bb.3:
172172 successors: %bb.4(0x80000000)
22 name: f
33 body: |
44 bb.0:
5 JB_1 %bb.2, undef implicit killed $eflags
5 JCC_1 %bb.2, 2, undef implicit killed $eflags
66 JMP_1 %bb.1
77
88 bb.1:
1212 ; CHECK: successors: %[[PEELED_CASE_LABEL:.*]](0x5999999a), %[[PEELED_SWITCH_LABEL:.*]](0x26666666)
1313 ; CHECK: %[[VAL:[0-9]+]]:gr32 = COPY $edi
1414 ; CHECK: %{{[0-9]+}}:gr32 = SUB32ri %[[VAL]], 18568, implicit-def $eflags
15 ; CHECK: JE_1 %[[PEELED_CASE_LABEL]], implicit $eflags
15 ; CHECK: JCC_1 %[[PEELED_CASE_LABEL]], 4, implicit $eflags
1616 ; CHECK: JMP_1 %[[PEELED_SWITCH_LABEL]]
1717 ; CHECK: [[PEELED_SWITCH_LABEL]].{{[a-zA-Z0-9.]+}}:
1818 ; CHECK: successors: %[[BB1_LABEL:.*]](0x0206d3a0), %[[BB2_LABEL:.*]](0x7df92c60)
1919 ; CHECK: %{{[0-9]+}}:gr32 = SUB32ri %[[VAL]], 18311, implicit-def $eflags
20 ; CHECK: JG_1 %[[BB2_LABEL]], implicit $eflags
20 ; CHECK: JCC_1 %[[BB2_LABEL]], 15, implicit $eflags
2121 ; CHECK: JMP_1 %[[BB1_LABEL]]
2222 ; CHECK: [[BB1_LABEL]].{{[a-zA-Z0-9.]+}}:
2323 ; CHECK: successors: %[[CASE2_LABEL:.*]](0x35e50d5b), %[[BB3_LABEL:.*]](0x4a1af2a5)
2424 ; CHECK: %{{[0-9]+}}:gr32 = SUB32ri %[[VAL]], -8826, implicit-def $eflags
25 ; CHECK: JE_1 %[[CASE2_LABEL]], implicit $eflags
25 ; CHECK: JCC_1 %[[CASE2_LABEL]], 4, implicit $eflags