llvm.org GIT mirror llvm / 2306628
For now, don't split live intervals around x87 stack register barriers. FpGET_ST0_80 must be right after a call instruction (and ADJCALLSTACKUP) so we need to find a way to prevent reload of x87 registers between them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58230 91177308-0d34-0410-b5e6-96231b3b80d8 Evan Cheng 11 years ago
6 changed file(s) with 60 addition(s) and 1 deletion(s). Raw diff Collapse all Expand all
406406 return false;
407407 }
408408
409 /// IgnoreRegisterClassBarriers - Returns true if pre-register allocation
410 /// live interval splitting pass should ignore barriers of the specified
411 /// register class.
412 virtual bool IgnoreRegisterClassBarriers(const TargetRegisterClass *RC) const{
413 return true;
414 }
415
409416 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer
410417 /// values.
411418 virtual const TargetRegisterClass *getPointerRegClass() const {
424431 /// GetFunctionSizeInBytes - Returns the size of the specified MachineFunction.
425432 ///
426433 virtual unsigned GetFunctionSizeInBytes(const MachineFunction &MF) const = 0;
427
428434 };
429435
430436 /// TargetInstrInfoImpl - This is the default implementation of
658658 // by the current barrier.
659659 SmallVector Intervals;
660660 for (const TargetRegisterClass **RC = RCs; *RC; ++RC) {
661 if (TII->IgnoreRegisterClassBarriers(*RC))
662 continue;
661663 std::vector &VRs = MRI->getRegClassVirtRegs(*RC);
662664 for (unsigned i = 0, e = VRs.size(); i != e; ++i) {
663665 unsigned Reg = VRs[i];
24102410 return false;
24112411 }
24122412
2413 bool X86InstrInfo::
2414 IgnoreRegisterClassBarriers(const TargetRegisterClass *RC) const {
2415 // FIXME: Ignore bariers of x87 stack registers for now. We can't
2416 // allow any loads of these registers before FpGet_ST0_80.
2417 return RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||
2418 RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass;
2419 }
2420
24132421 const TargetRegisterClass *X86InstrInfo::getPointerRegClass() const {
24142422 const X86Subtarget *Subtarget = &TM.getSubtarget();
24152423 if (Subtarget->is64Bit())
404404 virtual
405405 bool ReverseBranchCondition(SmallVectorImpl &Cond) const;
406406
407 /// IgnoreRegisterClassBarriers - Returns true if pre-register allocation
408 /// live interval splitting pass should ignore barriers of the specified
409 /// register class.
410 bool IgnoreRegisterClassBarriers(const TargetRegisterClass *RC) const;
411
407412 const TargetRegisterClass *getPointerRegClass() const;
408413
409414 // getBaseOpcodeFor - This function returns the "base" X86 opcode for the
9393
9494 /// Code Generation virtual methods...
9595 ///
96
97 /// getCrossCopyRegClass - Returns a legal register class to copy a register
98 /// in the specified class to or from. Returns NULL if it is possible to copy
99 /// between a two registers of the specified class.
96100 const TargetRegisterClass *
97101 getCrossCopyRegClass(const TargetRegisterClass *RC) const;
98102
0 ; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -pre-alloc-split
1
2 @object_distance = external global double, align 8 ; [#uses=1]
3 @axis_slope_angle = external global double, align 8 ; [#uses=1]
4 @current_surfaces.b = external global i1 ; [#uses=1]
5
6 declare double @sin(double) nounwind readonly
7
8 declare double @asin(double) nounwind readonly
9
10 declare double @tan(double) nounwind readonly
11
12 define fastcc void @trace_line(i32 %line) nounwind {
13 entry:
14 %.b3 = load i1* @current_surfaces.b ; [#uses=1]
15 br i1 %.b3, label %bb, label %return
16
17 bb: ; preds = %bb, %entry
18 %0 = tail call double @asin(double 0.000000e+00) nounwind readonly ; [#uses=1]
19 %1 = add double 0.000000e+00, %0 ; [#uses=2]
20 %2 = tail call double @asin(double 0.000000e+00) nounwind readonly ; [#uses=1]
21 %3 = sub double %1, %2 ; [#uses=2]
22 store double %3, double* @axis_slope_angle, align 8
23 %4 = fdiv double %1, 2.000000e+00 ; [#uses=1]
24 %5 = tail call double @sin(double %4) nounwind readonly ; [#uses=1]
25 %6 = mul double 0.000000e+00, %5 ; [#uses=1]
26 %7 = tail call double @tan(double %3) nounwind readonly ; [#uses=0]
27 %8 = add double 0.000000e+00, %6 ; [#uses=1]
28 store double %8, double* @object_distance, align 8
29 br label %bb
30
31 return: ; preds = %entry
32 ret void
33 }