llvm.org GIT mirror llvm / 22fee2d
Merge XXXGenRegisterNames.inc into XXXGenRegisterInfo.inc git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134024 91177308-0d34-0410-b5e6-96231b3b80d8 Evan Cheng 9 years ago
67 changed file(s) with 165 addition(s) and 120 deletion(s). Raw diff Collapse all Expand all
17191719 # All of these files depend on tblgen and the .td files.
17201720 $(INCTMPFiles) : $(TBLGEN) $(TDFiles)
17211721
1722 $(TARGET:%=$(ObjDir)/%GenRegisterNames.inc.tmp): \
1723 $(ObjDir)/%GenRegisterNames.inc.tmp : %.td $(ObjDir)/.dir
1724 $(Echo) "Building $(
1725 $(Verb) $(TableGen) -gen-register-enums -o $(call SYSPATH, $@) $<
1726
1727 $(TARGET:%=$(ObjDir)/%GenRegisterDesc.inc.tmp): \
1728 $(ObjDir)/%GenRegisterDesc.inc.tmp : %.td $(ObjDir)/.dir
1729 $(Echo) "Building $(
1730 $(Verb) $(TableGen) -gen-register-desc -o $(call SYSPATH, $@) $<
1731
1732 $(TARGET:%=$(ObjDir)/%GenRegisterInfo.h.inc.tmp): \
1733 $(ObjDir)/%GenRegisterInfo.h.inc.tmp : %.td $(ObjDir)/.dir
1734 $(Echo) "Building $(
1735 $(Verb) $(TableGen) -gen-register-info-header -o $(call SYSPATH, $@) $<
1736
17371722 $(TARGET:%=$(ObjDir)/%GenRegisterInfo.inc.tmp): \
17381723 $(ObjDir)/%GenRegisterInfo.inc.tmp : %.td $(ObjDir)/.dir
17391724 $(Echo) "Building $(
17401725 $(Verb) $(TableGen) -gen-register-info -o $(call SYSPATH, $@) $<
17411726
1742 $(TARGET:%=$(ObjDir)/%GenInstrNames.inc.tmp): \
1743 $(ObjDir)/%GenInstrNames.inc.tmp : %.td $(ObjDir)/.dir
1744 $(Echo) "Building $(
1745 $(Verb) $(TableGen) -gen-instr-enums -o $(call SYSPATH, $@) $<
1746
17471727 $(TARGET:%=$(ObjDir)/%GenInstrInfo.inc.tmp): \
17481728 $(ObjDir)/%GenInstrInfo.inc.tmp : %.td $(ObjDir)/.dir
17491729 $(Echo) "Building $(
1750 $(Verb) $(TableGen) -gen-instr-desc -o $(call SYSPATH, $@) $<
1730 $(Verb) $(TableGen) -gen-instr-info -o $(call SYSPATH, $@) $<
17511731
17521732 $(TARGET:%=$(ObjDir)/%GenAsmWriter.inc.tmp): \
17531733 $(ObjDir)/%GenAsmWriter.inc.tmp : %.td $(ObjDir)/.dir
66 //
77 //===----------------------------------------------------------------------===//
88 //
9 // This file defines the McOperandInfo and McInstrDesc classes, which
9 // This file defines the MCOperandInfo and MCInstrDesc classes, which
1010 // are used to describe target instructions and their operands.
1111 //
1212 //===----------------------------------------------------------------------===//
2929
3030 // Defines symbolic names for the ARM instructions.
3131 //
32 #include "ARMGenInstrNames.inc"
32 #define GET_INSTRINFO_ENUM
33 #include "ARMGenInstrInfo.inc"
3334
3435 namespace llvm {
3536
1717 #include "ARMHazardRecognizer.h"
1818 #include "ARMMachineFunctionInfo.h"
1919 #include "ARMRegisterInfo.h"
20 #include "ARMGenInstrInfo.inc"
2120 #include "llvm/Constants.h"
2221 #include "llvm/Function.h"
2322 #include "llvm/GlobalValue.h"
3433 #include "llvm/Support/Debug.h"
3534 #include "llvm/Support/ErrorHandling.h"
3635 #include "llvm/ADT/STLExtras.h"
36
37 #define GET_INSTRINFO_MC_DESC
38 #include "ARMGenInstrInfo.inc"
39
3740 using namespace llvm;
3841
3942 static cl::opt
1313 #include "ARMInstrInfo.h"
1414 #include "ARM.h"
1515 #include "ARMAddressingModes.h"
16 #include "ARMGenInstrInfo.inc"
1716 #include "ARMMachineFunctionInfo.h"
1817 #include "llvm/ADT/STLExtras.h"
1918 #include "llvm/CodeGen/LiveVariables.h"
0 set(LLVM_TARGET_DEFINITIONS ARM.td)
11
22 tablegen(ARMGenRegisterInfo.inc -gen-register-info)
3 tablegen(ARMGenInstrNames.inc -gen-instr-enums)
4 tablegen(ARMGenInstrInfo.inc -gen-instr-desc)
3 tablegen(ARMGenInstrInfo.inc -gen-instr-info)
54 tablegen(ARMGenCodeEmitter.inc -gen-emitter)
65 tablegen(ARMGenMCCodeEmitter.inc -gen-emitter -mc-emitter)
76 tablegen(ARMGenAsmWriter.inc -gen-asm-writer)
7070 /// { ARM::CCRRegClassID, 0|(1<
7171 ///
7272 /// And this maps to one MCOperand with the regsiter kind of ARM::CPSR.
73 #define GET_INSTRINFO_MC_DESC
7374 #include "ARMGenInstrInfo.inc"
7475
7576 using namespace llvm;
1111 TARGET = ARM
1212
1313 # Make sure that tblgen is run, first thing.
14 BUILT_SOURCES = ARMGenRegisterInfo.inc \
15 ARMGenInstrNames.inc ARMGenInstrInfo.inc \
14 BUILT_SOURCES = ARMGenRegisterInfo.inc ARMGenInstrInfo.inc \
1615 ARMGenAsmWriter.inc ARMGenAsmMatcher.inc \
1716 ARMGenDAGISel.inc ARMGenSubtarget.inc \
1817 ARMGenCodeEmitter.inc ARMGenCallingConv.inc \
1212
1313 #include "Thumb1InstrInfo.h"
1414 #include "ARM.h"
15 #include "ARMGenInstrInfo.inc"
1615 #include "ARMMachineFunctionInfo.h"
1716 #include "llvm/CodeGen/MachineFrameInfo.h"
1817 #include "llvm/CodeGen/MachineInstrBuilder.h"
1414 #include "ARM.h"
1515 #include "ARMConstantPoolValue.h"
1616 #include "ARMAddressingModes.h"
17 #include "ARMGenInstrInfo.inc"
1817 #include "ARMMachineFunctionInfo.h"
1918 #include "Thumb2InstrInfo.h"
2019 #include "llvm/CodeGen/MachineFrameInfo.h"
4949
5050 // Defines symbolic names for the Alpha instructions.
5151 //
52 #include "AlphaGenInstrNames.inc"
52 #define GET_INSTRINFO_ENUM
53 #include "AlphaGenInstrInfo.inc"
5354
5455 #endif
1313 #include "Alpha.h"
1414 #include "AlphaInstrInfo.h"
1515 #include "AlphaMachineFunctionInfo.h"
16 #include "AlphaGenInstrInfo.inc"
1716 #include "llvm/CodeGen/MachineRegisterInfo.h"
1817 #include "llvm/ADT/STLExtras.h"
1918 #include "llvm/ADT/SmallVector.h"
2019 #include "llvm/CodeGen/MachineInstrBuilder.h"
2120 #include "llvm/Support/ErrorHandling.h"
21
22 #define GET_INSTRINFO_MC_DESC
23 #include "AlphaGenInstrInfo.inc"
2224 using namespace llvm;
2325
2426 AlphaInstrInfo::AlphaInstrInfo()
0 set(LLVM_TARGET_DEFINITIONS Alpha.td)
11
22 tablegen(AlphaGenRegisterInfo.inc -gen-register-info)
3 tablegen(AlphaGenInstrNames.inc -gen-instr-enums)
4 tablegen(AlphaGenInstrInfo.inc -gen-instr-desc)
3 tablegen(AlphaGenInstrInfo.inc -gen-instr-info)
54 tablegen(AlphaGenAsmWriter.inc -gen-asm-writer)
65 tablegen(AlphaGenDAGISel.inc -gen-dag-isel)
76 tablegen(AlphaGenCallingConv.inc -gen-callingconv)
1111 TARGET = Alpha
1212
1313 # Make sure that tblgen is run, first thing.
14 BUILT_SOURCES = AlphaGenRegisterInfo.inc \
15 AlphaGenInstrNames.inc AlphaGenInstrInfo.inc \
14 BUILT_SOURCES = AlphaGenRegisterInfo.inc AlphaGenInstrInfo.inc \
1615 AlphaGenAsmWriter.inc AlphaGenDAGISel.inc \
1716 AlphaGenCallingConv.inc AlphaGenSubtarget.inc
1817
3333 #include "BlackfinGenRegisterInfo.inc"
3434
3535 // Defines symbolic names for the Blackfin instructions.
36 #include "BlackfinGenInstrNames.inc"
36 #define GET_INSTRINFO_ENUM
37 #include "BlackfinGenInstrInfo.inc"
3738
3839 #endif
1818 #include "llvm/CodeGen/MachineRegisterInfo.h"
1919 #include "llvm/CodeGen/MachineInstrBuilder.h"
2020 #include "llvm/Support/ErrorHandling.h"
21
22 #define GET_INSTRINFO_MC_DESC
2123 #include "BlackfinGenInstrInfo.inc"
2224
2325 using namespace llvm;
0 set(LLVM_TARGET_DEFINITIONS Blackfin.td)
11
22 tablegen(BlackfinGenRegisterInfo.inc -gen-register-info)
3 tablegen(BlackfinGenInstrNames.inc -gen-instr-enums)
4 tablegen(BlackfinGenInstrInfo.inc -gen-instr-desc)
3 tablegen(BlackfinGenInstrInfo.inc -gen-instr-info)
54 tablegen(BlackfinGenAsmWriter.inc -gen-asm-writer)
65 tablegen(BlackfinGenDAGISel.inc -gen-dag-isel)
76 tablegen(BlackfinGenSubtarget.inc -gen-subtarget)
1111 TARGET = Blackfin
1212
1313 # Make sure that tblgen is run, first thing.
14 BUILT_SOURCES = BlackfinGenRegisterInfo.inc BlackfinGenInstrNames.inc \
15 BlackfinGenInstrInfo.inc BlackfinGenAsmWriter.inc \
14 BUILT_SOURCES = BlackfinGenRegisterInfo.inc BlackfinGenInstrInfo.inc \
15 BlackfinGenAsmWriter.inc \
1616 BlackfinGenDAGISel.inc BlackfinGenSubtarget.inc \
1717 BlackfinGenCallingConv.inc BlackfinGenIntrinsics.inc
1818
0 set(LLVM_TARGET_DEFINITIONS SPU.td)
11
2 tablegen(SPUGenInstrNames.inc -gen-instr-enums)
32 tablegen(SPUGenAsmWriter.inc -gen-asm-writer)
43 tablegen(SPUGenCodeEmitter.inc -gen-emitter)
54 tablegen(SPUGenRegisterInfo.inc -gen-register-info)
6 tablegen(SPUGenInstrInfo.inc -gen-instr-desc)
5 tablegen(SPUGenInstrInfo.inc -gen-instr-info)
76 tablegen(SPUGenDAGISel.inc -gen-dag-isel)
87 tablegen(SPUGenSubtarget.inc -gen-subtarget)
98 tablegen(SPUGenCallingConv.inc -gen-callingconv)
99 LEVEL = ../../..
1010 LIBRARYNAME = LLVMCellSPUCodeGen
1111 TARGET = SPU
12 BUILT_SOURCES = SPUGenInstrNames.inc SPUGenRegisterInfo.inc \
12 BUILT_SOURCES = SPUGenInstrInfo.inc SPUGenRegisterInfo.inc \
1313 SPUGenAsmWriter.inc SPUGenCodeEmitter.inc \
14 SPUGenInstrInfo.inc SPUGenDAGISel.inc \
14 SPUGenDAGISel.inc \
1515 SPUGenSubtarget.inc SPUGenCallingConv.inc
1616
1717 DIRS = TargetInfo
2929
3030 // Defines symbolic names for the SPU instructions.
3131 //
32 #include "SPUGenInstrNames.inc"
32 #define GET_INSTRINFO_ENUM
33 #include "SPUGenInstrInfo.inc"
3334
3435 #endif /* LLVM_TARGET_IBMCELLSPU_H */
1414 #include "SPUInstrInfo.h"
1515 #include "SPUInstrBuilder.h"
1616 #include "SPUTargetMachine.h"
17 #include "SPUGenInstrInfo.inc"
1817 #include "SPUHazardRecognizers.h"
1918 #include "llvm/CodeGen/MachineInstrBuilder.h"
2019 #include "llvm/Support/Debug.h"
2120 #include "llvm/Support/ErrorHandling.h"
2221 #include "llvm/Support/raw_ostream.h"
2322 #include "llvm/MC/MCContext.h"
23
24 #define GET_INSTRINFO_MC_DESC
25 #include "SPUGenInstrInfo.inc"
2426
2527 using namespace llvm;
2628
0 set(LLVM_TARGET_DEFINITIONS MBlaze.td)
11
22 tablegen(MBlazeGenRegisterInfo.inc -gen-register-info)
3 tablegen(MBlazeGenInstrNames.inc -gen-instr-enums)
4 tablegen(MBlazeGenInstrInfo.inc -gen-instr-desc)
3 tablegen(MBlazeGenInstrInfo.inc -gen-instr-info)
54 tablegen(MBlazeGenCodeEmitter.inc -gen-emitter)
65 tablegen(MBlazeGenAsmWriter.inc -gen-asm-writer)
76 tablegen(MBlazeGenAsmMatcher.inc -gen-asm-matcher)
2626
2727 // #include "MBlazeGenDecoderTables.inc"
2828 // #include "MBlazeGenRegisterNames.inc"
29 #define GET_INSTRINFO_MC_DESC
2930 #include "MBlazeGenInstrInfo.inc"
3031 #include "MBlazeGenEDInfo.inc"
3132
4242 #include "MBlazeGenRegisterInfo.inc"
4343
4444 // Defines symbolic names for the MBlaze instructions.
45 #include "MBlazeGenInstrNames.inc"
45 #define GET_INSTRINFO_ENUM
46 #include "MBlazeGenInstrInfo.inc"
4647
4748 #endif
1919 #include "llvm/CodeGen/ScoreboardHazardRecognizer.h"
2020 #include "llvm/Support/CommandLine.h"
2121 #include "llvm/Support/ErrorHandling.h"
22
23 #define GET_INSTRINFO_MC_DESC
2224 #include "MBlazeGenInstrInfo.inc"
2325
2426 using namespace llvm;
1010 TARGET = MBlaze
1111
1212 # Make sure that tblgen is run, first thing.
13 BUILT_SOURCES = MBlazeGenRegisterInfo.inc MBlazeGenInstrNames.inc \
14 MBlazeGenInstrInfo.inc MBlazeGenAsmWriter.inc \
13 BUILT_SOURCES = MBlazeGenRegisterInfo.inc MBlazeGenInstrInfo.inc \
14 MBlazeGenAsmWriter.inc \
1515 MBlazeGenDAGISel.inc MBlazeGenAsmMatcher.inc \
1616 MBlazeGenCodeEmitter.inc MBlazeGenCallingConv.inc \
1717 MBlazeGenSubtarget.inc MBlazeGenIntrinsics.inc \
0 set(LLVM_TARGET_DEFINITIONS MSP430.td)
11
22 tablegen(MSP430GenRegisterInfo.inc -gen-register-info)
3 tablegen(MSP430GenInstrNames.inc -gen-instr-enums)
4 tablegen(MSP430GenInstrInfo.inc -gen-instr-desc)
3 tablegen(MSP430GenInstrInfo.inc -gen-instr-info)
54 tablegen(MSP430GenAsmWriter.inc -gen-asm-writer)
65 tablegen(MSP430GenDAGISel.inc -gen-dag-isel)
76 tablegen(MSP430GenCallingConv.inc -gen-callingconv)
5050 #include "MSP430GenRegisterInfo.inc"
5151
5252 // Defines symbolic names for the MSP430 instructions.
53 #include "MSP430GenInstrNames.inc"
53 #define GET_INSTRINFO_ENUM
54 #include "MSP430GenInstrInfo.inc"
5455
5556 #endif
1414 #include "MSP430InstrInfo.h"
1515 #include "MSP430MachineFunctionInfo.h"
1616 #include "MSP430TargetMachine.h"
17 #include "MSP430GenInstrInfo.inc"
1817 #include "llvm/Function.h"
1918 #include "llvm/CodeGen/MachineFrameInfo.h"
2019 #include "llvm/CodeGen/MachineInstrBuilder.h"
2120 #include "llvm/CodeGen/MachineRegisterInfo.h"
2221 #include "llvm/CodeGen/PseudoSourceValue.h"
2322 #include "llvm/Support/ErrorHandling.h"
23
24 #define GET_INSTRINFO_MC_DESC
25 #include "MSP430GenInstrInfo.inc"
2426
2527 using namespace llvm;
2628
1111 TARGET = MSP430
1212
1313 # Make sure that tblgen is run, first thing.
14 BUILT_SOURCES = MSP430GenRegisterInfo.inc MSP430GenInstrNames.inc \
15 MSP430GenInstrInfo.inc MSP430GenAsmWriter.inc \
14 BUILT_SOURCES = MSP430GenRegisterInfo.inc MSP430GenInstrInfo.inc \
15 MSP430GenAsmWriter.inc \
1616 MSP430GenDAGISel.inc MSP430GenCallingConv.inc \
1717 MSP430GenSubtarget.inc
1818
0 set(LLVM_TARGET_DEFINITIONS Mips.td)
11
22 tablegen(MipsGenRegisterInfo.inc -gen-register-info)
3 tablegen(MipsGenInstrNames.inc -gen-instr-enums)
4 tablegen(MipsGenInstrInfo.inc -gen-instr-desc)
3 tablegen(MipsGenInstrInfo.inc -gen-instr-info)
54 tablegen(MipsGenAsmWriter.inc -gen-asm-writer)
65 tablegen(MipsGenDAGISel.inc -gen-dag-isel)
76 tablegen(MipsGenCallingConv.inc -gen-callingconv)
1111 TARGET = Mips
1212
1313 # Make sure that tblgen is run, first thing.
14 BUILT_SOURCES = MipsGenRegisterInfo.inc MipsGenInstrNames.inc \
15 MipsGenInstrInfo.inc MipsGenAsmWriter.inc \
14 BUILT_SOURCES = MipsGenRegisterInfo.inc MipsGenInstrInfo.inc \
15 MipsGenAsmWriter.inc \
1616 MipsGenDAGISel.inc MipsGenCallingConv.inc \
1717 MipsGenSubtarget.inc
1818
3838 #include "MipsGenRegisterInfo.inc"
3939
4040 // Defines symbolic names for the Mips instructions.
41 #include "MipsGenInstrNames.inc"
41 #define GET_INSTRINFO_ENUM
42 #include "MipsGenInstrInfo.inc"
4243
4344 #endif
1717 #include "llvm/CodeGen/MachineInstrBuilder.h"
1818 #include "llvm/CodeGen/MachineRegisterInfo.h"
1919 #include "llvm/Support/ErrorHandling.h"
20
21 #define GET_INSTRINFO_MC_DESC
2022 #include "MipsGenInstrInfo.inc"
2123
2224 using namespace llvm;
22 tablegen(PTXGenAsmWriter.inc -gen-asm-writer)
33 tablegen(PTXGenCallingConv.inc -gen-callingconv)
44 tablegen(PTXGenDAGISel.inc -gen-dag-isel)
5 tablegen(PTXGenInstrInfo.inc -gen-instr-desc)
6 tablegen(PTXGenInstrNames.inc -gen-instr-enums)
5 tablegen(PTXGenInstrInfo.inc -gen-instr-info)
76 tablegen(PTXGenRegisterInfo.inc -gen-register-info)
87 tablegen(PTXGenSubtarget.inc -gen-subtarget)
98
1515 PTXGenCallingConv.inc \
1616 PTXGenDAGISel.inc \
1717 PTXGenInstrInfo.inc \
18 PTXGenInstrNames.inc \
1918 PTXGenRegisterInfo.inc \
2019 PTXGenSubtarget.inc
2120
5050 #include "PTXGenRegisterInfo.inc"
5151
5252 // Defines symbolic names for the PTX instructions.
53 #include "PTXGenInstrNames.inc"
53 #define GET_INSTRINFO_ENUM
54 #include "PTXGenInstrInfo.inc"
5455
5556 #endif // PTX_H
2020 #include "llvm/Support/Debug.h"
2121 #include "llvm/Support/raw_ostream.h"
2222
23 #define GET_INSTRINFO_MC_DESC
24 #include "PTXGenInstrInfo.inc"
25
2326 using namespace llvm;
24
25 #include "PTXGenInstrInfo.inc"
2627
2728 PTXInstrInfo::PTXInstrInfo(PTXTargetMachine &_TM)
2829 : TargetInstrInfoImpl(PTXInsts, array_lengthof(PTXInsts)),
0 set(LLVM_TARGET_DEFINITIONS PPC.td)
11
2 tablegen(PPCGenInstrNames.inc -gen-instr-enums)
32 tablegen(PPCGenAsmWriter.inc -gen-asm-writer)
43 tablegen(PPCGenCodeEmitter.inc -gen-emitter)
54 tablegen(PPCGenMCCodeEmitter.inc -gen-emitter -mc-emitter)
65 tablegen(PPCGenRegisterInfo.inc -gen-register-info)
7 tablegen(PPCGenInstrInfo.inc -gen-instr-desc)
6 tablegen(PPCGenInstrInfo.inc -gen-instr-info)
87 tablegen(PPCGenDAGISel.inc -gen-dag-isel)
98 tablegen(PPCGenCallingConv.inc -gen-callingconv)
109 tablegen(PPCGenSubtarget.inc -gen-subtarget)
1111 TARGET = PPC
1212
1313 # Make sure that tblgen is run, first thing.
14 BUILT_SOURCES = PPCGenInstrNames.inc PPCGenRegisterInfo.inc \
14 BUILT_SOURCES = PPCGenRegisterInfo.inc \
1515 PPCGenAsmWriter.inc PPCGenCodeEmitter.inc \
1616 PPCGenInstrInfo.inc PPCGenDAGISel.inc \
1717 PPCGenSubtarget.inc PPCGenCallingConv.inc \
8888
8989 // Defines symbolic names for the PowerPC instructions.
9090 //
91 #include "PPCGenInstrNames.inc"
91 #define GET_INSTRINFO_ENUM
92 #include "PPCGenInstrInfo.inc"
9293
9394 #endif
1414 #include "PPCInstrBuilder.h"
1515 #include "PPCMachineFunctionInfo.h"
1616 #include "PPCPredicates.h"
17 #include "PPCGenInstrInfo.inc"
1817 #include "PPCTargetMachine.h"
1918 #include "PPCHazardRecognizers.h"
2019 #include "llvm/ADT/STLExtras.h"
2726 #include "llvm/Support/ErrorHandling.h"
2827 #include "llvm/Support/raw_ostream.h"
2928 #include "llvm/MC/MCAsmInfo.h"
29
30 #define GET_INSTRINFO_MC_DESC
31 #include "PPCGenInstrInfo.inc"
3032
3133 namespace llvm {
3234 extern cl::opt EnablePPC32RS; // FIXME (64-bit): See PPCRegisterInfo.cpp.
0 set(LLVM_TARGET_DEFINITIONS Sparc.td)
11
22 tablegen(SparcGenRegisterInfo.inc -gen-register-info)
3 tablegen(SparcGenInstrNames.inc -gen-instr-enums)
4 tablegen(SparcGenInstrInfo.inc -gen-instr-desc)
3 tablegen(SparcGenInstrInfo.inc -gen-instr-info)
54 tablegen(SparcGenAsmWriter.inc -gen-asm-writer)
65 tablegen(SparcGenDAGISel.inc -gen-dag-isel)
76 tablegen(SparcGenSubtarget.inc -gen-subtarget)
1111 TARGET = Sparc
1212
1313 # Make sure that tblgen is run, first thing.
14 BUILT_SOURCES = SparcGenRegisterInfo.inc SparcGenInstrNames.inc \
15 SparcGenInstrInfo.inc SparcGenAsmWriter.inc \
14 BUILT_SOURCES = SparcGenRegisterInfo.inc SparcGenInstrInfo.inc \
15 SparcGenAsmWriter.inc \
1616 SparcGenDAGISel.inc SparcGenSubtarget.inc SparcGenCallingConv.inc
1717
1818 DIRS = TargetInfo
4040
4141 // Defines symbolic names for the Sparc instructions.
4242 //
43 #include "SparcGenInstrNames.inc"
43 #define GET_INSTRINFO_ENUM
44 #include "SparcGenInstrInfo.inc"
4445
4546
4647 namespace llvm {
1818 #include "llvm/CodeGen/MachineInstrBuilder.h"
1919 #include "llvm/CodeGen/MachineRegisterInfo.h"
2020 #include "llvm/Support/ErrorHandling.h"
21 #include "SparcMachineFunctionInfo.h"
22
23 #define GET_INSTRINFO_MC_DESC
2124 #include "SparcGenInstrInfo.inc"
22 #include "SparcMachineFunctionInfo.h"
25
2326 using namespace llvm;
2427
2528 SparcInstrInfo::SparcInstrInfo(SparcSubtarget &ST)
0 set(LLVM_TARGET_DEFINITIONS SystemZ.td)
11
22 tablegen(SystemZGenRegisterInfo.inc -gen-register-info)
3 tablegen(SystemZGenInstrNames.inc -gen-instr-enums)
4 tablegen(SystemZGenInstrInfo.inc -gen-instr-desc)
3 tablegen(SystemZGenInstrInfo.inc -gen-instr-info)
54 tablegen(SystemZGenAsmWriter.inc -gen-asm-writer)
65 tablegen(SystemZGenDAGISel.inc -gen-dag-isel)
76 tablegen(SystemZGenCallingConv.inc -gen-callingconv)
1111 TARGET = SystemZ
1212
1313 # Make sure that tblgen is run, first thing.
14 BUILT_SOURCES = SystemZGenRegisterInfo.inc SystemZGenInstrNames.inc \
15 SystemZGenInstrInfo.inc SystemZGenAsmWriter.inc \
14 BUILT_SOURCES = SystemZGenRegisterInfo.inc SystemZGenInstrInfo.inc \
15 SystemZGenAsmWriter.inc \
1616 SystemZGenDAGISel.inc SystemZGenSubtarget.inc SystemZGenCallingConv.inc
1717
1818 DIRS = TargetInfo
5656 #include "SystemZGenRegisterInfo.inc"
5757
5858 // Defines symbolic names for the SystemZ instructions.
59 #include "SystemZGenInstrNames.inc"
59 #define GET_INSTRINFO_ENUM
60 #include "SystemZGenInstrInfo.inc"
6061
6162 #endif
1515 #include "SystemZInstrInfo.h"
1616 #include "SystemZMachineFunctionInfo.h"
1717 #include "SystemZTargetMachine.h"
18 #include "SystemZGenInstrInfo.inc"
1918 #include "llvm/Function.h"
2019 #include "llvm/CodeGen/MachineFrameInfo.h"
2120 #include "llvm/CodeGen/MachineInstrBuilder.h"
2221 #include "llvm/CodeGen/MachineRegisterInfo.h"
2322 #include "llvm/CodeGen/PseudoSourceValue.h"
2423 #include "llvm/Support/ErrorHandling.h"
24
25 #define GET_INSTRINFO_MC_DESC
26 #include "SystemZGenInstrInfo.inc"
27
2528 using namespace llvm;
2629
2730 SystemZInstrInfo::SystemZInstrInfo(SystemZTargetMachine &tm)
11
22 tablegen(X86GenRegisterInfo.inc -gen-register-info)
33 tablegen(X86GenDisassemblerTables.inc -gen-disassembler)
4 tablegen(X86GenInstrNames.inc -gen-instr-enums)
5 tablegen(X86GenInstrInfo.inc -gen-instr-desc)
4 tablegen(X86GenInstrInfo.inc -gen-instr-info)
65 tablegen(X86GenAsmWriter.inc -gen-asm-writer)
76 tablegen(X86GenAsmWriter1.inc -gen-asm-writer -asmwriternum=1)
87 tablegen(X86GenAsmMatcher.inc -gen-asm-matcher)
1515 #include "X86ATTInstPrinter.h"
1616 #include "X86InstComments.h"
1717 #include "X86Subtarget.h"
18 #include "MCTargetDesc/X86TargetDesc.h"
1819 #include "llvm/MC/MCInst.h"
1920 #include "llvm/MC/MCAsmInfo.h"
2021 #include "llvm/MC/MCExpr.h"
2122 #include "llvm/Support/ErrorHandling.h"
2223 #include "llvm/Support/Format.h"
2324 #include "llvm/Support/FormattedStream.h"
24 #include "X86GenInstrNames.inc"
2525 #include
2626 using namespace llvm;
2727
2828 // Include the auto-generated portion of the assembly writer.
29 #define GET_REGINFO_ENUM
30 #include "X86GenRegisterInfo.inc"
3129 #define GET_INSTRUCTION_NAME
3230 #define PRINT_ALIAS_INSTR
3331 #include "X86GenAsmWriter.inc"
1212 //===----------------------------------------------------------------------===//
1313
1414 #include "X86InstComments.h"
15 #include "X86GenInstrNames.inc"
15 #include "MCTargetDesc/X86TargetDesc.h"
1616 #include "llvm/MC/MCInst.h"
1717 #include "llvm/Support/raw_ostream.h"
1818 #include "../Utils/X86ShuffleDecode.h"
1515 #include "X86IntelInstPrinter.h"
1616 #include "X86InstComments.h"
1717 #include "X86Subtarget.h"
18 #include "MCTargetDesc/X86TargetDesc.h"
1819 #include "llvm/MC/MCInst.h"
1920 #include "llvm/MC/MCAsmInfo.h"
2021 #include "llvm/MC/MCExpr.h"
2122 #include "llvm/Support/ErrorHandling.h"
2223 #include "llvm/Support/FormattedStream.h"
23 #include "X86GenInstrNames.inc"
2424 #include
2525 using namespace llvm;
2626
1111 //===----------------------------------------------------------------------===//
1212
1313 #include "X86TargetDesc.h"
14 #include "llvm/MC/MCInstrInfo.h"
1415 #include "llvm/MC/MCRegisterInfo.h"
1516 #include "llvm/Target/TargetRegistry.h"
1617
1718 #define GET_REGINFO_MC_DESC
1819 #include "X86GenRegisterInfo.inc"
20
21 #define GET_INSTRINFO_MC_DESC
22 #include "X86GenInstrInfo.inc"
23
1924 using namespace llvm;
2025
2126 MCRegisterInfo *createX86MCRegisterInfo() {
2525 #define GET_REGINFO_ENUM
2626 #include "X86GenRegisterInfo.inc"
2727
28 // Defines symbolic names for the X86 instructions.
29 //
30 #define GET_INSTRINFO_ENUM
31 #include "X86GenInstrInfo.inc"
32
2833 #endif
1111 TARGET = X86
1212
1313 # Make sure that tblgen is run, first thing.
14 BUILT_SOURCES = X86GenRegisterInfo.inc \
15 X86GenInstrNames.inc X86GenInstrInfo.inc \
14 BUILT_SOURCES = X86GenRegisterInfo.inc X86GenInstrInfo.inc \
1615 X86GenAsmWriter.inc X86GenAsmMatcher.inc \
1716 X86GenAsmWriter1.inc X86GenDAGISel.inc \
1817 X86GenDisassemblerTables.inc X86GenFastISel.inc \
1414 #ifndef TARGET_X86_H
1515 #define TARGET_X86_H
1616
17 #include "MCTargetDesc/X86TargetDesc.h"
1718 #include "llvm/Support/DataTypes.h"
1819 #include "llvm/Target/TargetMachine.h"
1920
8586
8687 } // End llvm namespace
8788
88 #include "MCTargetDesc/X86TargetDesc.h"
89
90 // Defines symbolic names for the X86 instructions.
91 //
92 #include "X86GenInstrNames.inc"
93
9489 #endif
1212
1313 #include "X86InstrInfo.h"
1414 #include "X86.h"
15 #include "X86GenInstrInfo.inc"
1615 #include "X86InstrBuilder.h"
1716 #include "X86MachineFunctionInfo.h"
1817 #include "X86Subtarget.h"
3433 #include "llvm/Target/TargetOptions.h"
3534 #include "llvm/MC/MCAsmInfo.h"
3635 #include
36
37 #define GET_INSTRINFO_MC_DESC
38 #include "X86GenInstrInfo.inc"
3739
3840 using namespace llvm;
3941
0 set(LLVM_TARGET_DEFINITIONS XCore.td)
11
22 tablegen(XCoreGenRegisterInfo.inc -gen-register-info)
3 tablegen(XCoreGenInstrNames.inc -gen-instr-enums)
4 tablegen(XCoreGenInstrInfo.inc -gen-instr-desc)
3 tablegen(XCoreGenInstrInfo.inc -gen-instr-info)
54 tablegen(XCoreGenAsmWriter.inc -gen-asm-writer)
65 tablegen(XCoreGenDAGISel.inc -gen-dag-isel)
76 tablegen(XCoreGenCallingConv.inc -gen-callingconv)
1111 TARGET = XCore
1212
1313 # Make sure that tblgen is run, first thing.
14 BUILT_SOURCES = XCoreGenRegisterInfo.inc XCoreGenInstrNames.inc \
15 XCoreGenInstrInfo.inc XCoreGenAsmWriter.inc \
14 BUILT_SOURCES = XCoreGenRegisterInfo.inc XCoreGenInstrInfo.inc \
15 XCoreGenAsmWriter.inc \
1616 XCoreGenDAGISel.inc XCoreGenCallingConv.inc \
1717 XCoreGenSubtarget.inc
1818
3636
3737 // Defines symbolic names for the XCore instructions.
3838 //
39 #include "XCoreGenInstrNames.inc"
39 #define GET_INSTRINFO_ENUM
40 #include "XCoreGenInstrInfo.inc"
4041
4142 #endif
1717 #include "llvm/CodeGen/MachineInstrBuilder.h"
1818 #include "llvm/CodeGen/MachineFrameInfo.h"
1919 #include "llvm/CodeGen/MachineLocation.h"
20 #include "XCoreGenInstrInfo.inc"
2120 #include "llvm/ADT/STLExtras.h"
2221 #include "llvm/Support/Debug.h"
2322 #include "llvm/Support/ErrorHandling.h"
23
24 #define GET_INSTRINFO_MC_DESC
25 #include "XCoreGenInstrInfo.inc"
2426
2527 namespace llvm {
2628 namespace XCore {
155155
156156 // run - Emit the main instruction description records for the target...
157157 void InstrInfoEmitter::run(raw_ostream &OS) {
158 emitEnums(OS);
159
158160 GatherItinClasses();
159161
160162 EmitSourceFileHeader("Target Instruction Descriptors", OS);
163
164 OS << "\n#ifdef GET_INSTRINFO_MC_DESC\n";
165 OS << "#undef GET_INSTRINFO_MC_DESC\n";
166
161167 OS << "namespace llvm {\n\n";
162168
163169 CodeGenTarget &Target = CDP.getTargetInfo();
201207 OperandInfoIDs, OS);
202208 OS << "};\n";
203209 OS << "} // End llvm namespace \n";
210
211 OS << "#endif // GET_INSTRINFO_MC_DESC\n\n";
204212 }
205213
206214 void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
282290
283291 OS << " }, // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n";
284292 }
293
294 // emitEnums - Print out enum values for all of the instructions.
295 void InstrInfoEmitter::emitEnums(raw_ostream &OS) {
296 EmitSourceFileHeader("Target Instruction Enum Values", OS);
297
298 OS << "\n#ifdef GET_INSTRINFO_ENUM\n";
299 OS << "#undef GET_INSTRINFO_ENUM\n";
300
301 OS << "namespace llvm {\n\n";
302
303 CodeGenTarget Target(Records);
304
305 // We must emit the PHI opcode first...
306 std::string Namespace = Target.getInstNamespace();
307
308 if (Namespace.empty()) {
309 fprintf(stderr, "No instructions defined!\n");
310 exit(1);
311 }
312
313 const std::vector &NumberedInstructions =
314 Target.getInstructionsByEnumValue();
315
316 OS << "namespace " << Namespace << " {\n";
317 OS << " enum {\n";
318 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
319 OS << " " << NumberedInstructions[i]->TheDef->getName()
320 << "\t= " << i << ",\n";
321 }
322 OS << " INSTRUCTION_LIST_END = " << NumberedInstructions.size() << "\n";
323 OS << " };\n}\n";
324 OS << "} // End llvm namespace \n";
325
326 OS << "#endif // GET_INSTRINFO_ENUM\n\n";
327 }
3838 void run(raw_ostream &OS);
3939
4040 private:
41 typedef std::map, unsigned> OperandInfoMapTy;
42
41 void emitEnums(raw_ostream &OS);
42
43 typedef std::map, unsigned> OperandInfoMapTy;
4344 void emitRecord(const CodeGenInstruction &Inst, unsigned Num,
4445 Record *InstrInfo,
4546 std::map, unsigned> &EL,
2727 #include "EDEmitter.h"
2828 #include "Error.h"
2929 #include "FastISelEmitter.h"
30 #include "InstrEnumEmitter.h"
3130 #include "InstrInfoEmitter.h"
3231 #include "IntrinsicEmitter.h"
3332 #include "LLVMCConfigurationEmitter.h"
5453 PrintRecords,
5554 GenEmitter,
5655 GenRegisterInfo,
57 GenInstrEnums, GenInstrs, GenAsmWriter, GenAsmMatcher,
56 GenInstrInfo,
57 GenAsmWriter,
58 GenAsmMatcher,
5859 GenARMDecoder,
5960 GenDisassembler,
6061 GenCallingConv,
9495 "Generate machine code emitter"),
9596 clEnumValN(GenRegisterInfo, "gen-register-info",
9697 "Generate registers and register classes info"),
97 clEnumValN(GenInstrEnums, "gen-instr-enums",
98 "Generate enum values for instructions"),
99 clEnumValN(GenInstrs, "gen-instr-desc",
98 clEnumValN(GenInstrInfo, "gen-instr-info",
10099 "Generate instruction descriptions"),
101100 clEnumValN(GenCallingConv, "gen-callingconv",
102101 "Generate calling convention descriptions"),
259258 case GenRegisterInfo:
260259 RegisterInfoEmitter(Records).run(Out.os());
261260 break;
262 case GenInstrEnums:
263 InstrEnumEmitter(Records).run(Out.os());
264 break;
265 case GenInstrs:
261 case GenInstrInfo:
266262 InstrInfoEmitter(Records).run(Out.os());
267263 break;
268264 case GenCallingConv: