llvm.org GIT mirror llvm / 22f5dc7
Rename sat_shift operand to shift_imm, in preparation for using it for other instructions besides saturate instructions. No functional changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111168 91177308-0d34-0410-b5e6-96231b3b80d8 Bob Wilson 10 years ago
6 changed file(s) with 18 addition(s) and 15 deletion(s). Raw diff Collapse all Expand all
123123 raw_ostream &O);
124124 void printMemBOption(const MachineInstr *MI, int OpNum,
125125 raw_ostream &O);
126 void printSatShiftOperand(const MachineInstr *MI, int OpNum,
126 void printShiftImmOperand(const MachineInstr *MI, int OpNum,
127127 raw_ostream &O);
128128
129129 void printThumbS4ImmOperand(const MachineInstr *MI, int OpNum,
679679 O << ARM_MB::MemBOptToString(val);
680680 }
681681
682 void ARMAsmPrinter::printSatShiftOperand(const MachineInstr *MI, int OpNum,
682 void ARMAsmPrinter::printShiftImmOperand(const MachineInstr *MI, int OpNum,
683683 raw_ostream &O) {
684684 unsigned ShiftOp = MI->getOperand(OpNum).getImm();
685685 ARM_AM::ShiftOpc Opc = ARM_AM::getSORegShOp(ShiftOp);
693693 O << ", asr #";
694694 break;
695695 default:
696 assert(0 && "unexpected shift opcode for saturate shift operand");
696 assert(0 && "unexpected shift opcode for shift immediate operand");
697697 }
698698 O << ARM_AM::getSORegOffset(ShiftOp);
699699 }
295295 let PrintMethod = "printPCLabel";
296296 }
297297
298 // shift_imm: An integer that encodes a shift amount and the type of shift
299 // (currently either asr or lsl) using the same encoding used for the
300 // immediates in so_reg operands.
301 def shift_imm : Operand {
302 let PrintMethod = "printShiftImmOperand";
303 }
304
298305 // shifter_operand operands: so_reg and so_imm.
299306 def so_reg : Operand, // reg reg imm
300307 ComplexPattern
18041811
18051812 // Signed/Unsigned saturate -- for disassembly only
18061813
1807 def sat_shift : Operand {
1808 let PrintMethod = "printSatShiftOperand";
1809 }
1810
1811 def SSAT : AI<(outs GPR:$dst), (ins i32imm:$bit_pos, GPR:$a, sat_shift:$sh),
1814 def SSAT : AI<(outs GPR:$dst), (ins i32imm:$bit_pos, GPR:$a, shift_imm:$sh),
18121815 SatFrm, NoItinerary, "ssat", "\t$dst, $bit_pos, $a$sh",
18131816 [/* For disassembly only; pattern left blank */]> {
18141817 let Inst{27-21} = 0b0110101;
18221825 let Inst{7-4} = 0b0011;
18231826 }
18241827
1825 def USAT : AI<(outs GPR:$dst), (ins i32imm:$bit_pos, GPR:$a, sat_shift:$sh),
1828 def USAT : AI<(outs GPR:$dst), (ins i32imm:$bit_pos, GPR:$a, shift_imm:$sh),
18261829 SatFrm, NoItinerary, "usat", "\t$dst, $bit_pos, $a$sh",
18271830 [/* For disassembly only; pattern left blank */]> {
18281831 let Inst{27-21} = 0b0110111;
15221522
15231523 // Signed/Unsigned saturate -- for disassembly only
15241524
1525 def t2SSAT: T2I<(outs rGPR:$dst), (ins i32imm:$bit_pos, rGPR:$a, sat_shift:$sh),
1525 def t2SSAT: T2I<(outs rGPR:$dst), (ins i32imm:$bit_pos, rGPR:$a, shift_imm:$sh),
15261526 NoItinerary, "ssat", "\t$dst, $bit_pos, $a$sh",
15271527 [/* For disassembly only; pattern left blank */]> {
15281528 let Inst{31-27} = 0b11110;
15431543 let Inst{7-6} = 0b00; // imm2 = '00'
15441544 }
15451545
1546 def t2USAT: T2I<(outs rGPR:$dst), (ins i32imm:$bit_pos, rGPR:$a, sat_shift:$sh),
1546 def t2USAT: T2I<(outs rGPR:$dst), (ins i32imm:$bit_pos, rGPR:$a, shift_imm:$sh),
15471547 NoItinerary, "usat", "\t$dst, $bit_pos, $a$sh",
15481548 [/* For disassembly only; pattern left blank */]> {
15491549 let Inst{31-27} = 0b11110;
477477 O << ARM_MB::MemBOptToString(val);
478478 }
479479
480 void ARMInstPrinter::printSatShiftOperand(const MCInst *MI, unsigned OpNum,
480 void ARMInstPrinter::printShiftImmOperand(const MCInst *MI, unsigned OpNum,
481481 raw_ostream &O) {
482482 unsigned ShiftOp = MI->getOperand(OpNum).getImm();
483483 ARM_AM::ShiftOpc Opc = ARM_AM::getSORegShOp(ShiftOp);
491491 O << ", asr #";
492492 break;
493493 default:
494 assert(0 && "unexpected shift opcode for saturate shift operand");
494 assert(0 && "unexpected shift opcode for shift immediate operand");
495495 }
496496 O << ARM_AM::getSORegOffset(ShiftOp);
497497 }
5757 void printBitfieldInvMaskImmOperand(const MCInst *MI, unsigned OpNum,
5858 raw_ostream &O);
5959 void printMemBOption(const MCInst *MI, unsigned OpNum, raw_ostream &O);
60 void printSatShiftOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
60 void printShiftImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
6161
6262 void printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
6363 void printThumbITMask(const MCInst *MI, unsigned OpNum, raw_ostream &O);
607607 IMM("jt2block_operand");
608608 IMM("t_imm_s4");
609609 IMM("pclabel");
610 IMM("sat_shift");
610 IMM("shift_imm");
611611
612612 MISC("brtarget", "kOperandTypeARMBranchTarget"); // ?
613613 MISC("so_reg", "kOperandTypeARMSoReg"); // R, R, I