llvm.org GIT mirror llvm / 22f3cb0
[X86] Refactor X86ISelDAGToDAG::SelectAtomicLoadArith - NFC Summary: Mostly renaming the (not very explicit) variables Tmp0, .. Tmp4, and grouping related statements together, along with a few lines of comments for the surprising parts. No functional change intended. Test Plan: make check-all Reviewers: jfb Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5088 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216768 91177308-0d34-0410-b5e6-96231b3b80d8 Robin Morisset 6 years ago
1 changed file(s) with 21 addition(s) and 14 deletion(s). Raw diff Collapse all Expand all
17541754 SDValue Chain = Node->getOperand(0);
17551755 SDValue Ptr = Node->getOperand(1);
17561756 SDValue Val = Node->getOperand(2);
1757 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
1758 if (!SelectAddr(Node, Ptr, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4))
1757 SDValue Base, Scale, Index, Disp, Segment;
1758 if (!SelectAddr(Node, Ptr, Base, Scale, Index, Disp, Segment))
17591759 return nullptr;
17601760
17611761 // Which index into the table.
18091809 Opc = AtomicOpcTbl[Op][I32];
18101810 break;
18111811 case MVT::i64:
1812 Opc = AtomicOpcTbl[Op][I64];
18131812 if (isCN) {
18141813 if (immSext8(Val.getNode()))
18151814 Opc = AtomicOpcTbl[Op][SextConstantI64];
18161815 else if (i64immSExt32(Val.getNode()))
18171816 Opc = AtomicOpcTbl[Op][ConstantI64];
1818 }
1817 } else
1818 Opc = AtomicOpcTbl[Op][I64];
18191819 break;
18201820 }
18211821
18221822 assert(Opc != 0 && "Invalid arith lock transform!");
18231823
1824 // Building the new node.
18241825 SDValue Ret;
1826 if (isUnOp) {
1827 SDValue Ops[] = { Base, Scale, Index, Disp, Segment, Chain };
1828 Ret = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops), 0);
1829 } else {
1830 SDValue Ops[] = { Base, Scale, Index, Disp, Segment, Val, Chain };
1831 Ret = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops), 0);
1832 }
1833
1834 // Copying the MachineMemOperand.
1835 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1836 MemOp[0] = cast(Node)->getMemOperand();
1837 cast(Ret)->setMemRefs(MemOp, MemOp + 1);
1838
1839 // We need to have two outputs as that is what the original instruction had.
1840 // So we add a dummy, undefined output. This is safe as we checked first
1841 // that no-one uses our output anyway.
18251842 SDValue Undef = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,
18261843 dl, NVT), 0);
1827 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1828 MemOp[0] = cast(Node)->getMemOperand();
1829 if (isUnOp) {
1830 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Chain };
1831 Ret = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops), 0);
1832 } else {
1833 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Val, Chain };
1834 Ret = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops), 0);
1835 }
1836 cast(Ret)->setMemRefs(MemOp, MemOp + 1);
18371844 SDValue RetVals[] = { Undef, Ret };
18381845 return CurDAG->getMergeValues(RetVals, dl).getNode();
18391846 }